JPH0235543A - Page table entry invalidating device - Google Patents

Abstract

PURPOSE:To evade unnecessary partial deletion and to shorten a retrieval time by sending the real address of an object page and a page index indicated with an instruction to the CPU of this system and other CPUs and invalidating an entry in an address conversion buffer wherein an object actual address is coincident by each CPU. CONSTITUTION:An address to be deleted partially and a page index part PX are set in registers 5 and 7 and a partial deletion request is sent to all CPUs through an MCU. Each CPU receives the address by a register 6 and the page index part PX by a register 8. Then the contents of the register 6 holding the actual address to be deleted are compared by a comparing circuit 12 with the contents of the register 4 holding the read result of the address conversion buffer TLB and only when there is a coincident entry, its significant bit is set to 0, thus performing the partial deletion. Address generation for this retrieval is performed by a control circuit 9.

Description

[Detailed Description of the Invention] [Summary] This invention aims to avoid unnecessary partial deletion and shorten the time required for searching regarding page table entry invalidation for invalidating a specific page of a virtual address. , sends the actual address of the target page and the page index specified by the instruction to the local CPU and other CPUs 1. : send,
Next, each CPIJ is configured to partially search the address translation buffer based on the page index and invalidate the entry in the address translation buffer that matches the target real address.

[Industrial Application Field] The present invention relates to page table entry invalidation (■pTE; lnvalidate) for invalidating a specific page of a virtual address in a virtual computer system.
The present invention relates to a device that executes a Page Table [:ntry) instruction, and particularly relates to partial deletion of an address translation buffer (TLB) accompanying the execution of page table entry invalidation.

Today, virtual computer systems are widely adopted to enable programming without being limited by the capacity of storage devices, and to enable multiple programming in which multiple programs are placed on a storage device and executed alternately. ing. In such a system, the virtual address space is divided into units (called pages), and each page of virtual addresses is converted to a real address according to an address conversion table, so that it can be allocated arbitrarily on the storage device. There is.

The address translation table is under the control of the operating system (<O8), but when it becomes impossible to place a page of virtual addresses on the storage device, the O8
loads this area into auxiliary storage, rewrites the address translation table, and creates an address translation buffer (TLB) that holds part of the correspondence between virtual addresses and real addresses created according to the previous address translation table.
It is necessary to delete the entry. For example, in the IBM computer system 370, instructions for rewriting the address translation table and partially deleting the address translation buffer (TLB) are prepared as IPTE instructions.

[Prior Art] The process of converting a virtual address to a real address in the IBM computer system 370 is as follows. As shown in FIG. 6, the segment size and page size of the virtual address are determined by the value of control register 0 (referred to as CRO) as shown in FIG. 6(a). Note that the virtual address is the segment index section <SX>
, a page index section (PX), and a byte index section (BX) ((b) in the same figure).

The address of the segment table entry (STE) shown in (d) of the same figure is obtained from the segment table origin (STO) in the control register CR1 ((C) of the same figure) and the above-mentioned SX, and the page table origin (PTO) in the STE is found. ) and the PX, the page table entry (PTE) address shown in FIG.

In the rPTE instruction, PTO and PX used in the address conversion process are given as operands, and based on these, the address of P'TE is determined, the page invalid bit in PTE is set to 1, and the following ( 1) or 4)
The address translation buffer (T
LB) entry for all central processing bags! (C
PU). (1) C that issued the IPTE instruction
Segment and page size indicated by CRO of PU (2
>PTO specified by the operand of the IPTE instruction (3) PX specified by the operand of the IPTE instruction (4) PTE determined from the operand of the IPTE instruction
In the conventional method, the contents of the PTE are read from the PTE address obtained from the operand, the page invalid bit is rewritten to 1, and this is stored in the PTE address. TLB to be partially deleted
The partial deletion instruction is sent to the local CPU and other CPUs as the real address of
Send to PU.

As a result, each CPU sequentially searches TLB entries, and when a TLB entry having a real address part that matches the specified real address is found, the valid bit of this entry is turned off.

This LB search can be performed independently of pipeline-controlled operations such as instruction fetch and operand access within the CPU. However, if the real address of the TLB fetch simulation for pipeline control access matches the real address targeted for partial deletion of the TLB, that real address is invalid, so until all entries in the TLB have been searched. It is necessary to stop the operation of the vibration line.

[Problems to be Solved by the Invention] However, in the conventional method as described above, TLB entries are invalidated only by the page frame real address PFRA, which results in deletion of more TLB entries than necessary. A decrease in TLB hit rate occurs. In addition, the TLB search performed for partial TLB deletion requires a long time because it needs to be performed for all entries, and during this time, if the real address required by the pipeline matches the target of partial deletion, There is a problem in that the vibration line stops moving and the throughput drops.

Furthermore, when requests for partial deletion of the TLB occur one after another, the requests cannot be held (thus, it becomes necessary to delete the entire TLB, which causes a problem that the hit rate of the TLB decreases significantly.

The purpose of the present invention is to solve these problems, and by limiting the scope of TLB searches for partial deletions, unnecessary partial deletions can be avoided and the time required for searches can be reduced. An object of the present invention is to provide a page table entry invalidation device that can be shortened.

[Means for Solving the Problems 1] FIG. 1 is an explanatory diagram of the original page table entry invalidation device of the present invention. In the figure, 1 is an instruction control unit (I unit) that generates a page table entry (PTE) address and outputs a partial deletion request, and 3 has a set-associative configuration and is addressed by some bits of a virtual address. address translation buffer (TLB)
>, 2 is an address register that outputs an address for accessing the address translation buffer 3 into which the real address is entered, 4 is a register that reads and holds the real address of the address translation buffer 3, and 5 is for accessing the memory control unit MCtJ. 6 is an address translation buffer y from the memory control unit MCU.
(TLB) This is a register that receives and holds an address as a partial deletion request.

7 is the page index section (PX
) to the memory control unit MCU; 8 is a register for receiving and holding the page index part (PX) as a request for partial deletion of the address translation buffer from the memory t111-unit MC (J; 9 is a register for holding the page This is a control circuit for generating an address necessary for partial deletion based on the index section (PX) and setting it in the address register 2.

10 is a selection circuit that switches and selects the output of I unit 1 or control circuit 9; 11 is a selection circuit that switches and selects the output of address register 2 or register 4; and 12 is a comparison circuit that detects a match between the outputs of register 4 and register 6. It is a circuit.

[Effect]

In the present invention, the real address of the target page and the page index specified by the instruction are sent from the register (7) to the own CPIJt3 and other CPUs.

Next, each CPU partially searches the address translation buffer based on the page index, and invalidates the entry in the address translation buffer that matches the target real address.

In the I PTE instruction, first the page table entry PT
It is necessary to set the page invalid bit of E to 1. Therefore, PTO and PX, which are operands of the 1PTE instruction, are added to generate a PTE address, which is sent out from unit 1. Fetch the main memory at this address, rewrite the page invalid bit position in the PTE to 1, and memory control unit MCLII! Store it in main memory using

Next, a partial deletion request for address translation back 7 TLB is sent from I unit 1 at the same address.

At this time, the PX added to the upper position is temporarily held in register 7, and at the same time, the page table entry PTE is
Access to obtain PFRA.

This is the address of the page to be partially deleted.

This address is set in register 5 and a partial deletion request is sent to all CPUs via the MCU. Each CPt1 sends an address and PX as a partial deletion request. The address is received by register 6, and the PX is received by register 8.

Here, assuming that the TLB consists of 512 sets and is addressed by 9 bits, bits 11 to 19 of the virtual address, when the page size is 4 bytes, bit 11 of the address for accessing the TLB is SX The least significant bits of the address, bits 12 to 19, correspond to all eight pits of PX.

Therefore, in this case, only two sets are searched, and the comparison circuit 12 compares the register 6 containing the real address to be deleted and the register 4 containing the TLB read result,
Partial deletion can be performed by setting the valid bit to 0 only when there is a matching entry. Address generation for this search is performed by the control circuit 9.

[Example] Figure 2 is a configuration diagram showing an example of the device of the present invention.
The overall configuration of the peripheral area is shown. Also, T in Figures 3 and 4.
The internal configuration of LBl and TLB2 is shown.

The address of the 7 etch request from I unit 1 is set in the address register 21, and the first TL is set at this address.
B22 (abbreviated as TLBl) is searched. Primer IJ (PRrMARY) with the same bit configuration is in TLB1.
,! : There is an alternate (ALTERNATE>), and the selection circuit 24 selects the real address of the matching one of the two ways.

Next, the real address passes through the selection circuit 25 and is sent to the MCU.
The address register (MSAR) 26 or local buffer storage (Local buffer storage) 26 for accessing the main memory
age> is set in the address register 27 for accessing.

Next, the fetched data from the main memory or local buffer storage is selected by the selection circuit 28 and then set in the data register 29.

If the two ways do not match, the address conversion circuit 31 determines the real address for the virtual address in the address register 21 according to the address conversion table, and registers it in TLB1.

FIG. 3 is a diagram showing the internal structure of TLB1.

The TLBI consists of 512 sets addressed by 9 bits 11 to 19 of the address register 21, each set consists of two ways, and each entry consists of a valid bit, an ID field, a virtual address field, and a real address field. ing. ■When searching TL8 when accessing from the unit, bit 0 of the virtual address in the address register 21
0 to 10 and the current ID31 (for example, STo, etc. that identifies the virtual space), as well as the valid bit in the TLB, ID
The comparison circuit 32 compares the part and the virtual address part to detect a match. Bits 20 to 31 of the address register 21 are added to the real address portion of the matching TLB by the addition circuit 36 to obtain the real address. Comparison circuit 33.35
This is to prevent the real address (PPAR) to be partially deleted from being used for access from the unit before it is partially deleted, and when a match is detected, the real address (PPAR) to be partially deleted is Access from the r unit is prohibited.

The second TLB 42 (hereinafter abbreviated as TLB 2) shown in FIG. 4 performs the process of partially deleting a TLB independently of the access from the above-mentioned unit (2). T'L
B2, like TLB1, consists of 512 sets addressed by 9 bits 11-19 of address register 41, each set containing PRIMARY and ALTER.
It consists of two ways: NATE. However, T
It is a partial copy of LBl, with each entry consisting only of valid bits and a real address part. When the address register 41 is given a search address, TLB2
is read out, and the comparison circuits 43 and 44 select the real address (partial purge) to be partially deleted.
Address Re5ister: PPAR)
A comparison is made with 45. When a match is detected here,
At that point, the valid bit of the matching entry is set to 0 for TLBI and TLB2.

Next, the operation of partial TLB deletion processing when executing an IPTE instruction will be described. In Figure 2, ■Unit 1
Then, a value obtained by adding 8 bits of PX to bits 00 to 07 of the PTE address is set in the At1nos register. At the next timing, bits 00-07 are set in the Px register 23, and the value with bits 00-07 forced to O passes through the selection circuit 25 and is set in the MSAR 26 or address register 27. PTEs fetched from main memory or from LBS at MCU exit
is placed in the data register 29. PFAR in PTE
The value of the PX register 23 is merged (into bits 24 to 31) with the value of the PX register 23 by the merge circuit 30, and the result passes through the selection circuit 25 and is set in the MSAR 26. A value containing the real address and PX of the page to be partially deleted is sent to all CPUs via the MCU along with a partial deletion request instruction.

In each CPU, this request is received by the PPAR 40, and the second TLB 42 is used to perform partial deletion processing.

FIG. 5 shows details of the I11 control circuit 9 that generates a search address for partial deletion. Bit 2 of PPAR40
4 to 31 are the values of PX, which are set to bits 12 to 1 of the address register 56 via the register 55. This part remains unchanged during the search. The other upper bits of the address register 56 (in this example, only bit 11 is one bit) are set via the register 54. At the start of partial deletion, the selection circuit 52 selects reset for the register 54, and the value becomes O. From then on, the value incremented by the adder 51 is used as the register 54.
Set to 4.

Also, when the incremented value overflows,
An overflow signal is output from the terminal 53, indicating that the necessary search has been completed. In this embodiment, the search ends after two searches.

[Effects of the Invention] As explained above, according to the present invention, when an IPTE instruction is executed, the real address of the target page and the PX specified by the instruction are sent to the own CPU and other CPUs (J, and each C
In the PU, by partially searching the TLB based on the PX and invalidating the TLB entry that matches the target real address, unnecessary partial deletion can be avoided and partial deletion can be performed in a short time. can be terminated.

Nowadays, there is a need to increase the hit rate of the first LB in order to improve CPU performance, and for this purpose it is necessary to increase the number of entries of the first L8. There are two ways to do this: increasing the number of entries that can be accessed simultaneously, that is, increasing the number of ways, and increasing the number of sets. Although the number of sets can be easily achieved by increasing the capacity in the depth direction of the RAM that physically constitutes the TLB, the TLB search time associated with partial deletion has been a problem. This problem is solved by adopting the present invention.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a configuration diagram of the T18 peripheral part showing an embodiment of the present invention, FIG. 3 is a diagram showing the internal configuration of the first TLB, and FIG. FIG. 5 is a diagram showing the internal configuration of the second LB, FIG. 5 is a diagram showing the circuit configuration for generating an address for TLB search, and FIG. 6 is an explanatory diagram for explaining the format of the address conversion table. In Figure 1, 1 is an instruction control unit, 2 is an address register, 3 is an address translation buffer, 4 is a comparison circuit, 5 is an address register, 6.7.8 is a register, 9 is a control circuit, io and il are selections. 12 is a comparison circuit. Patent applicant: Fujitsu Limited
Ceremony Attorney Patent Attorney Ijima
Fuji Jigai 1 person MCI From MCU to JR2 (D T L B G inner waf J, e

Claims (1)

[Claims] An address conversion buffer is provided in the central processing unit, and 1
A page table entry invalidation device used in a system comprising one or more central processing units and executing a page table entry invalidation (IPTE) instruction, which is an instruction to invalidate a specific page at a virtual address. , an instruction control unit (1) that generates the address of a page table entry (PTE) and outputs a partial deletion request, and an address translation buffer (1) that has a set-associative configuration and is addressed by some bits of a virtual address.
3) and an address register (2) that outputs the address to access the address translation buffer (3) that contains the real address.
), a register (4) that reads and holds the real address of the address translation buffer (3), a register (5) that holds an address for accessing the memory control unit (MCU), and a register (5) that holds the address for accessing the memory control unit (MCU). ) for receiving and holding an address as a partial address translation buffer deletion request from ), and for sending the page index section (PX) to the memory control unit (MCU) when executing the page table entry invalidation (IPTE) instruction. holding register (7) and the page index section (PX) as a request to delete part of the address translation buffer from the memory control unit (MCU)
); a control circuit (9) for generating an address necessary for partial deletion based on the page index section (PX) and setting it in the address register (2); Command control unit (
1) or a selection circuit (10) that switches and selects the output of the control circuit (9); a selection circuit (11) that switches and selects the output of the address register (2) or the register (4); and the register (4). and a comparison circuit (12) that detects a match between the outputs of the register (6) and sends the real address of the target page and the page index specified by the instruction from the register (7) to the own CPU and other CPUs. ,
Next, each CPU partially searches the address translation buffer based on the page index, and invalidates the entry in the address translation buffer that matches the target real address. conversion device.