JP3465770B2 - Semiconductor memory test equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory test device, and more particularly to a semiconductor memory test device capable of executing fail counting at high speed in synchronization with a system clock even during a memory test.

[0002]

2. Description of the Related Art A conventional example of a semiconductor memory test apparatus will be described with reference to FIG. The address signal ADS, the data signal TPD, and the control signal CS generated by the pattern generator 2 are supplied to the waveform shaper 3, where they are waveform-shaped and then applied to the memory under test MUT.
The logic comparator 4 compares the data RD read from the memory under test MUT with the expected value signal ED applied from the pattern generator 2 to determine whether the memory under test MUT is pass or fail. The fail memory 5 outputs the fail signal FS output from the logical comparator 4 to the fail fetch address signal F input from the pattern generator 2.
It is stored for each address according to ADS. The above series of operations is performed in synchronization with the clock CLK applied from the timing generator 1 to each unit.

The internal structure of the fail memory 5 will be described with reference to FIG. The fail bit memory 52 accommodated in the fail memory 5 has the same storage capacity as the memory under test MUT, has the same address, and corresponds to the number of fail bits to be input.
It has an in and a write terminal / WE. The address selector 55 selects the address signal input from the pattern generator 2 and the R / W address input from the system bus, and applies it to the address input terminal Ain of the fail bit memory 52. The WE control unit 53 generates a write signal from the fail signal FS input from the logical comparator 4, and supplies this to the write terminal / WE. The fail adder 56 adds the fail signals read from the fail bit memory 52.

Next, the operation of the fail memory 5 will be described. When the memory test is started and the fail is measured, the fail signal FS is input to the fail memory 5 from the logical comparator 4 of the memory testing device. The fail signal FS is applied to the data input terminal Din of the fail bit memory 52 that stores a fail and also to the WE control unit 53 that controls writing to the fail bit memory 52. The address signal applied from the pattern generator 2 of the memory test device is multiplexed with the R / W address input from the system bus in the address selector 55, and the fail bit memory 5
2 is applied to the address input terminal Ain. The WE control unit 53 generates a write signal to the fail bit memory 52 and supplies it to the write terminal / WE only in the cycle in which the fail occurs. Then, after the memory test is completed, the address required for reading the content of the fail stored in the fail bit memory 52 or adding the total fail generated in the memory under test MUT is from the system bus. Supply is applied. For fail addition, the fail adder 56 adds the number of bits for which the output of the fail bit memory 52 is "1" for each address.

By the way, the total number of failures and the number of failures for each data bit can be performed only after all the memory tests have been completed. This is because, in the memory test by the memory test device, it is usual that the test is performed a plurality of times for the same address. Therefore, adding a fail input while performing the test is the same. This is because fail will be added multiple times for the address. Therefore, if the read operation is performed before the write operation of the test result, it is possible to avoid multiply adding the failures generated at the same address among the failures generated in the memory under test MUT. A semiconductor memory test apparatus has been proposed which is capable of performing a memory test in this manner and simultaneously performing a fail count.
This will be described with reference to FIGS. 6 and 7.

In FIG. 6, in the fail memory 5 of FIG. 5, an AND gate 57 is interposed between the read terminal Dout of the fail bit memory 52 and the fail adder 56,
The read signal of the fail bit memory 52 is input to the inverting input of the AND gate 57, and the fail signal FS input from the logical comparator 4 is input to the non-inverting input of the AND gate 57. Here, the fail bit memory 52 for storing the fail stores the logical value “0” in all areas in advance before starting the test of the memory under test MUT.
Initialize and clear. In the memory test, the fail bit memory 52 is accessed by the address applied from the pattern generator 2 and the data corresponding to the accessed address is read. The output read from the fail bit memory 52 is input to the inverting input of the AND gate 57, and the logical comparator 4 to the AND gate 5
AND with the fail signal FS input to the non-inverting input of 7.
Is taken. When the output read from the fail bit memory 52 is "0", that address indicates that the fail has not occurred in the previous test,
Therefore, the fail signal FS input from the AND gate 57 is directly output to the fail adder 56 and added. When the output of the fail bit memory 52 is "1", that address indicates that a fail has occurred in the previous test, and therefore the AND gate 57 is used.
Outputs "0" and no addition is performed. The fail adder 56 is an AND gate 5 which is a fail selector.
The number of bits whose signal output from 7 is "1" is added in synchronization with the operation clock. FIG. 7 is a timing chart of the above operation of the fail bit memory 52 of FIG.

[0007]

The semiconductor memory test apparatus shown in FIG. 6 is capable of simultaneously performing a memory test and simultaneously performing a fail count. However, when a fail is stored, both a read operation and a write operation are performed. Since it is premised on performing both together, the cycle time of the fail memory 5 is the time obtained by adding the read cycle and the write cycle of the fail bit memory 52 that stores the fail. Is not preferable in achieving higher speed.

The present invention provides a semiconductor memory test apparatus which solves the above-mentioned problem of performing fail counting at high speed in synchronization with a system clock even during a memory test.

[0009]

In a semiconductor memory test apparatus having a fail memory 5 having the same storage capacity as that of a memory under test MUT and storing fail information of a semiconductor memory test, the fail memory 5 receives an input address. The first flip-flop FFA1 to the third flip-flop FFA3, which are cascade-connected with each other for cycle-shifting a signal, have three flip-flops, and the first flip-flops are cascade-connected with each other for cycle-shifting an input fail signal. 4 of the first fail bit memory 52A to the fourth fail bit memory 52D, each of which has three flip flops FFD1 to FFD3 of the third flip flop FFD3.
A first fail bit memory 52A to a fourth fail bit memory 52 by selectively switching each cycle-shifted address signal.
The first address multiplexer MUX1 to the fourth address multiplexer MUX4 for applying to D are provided, and the first address multiplexer MUX1 to the fourth address multiplexer MUX4 are provided.
A read cycle instruction flip-flop FFS for outputting a selection signal of the address multiplexer MUX4 and a signal for determining a read cycle and a write cycle,
Based on the input fail signal, the first fail bit memory 52A to the fourth fail bit memory 52
It has a WE control unit 53 for generating and outputting a write signal for D, and adds the outputs of the first fail bit memory 52A to the fourth fail bit memory 52D, the input fail signal and the input address signal as inputs. A semiconductor memory test apparatus having a select gate circuit for selecting a fail bit memory output to be formed and a fail adder 56 for counting fail data output from the select gate circuit in synchronization with a system clock was constructed.

The selection gate circuit of the above semiconductor memory test apparatus has a first NOR gate 581 which receives both outputs of the first fail bit memory 52A and the second fail bit memory 52B as input. A second NOR gate 582 having both outputs of the third fail bit memory 52C and the fourth fail bit memory 52D as inputs.
And a first AND gate 571 having three outputs of the output of the second flip-flop FFD2 for cycle-shifting the fail signal, the output of the read cycle instruction flip-flop FFS, and the output of the first NOR gate 581. And an address match detection ENOR gate 583, which receives the output of the first flip-flop FFA1 and the output of the second flip-flop FFA2 as input, and which outputs the output of the address match detection ENOR gate 583. It has a count inhibit NAND gate 574 that receives the output of a second 'flip-flop FFD2 that shifts the fail signal as a input, and a count inhibit NAND gate 574 and a first' flip-flop FFD1 that performs the cycle shift of the fail signal. Input output The third AND gate 57
And a second AND gate 572 having three outputs, the output of the third AND gate 573, the output of the read cycle instruction flip-flop FFS, and the output of the second NOR gate 582. A memory test device was constructed.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor memory test apparatus according to the present invention has, as its fail memories, two fail bit memories for counting odd cycle failures and two fail bit memories for counting even cycle failures. By adopting a pipeline structure and performing the fail storing operation and the fail counting operation in parallel, the fail counting is performed at high speed in synchronization with the system clock even during the memory test.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram for explaining a fail memory used in the semiconductor memory testing device of the present invention. The semiconductor memory test apparatus of the present invention has, as its fail memory 5, two first fail bit memories 52A and second fail bit memories 52B for reading and counting the fail of odd cycles and for even cycles. Third fail bit memory 52C and fourth fail bit memory 52 for reading and counting fail
By having two of D and performing the fail storing operation and the fail counting operation in parallel by adopting the pipeline structure, the fail counting is performed at high speed in synchronization with the system clock even during the memory test. To do.

The fail memory 5 of the semiconductor memory testing device of the present invention will be described below. The address signal AD input to the fail memory 5 is the first flip-flop F.
The first address multiplexer MUX1 to the fourth address multiplexer MUX are cycle-shifted by FA1 to the third flip-flop FFA3.
It is input to the first fail bit memory 52A to the fourth fail bit memory 52D via the No. The fail signal FS input to the fail memory 5 is cycle-shifted by the first ′ flip-flop FFD1 to the third ′ flip-flop FFD3, and then the first fail bit memory 52A to the fourth fail bit memory 52D. Entered in. The WE control unit 53 generates and outputs a write signal / WE for the first fail bit memory 52A to the fourth fail bit memory 52D from the input fail signal FS.

FIG. 2 is a timing chart showing the above operation timing for an arbitrary cycle n or more. All the fail bit memories 52 execute two consecutive cycles in the order of read cycle and write cycle. Specifically, the first cycle is the read cycle and 2
The second cycle is a write cycle. As for the first fail bit memory 52A, the address An is read in the read cycle, and the fail F generated in the address An in the write cycle in the cycle is read.
Write n. Thereafter, similarly, the operations of reading the address An + 2 and writing the fail Fn + 2 to the address An + 2, reading the address An + 4 and writing the fail Fn + 4 to the address An + 4 are repeated.

The second fail bit memory 52B reads the address An in the read cycle and writes the fail Fn + 1 generated in that cycle to the address An + 1 in the write cycle. Thereafter, similarly, the address An + 2 is read and the address An + 3 is read.
The operation of writing the fail Fn + 3 to the address, reading the address An + 4, and writing the fail Fn + 5 to the address An + 5 is repeated.

The third fail bit memory 52C reads the address An + 1 and writes the fail Fn generated in the cycle to the address An. Thereafter, similarly, the address An + 3 is read and the address An + 2 is read.
The operation of writing the fail Fn + 2 to, the address An + 5, and writing the fail Fn + 4 to the address An + 4 is repeated.

The fourth fail bit memory 52D reads the address An + 1 and writes the fail Fn + 1 generated in the cycle to the address An + 1. Hereinafter, similarly, the operation of reading the address An + 3, writing Fn + 3 to the address An + 3, reading the address An + 5, and writing the fail Fn + 5 to the address An + 5 is repeated.

By the operation as described above, the first fail bit memory 52A and the third fail bit memory 52C store the fail of odd cycles of nth, (n + 2), (n + 4). , Second fail bit memory 52B and fourth fail bit memory 5
For 2D, the (n + 1), (n + 3), (n + 5) ...
・ Fail of even cycle of is stored. That is, the first
If the fail bit memory 52A and the second fail bit memory 52B of No. 1 are regarded as one block, this block must be written if a failure occurs in consecutive nth and (n + 1) th cycles. become. Third fail bit memory 52C
When the fourth fail bit memory 52D is regarded as one block, the nth and (n +
1) If a failure has occurred in the cycle, similarly, this failure is always written.
Therefore, the first fail bit memory 52A and the second fail bit memory 52A
By reading the block of the fail bit memory 52B, it is possible to always read all the fail information generated in any cycle before that. And the third
Similarly, on the side of the fail bit memory 52C and the side of the fourth fail bit memory 52D, it is possible to read all the fail information generated in any cycle before that. The present invention takes advantage of this by performing a fail detection for odd cycles on a block of the first fail bit memory 52A and the second fail bit memory 52B for determining whether or not this is an address at which a fail has occurred before. The even number of cycles of fail detection are performed by the blocks of the third fail bit memory 52C and the fourth fail bit memory 52D.

The above fail counting method will be described with reference to the timing chart of FIG. To count the number of fails in the odd cycle, the output of the second flip-flop FFA2 is changed to the address multiplexer MU.
First fail bit memory 52A and second fail bit memory 52B via X1 and MUX2.
When the address An is input to, the data AQn and BQn corresponding to this address An are read, and both are ORed by the first NOR gate 581 to form the first AND gate.
It is input to the gate 571. First AND gate 571
Is an AND of the output of the NOR gate 581, the output of the read cycle instruction flip-flop FFS indicating that the cycle is a read cycle, and the output of the second 'flip-flop FFD2 indicating the fail signal of the cycle. Take And the first AND gate 5
71 denotes the first fail bit memory 52A and the second fail bit memory 52A.
When "0" indicating that a fail has not been previously stored is read from both fail bit memories 52B of the above, "1" is input from the first NOR gate 581 and the other two outputs are output. The AND is taken, "1" is output to the fail adder 56, and the fail is counted here in synchronization with the system clock. Thereafter, the same operation is performed every time the addresses An + 2, An + 4, ... Are input. That is, in the read cycle, the first fail bit memory 52A and the second fail bit memory 5 are
The input fail is added only when "1" is not read from any of 2B.

For counting the number of fails in the even cycles, when the address An + 1 is input to the third fail bit memory 52C and the fourth fail bit memory 52D, the data AQn + 1 and BQn + corresponding to the addresses are input.
1 is read, secondly ORed by the NOR gate 582 and input to the second AND gate 572. Second AN
The D gate 572 outputs the output of the NOR gate 582, the output of the read cycle instruction flip-flop FFS indicating that the cycle is a read cycle, and the third A
The three outputs of the ND gate 573 are ANDed. And A
The output of the ND gate 572 is input to the fail adder 56, and the fail is counted in synchronization with the system clock. After that, the same operation is performed for the addresses An + 3 and An + 5.
Each time "..." is entered.

Here, in counting the number of fails in even cycles, a third AND gate 573 is provided to directly output the output of the first 'flip-flop FFD1 to the second AND gate.
The reason why the gate 572 is not input will be described. If the same address is accessed in consecutive cycles from odd cycle to even cycle from the nth cycle to the (n + 1) th cycle, and a failure occurs in both cycles at that time, the fail adder 56 should count extra. become. Therefore, an address match detection EN for detecting that the addresses match in consecutive cycles
An OR gate 583, a count prohibiting NAND gate 574 that unconditionally prohibits counting of fail in even cycles if a fail occurs in odd cycles at that time, and AND
A gate 573 is provided to avoid extra counting.

[0022]

As described above, according to the semiconductor memory test apparatus of the present invention, as fail memories, two fail bit memories that count odd cycle failures and two fail bits that count even cycle failures are used. By having a bit memory and performing the fail storing operation and the fail counting operation in parallel by adopting a pipeline structure, the fail counting can be performed at high speed during a memory test.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an example.

FIG. 2 is an operation timing chart of the embodiment.

FIG. 3 is an operation timing chart of the embodiment.

FIG. 4 illustrates a semiconductor memory test device.

FIG. 5 is a diagram illustrating a conventional example of a fail memory.

FIG. 6 is a diagram illustrating another conventional example of a fail memory.

7 is an operation timing chart of the conventional example of FIG.

[Explanation of symbols]

5 Fail memories 52A to 52D First to fourth fail bit memories 53 WE control unit 56 Fail adders FFA1 to FFA3 First to third flip-flops FFD1 to FFD3 First 'to third' flip-flops FFS Read cycle Instruction flip-flops MUX1 to MUX4 First to fourth address multiplexers

Claims (2)

(57) [Claims] 1. A semiconductor memory test apparatus having a fail memory having the same storage capacity as a memory under test and storing fail information in a semiconductor memory test, wherein the fail memory cyclically shifts an input address signal. A first flip-flop or a third flip-flop which has three flip-flops, which are cascade-connected, of the first flip-flop and the third flip-flop, and which serially shifts a fail signal to be input, which are cascade-connected to each other. Has three flip-flops, and has four fail bit memories, a first fail bit memory to a fourth fail bit memory for storing fail signals, and selectively switches each cycle-shifted address signal. The first fail bit memory or the fourth fail bit Read having four first address multiplexers to fourth address multiplexers to be applied to the memory and outputting selection signals of the first address multiplexers to fourth address multiplexers and signals determining read cycles and write cycles. A cycle instruction flip-flop, and a WE control unit for generating and outputting a write signal to the first fail bit memory to the fourth fail bit memory based on the input fail signal. Fail data output from the select gate circuit, having a select gate circuit for selecting an output of the fourth fail bit memory, an input fail signal and an input address signal to select an output of the fail bit memory to be added Counting Having a fail adder performed in synchronization with a system clock, a semiconductor memory testing device, characterized in that. 2. The semiconductor memory test apparatus according to claim 1, wherein the select gate circuit has a first NOR gate that receives both outputs of the first fail bit memory and the second fail bit memory. A second NOR gate having both outputs of the third fail bit memory and the fourth fail bit memory as inputs, and the output of the second 'flip-flop for cycle-shifting the fail signal, the read cycle instruction flip-flop. Of the first flip-flop and the output of the second flip-flop for cycle-shifting the address signal. And an address match detection ENOR gate that outputs A counting-prohibited NAND gate that receives the output of a second 'flip-flop for cycle-shifting the fail signal and inputs the output of the counting-prohibition NAND gate and the output of a first' flip-flop for cycle-shifting the fail signal. The output of the third AND gate, the output of the read cycle instructing flip-flop, and the output of the second NOR gate.
A semiconductor memory test device having a second AND gate having an output as an input.