JP3141897B2 - Memory test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus for a memory used, for example, for displaying a graphic screen.

[0002]

2. Description of the Related Art There is a memory capable of high-speed writing and high-speed reading as an image display memory. As shown in FIG. 6, this memory includes a random access memory unit 1 (hereinafter, referred to as a RAM unit) and a serial access memory unit 2 (hereinafter, referred to as a SAM unit). The RAM unit 1 and the SAM unit 2 are independent. outside that can be read from or written to Te, the data D ₁ in the RAM section 1 as shown in FIG. 7, D _2, D _3, ... write the data D ₁ are written to the RAM unit 1 in the data transfer cycle, D _2, D
_3, transfers ... the SAM unit 2, which is the transfer data D
_1, D _2, D _3, ... and reading operation at high speed from the SAM unit 2 to the serial (hereinafter referred to as a read transfer operation), the serial data D ₁ at a high speed to the SAM unit 2 as shown in FIG. 8, D _2, D _3, write ... uptake, serial data D ₁ of the taken in this fast, D _2, D _3, and transfer ... to parallel to the RAM section 1 to any address of the RAM portion 1,
An operation of reading data D ₁ , D ₂ , D ₃ ,... From the RAM unit 1 (hereinafter referred to as a write transfer function) can be performed. This type of memory can perform more complicated operations, but since it is a function not directly related to the present invention, its description is omitted here.

FIG. 9 shows a schematic configuration of a conventional test apparatus for testing this type of memory. In the figure, MUT indicates a memory under test. The memory under test MUT is stored in the RAM unit 1 as described above.
And a SAM unit 2. A main timing generator 11, a main pattern generator 12, and a main logic comparator 13 are provided for the RAM unit 1.

At the time of the test of the read transfer operation, the main timing generator 11 outputs timing signals T _A and T _B ,
Enter the timing signal T _A to the main pattern generator 12, and outputs the main pattern signal P _A and the main expected value signal P _B from the main pattern generator 12. Main pattern signal P _A is input to the RAM unit 1. The test pattern signal input to the RAM unit 1 is transmitted to the SA by the read transfer operation.
The data is transferred to the M unit 2, read out serially from the SAM unit 2, and input to the sub logical comparator 23. Sub logical comparator 2
3 includes a sub expected value signal P _D from the sub pattern generator 22.
Is input, and the sub-expected value signal P _D is logically compared with the data read serially from the SAM unit 2.

On the other hand, during the test of the write transfer operation, the sub-pattern generator 22 outputs the sub-pattern signal Pc,
This sub-pattern signal Pc is written into the SAM unit 2. SA
The sub-pattern signal Pc written in the M unit 2 is transferred to the RAM unit 1 by a write transfer operation, read from the RAM unit 1 and input to the main logical comparator 13. At this time, the main logical comparator 13 is given a main expected value signal P _B from the main pattern generator 12, and the main expected value signal P _B and the data read out from the RAM unit 1 is logically compared.

[0006]

As described above, conventionally, in order to test the read transfer operation, the sub-pattern based on the main pattern signal written from the main pattern generator 12 to the RAM unit 1 of the memory under test MUT. It must generate a sub expected value signal P _D from the generator 22. To test the write transfer operation, the sub-pattern generator 2
It must generate a main expected value signal P _B from the main pattern generator 12 on the basis of 2 to the sub-pattern signal written in the SAM unit 2 of the memory under test MUT. This is different timing (asynchronous) between RAM and SAM
However, this is to enable testing.

Since there is no means for transmitting and receiving signals between the main pattern generator 12 and the sub-pattern generator 22, the sub-pattern generator 22 independently outputs the main pattern signal output from the main pattern generator 12. _A sub-expected value signal P _D that matches P _A must be generated.
That must generate a sub expected value signal P _D by considering whether what the output as the main pattern signal P _A. Thus creating a program for generating the sub expected value signal P _D from the sub-pattern generator 22 has become cumbersome to.

On the other hand, when testing the write transfer operation, the sub-pattern signal Pc from the sub-pattern
At the same time as writing to the AM section 2, the sub-pattern signal Pc is transferred from the SAM section 2 to the RAM section 1, and an arbitrary address of the RAM section 1 (this write address is
), The sub-pattern signal Pc is read out, input to the main logic comparator 13, and the main logic comparator 13 outputs the main expected value signal output from the main pattern generator 12. compared with the P _B.

Therefore, also in this case, the main pattern generator 1
Since 2 must generate main expected value signal P _B in consideration of the contents of the sub-pattern signal Pc which sub pattern generator 22 is output, even the creation of a program for generating the main expected value signal P _B It is troublesome. As described above, conventionally, it is troublesome to create a program for generating an expected value signal used for a read transfer test and a write transfer test, and the time and labor required for creating the program are large.

[0010]

According to the present invention, there is provided a RAM buffer memory in which a plurality of memories have the same capacity as the RAM section of the memory under test, and a SAM having a capacity which is a fraction of the integer of the SAM section of the memory under test. An emulator that operates in the same manner as the memory under test is constituted by the buffer memory, and the RAM buffer memory is accessed a plurality of times during the read transfer operation or the write transfer operation of the memory under test, and
In the transfer cycle, the amount of data to be sent to the SAM unit by the memory under test or the amount of data to be sent from the SAM unit to the RAM unit is transmitted by multiple data transfers, so that the state always equals the state of the memory under test. , And the main expected value signal is generated from the RAM buffer memory and the sub expected value signal is generated from the SAM buffer memory asynchronously like the memory under test.

According to the structure of the present invention, since the expected value signal is generated by the emulator, the main pattern generator and the sub pattern generator need only generate the test pattern. Therefore, the program relating to the expected value signal in the pattern generator is simplified, and the advantage that the creation thereof can be easily performed is obtained.

[0012]

FIG. 1 shows an embodiment of the present invention. In the present invention, an emulator EML that operates equivalently to the memory under test MUT is provided. The emulator EML is the memory under test M
Pseudo R having the same memory capacity as the RAM unit 1 of the UT
It comprises an AM unit 31 and a pseudo SAM unit 32 having a capacity that is 1 / integer of the capacity of the SAM unit 2 of the memory under test MUT. The read transfer operation and the write transfer operation are enabled between the pseudo RAM unit 31 and the pseudo SAM unit 32 in the same manner as the memory under test MUT.

That is, in the RAM unit 1 of the memory MUT under test,
The main pattern signal P from the main pattern generator 12_A
When writing the data, the main pattern signal is also stored in the pseudo RAM unit 31.
No.P _AWrite. In the memory under test MUT,
If there is a transfer operation, the
On the EML side, the pseudo SAM is also sent from the pseudo RAM unit 31.
The data transfer to the unit 32 is performed.

[0014] Data transferred to the pseudo SAM unit 32 provided as a sub expected value signal P _D in the sub-logic comparator 23 is read out serially, SAM unit 2 of the memory under test MUT
Is compared with the serial signal read from The quality of the read transfer operation is tested by this comparison operation. On the other hand, the sub-pattern generator 2 is connected to the SAM unit 2 of the memory under test.
When the sub-pattern signal Pc is written from No. 2, the sub-pattern signal Pc is also written into the pseudo SAM unit 32. When a write transfer operation is performed in the memory under test MUT, data transfer from the pseudo SAM unit 32 to the pseudo RAM unit 31 is also performed on the emulator EML side in conjunction with the write transfer operation. Data is transferred to the pseudo RAM unit 31 is read out from the pseudo RAM unit 31, is fed to a main logical comparator 13 as the main expected value signal P _B.

Thus, according to the present invention, the expected value signal
Since P _B and P _D are generated from the emulator EML, there is no need to generate the expected value signal in the main pattern generator 12 and the sub pattern generator 22. Therefore, according to the present invention, since the main pattern generator 12 and the sub-pattern generator 22 do not need to generate an expected value signal, the creation of the program is facilitated, and there is an advantage that the creation of the program can be simplified. Can be

The amount of data to be transferred at one time during a read transfer operation or a write transfer operation in the memory under test MUT is, for example, 9 bits for a row address and 9 bits for a column address in the case of a memory of 256 K words × 4 bits. Since the data to be transferred corresponds to one row address, data of 512 words × 4 bits = 2048 bits can be transferred at a time. (Hereafter, this will be described using an example of the memory under test MUT). This means that the memory under test M
This means that a multi-bit (2048) data bus exists inside the UT.

In order to realize such multi-bit batch transfer in the emulator EML, it is necessary to increase the circuit scale, and it is difficult to realize the transfer, and even if it is realized, it becomes very expensive. In the invention for this purpose, the emulator EML divides the multi-bit data into a bit capacity of an integral number, transfers the divided data in a time-division manner, and reduces the circuit scale.

The configuration for this will be described with reference to FIGS. As shown in FIG. 2, the pseudo RAM unit 31 includes an address selector 31A, an address controller 31B,
It comprises an AM buffer memory 31C, a read data formatter 31D, a write data formatter 31F, a multiplexer 31G, and a RAM controller 31H.

In this embodiment, 2048 (512 words ×
4 bits) are divided into eight, and 256 (64 words × 4)
A description will be given of a case in which bit data is transferred eight times and a transfer operation equivalent to that of the memory under test MUT is performed. For this purpose, the RAM buffer memory 31C is composed of a plurality of memories that can access 256 bits at a time. That is, the column address area is set to 8
The data is equally divided, and data for one row address is divided into eight times to perform reading and writing. For this purpose, an address controller 31B is provided, and the address controller 31B executes address control during the division transfer operation. The RAM controller 31H controls the entire emulator EML, and divides the operation cycle of the emulator EML into eight every time a transfer command is issued from the main pattern generator 12, as shown in FIG.

The address selector 31A rearranges the address signals supplied from the main pattern generator 12 into a format as shown in FIG.
The address 1C is sent to the address controller 31B as an access address, and the column address is sent to the SAM controller 32E. The SAM controller 32E has S
An AM address pointer SAP is provided, and is loaded when a transfer instruction comes to this SAM address pointer SAP.

The SAM buffer memory 32C has 512 (64 × 8) words × 4 bits = 2048 as shown in FIG.
The memory A is composed of a memory A of 512 bits and a memory B of 512 (64 × 8) words × 1 bit = 512 bits.
The memory A stores data to be transferred or transferred data, and the memory B stores a flag for determining whether to write data to the RAM buffer memory 31C at the time of write transfer. I do.

The read transfer operation is performed as follows. When a read transfer instruction is issued from the main pattern generator 12, the RAM controller 31H divides the cycle of the emulator EML into eight by the instruction cycle, and in each cycle, from all the memories accessed by the row address and the eight divided column addresses. The 256-bit data is read, and the 256-bit data is
Transfer to the unit 32. A 3-bit counter is provided in the RAM controller 31H.
To # 7, and the column address is divided into eight parts by substituting the transfer block address shown in FIG. The data for one row address is divided into eight times according to the progress of the column address, and the pseudo S
It is sent to the AM unit 32.

The 3 provided in the RAM controller 31H
The output of the bit counter is sent to the SAM controller 32E and applied as an address of the SAM buffer memory 32C. The start address of the SAM buffer memory 32C at the time of the read transfer is such that the column address of the RAM buffer memory 31C is loaded into the SAM address pointer SAP provided in the SAM controller 32E, and the SAM is incremented every time the sub-pattern generator 22 issues an increment instruction. The address pointer SAP performs an increment operation of +1 and data is read from the SAM buffer memory 32C. The data read from the SAM buffer memory 32C is formatted by the read data formatter 32D in the form of data on the memory under test MUT side, input to the sub logical comparator 23 as a sub expected value signal, and is output to the SAM section 2 of the memory under test MUT. And a test of the read transfer operation is performed.

The write transfer operation is performed as follows. At the time of write transfer, one row address (all data in the SAM buffer memory 32) is divided into 256 bits and transferred to the RAM buffer memory 31C. Here, when writing the sub-pattern signal from the sub-pattern generator 22 to the SAM buffer memory 32C, the SAM buffer memory 3
Flag memory B only at the address where 2C data was rewritten
Is set to the flag "1". RAM buffer memory 3
When data is transferred to the RAM buffer memory 31C in units of 256 bits at a time and data is written to the RAM buffer memory 31C, only the data of the address where the flag "1" is set is written to the RAM buffer memory 31C, thereby starting from an arbitrary address. correctly even data transfer to start the data transfer is executed, it is possible to output the main expected value signal P _B by reading the data from the RAM buffer memory 31C.

When the data transfer is completed, the pseudo RAM 3
1 and the pseudo SAM unit 32 are independently controlled by both the main pattern generator 12 and the sub-pattern generator 22, so that the expected value signal can be generated asynchronously.

[0026]

As described above, according to the present invention, the test of the read transfer operation and the test of the write transfer operation can all generate the expected value signal from the emulator EML. Therefore, the main pattern generator 12 and the sub pattern generator 22 do not need to generate the expected value signal. Therefore, since there is no need for a program for generating the expected value signal, the creation of the program can be simplified, and the benefit of making the program inexpensive is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;

FIG. 2 is a block diagram for explaining in detail a structure of a main part of the present invention.

FIG. 3 is a timing chart for explaining the operation of the present invention.

FIG. 4 is a diagram for explaining the operation of the present invention.

FIG. 5 is a diagram illustrating a configuration of a SAM buffer memory used in the embodiment of the present invention.

FIG. 6 is a block diagram for explaining a configuration of a memory under test.

FIG. 7 is a diagram for explaining a read transfer operation of a memory under test.

FIG. 8 is a diagram for explaining a write transfer operation of a memory under test.

FIG. 9 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

 MUT Memory under test 11 Main timing generator 12 Main pattern generator 13 Main logic comparator 22 Sub pattern generator 23 Sub logic comparator 31 Pseudo RAM unit 32 Pseudo SAM unit EML emulator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/16 G01R 31/28 G06F 11/22 G11C 29/00

Claims (1)

(57) [Claims] 1. A RAM unit capable of random access,
Part of the data written in the RAM portion is transferred, the transferred data can be sequentially read as high speed serial data, and high speed serial data can be fetched from outside. the taken-serial data transferred to the RAM unit at a time, the memory comprising a capable SAM unit be stored in the RAM unit, the memory pattern signal generated from the pattern generator
And the data read from the memory and the expected value
A memory test apparatus for comparing and testing a RAM with a logical comparator, a RAM buffer memory having a plurality of memories having a capacity equivalent to the RAM section of the memory under test, and a capacity of an integral number of the SAM section of the memory under test An emulator that operates in the same manner as the memory under test is constituted by the SAM buffer memory having the SAM buffer memory or the RAM buffer memory described above during the read transfer operation or the write transfer operation of the memory under test. A plurality of times, and the amount of data transmitted from the RAM unit to the SAM unit by the memory under test or the same amount of data transmitted from the SAM unit to the RAM unit in one transfer cycle is determined by the SAM buffer memory and the RAM.
The data is transferred between buffer memories , and always keeps the same state as the memory under test.
The main expected value signal from the M buffer memory and the SAM
A memory test device configured to generate a sub-expected value signal from a buffer memory.