JPH0477825A - Controller - Google Patents

Abstract

PURPOSE:To increase the operating speed of an APG by giving the instructions to all control means at one time and controlling all control subjects at one time. CONSTITUTION:A control means controls a control subject (register) in a single control unit, and plural pieces of such control unit are prepared. Then the instructions are given to all control means 45, 55 and 65 at one time, and these control means are controlled at one time. For instance, an X address generating part 22 includes three registers, i.e., an A register 46, a C register 56, and a program counter 66. The prescribed control operations such as the loading, increasing and shifting operations of data, etc., are applied to those three registers. Thus the desired data is obtained at the register 46. As a result, the control means are not required to selects the control subjects and the operating speed of an APG is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device for controlling multiple control objects such as registers simultaneously and at high speed, and in particular to a control device for controlling a plurality of control objects such as registers, etc.
The present invention relates to a control device suitable for an algorithmic pattern generator, etc. of a test device.

[Prior Art] FIG. 5 is a block diagram showing an example of a memory LSI testing device. Memory LSI test equipment is a memory LSI test equipment.
A test is performed by applying a predetermined test pattern, that is, an address pattern and a data pattern to the DUT 20, performing writing and reading, and comparing and verifying the written data and read data. A test program for generating test patterns is stored in the RAM 14 from the storage means 10 via the host computer 12. By applying a test program to an algorithmic pattern generator (hereinafter referred to as APG) 16 from the RA and M14, a test pattern is applied from the APG 16 to the DUT 20 via the I10 device 18. These controls are performed by the host computer 12.

[Problems to be Solved by the Invention] In recent years, as the write and read operation speeds of memory LSIs have improved, there has been a demand for faster test speeds, that is, faster test pattern generation speeds. For this purpose, it is necessary to increase the operating speed of the control device that controls the operations of A and PG. Also, in general, APG
Since control is performed in synchronization with a clock, it is required to simultaneously control a plurality of output signals (addresses and data) and to make the time required for each control the same. Therefore, among multiple controls that should be performed simultaneously, increasing the speed of only some controls or shortening only the time required for control at a certain point is an effective way to increase the operating speed of A, PG, and G. Does not contribute. In other words, it is necessary to simultaneously control each individual control and to shorten the time required for all the controls.

Therefore, an object of the present invention is to provide a control device that satisfies the above conditions and increases the operating speed of an APG.

[Means for Solving the Problem] The control device of the present invention includes a plurality of control units each including one controlled object and a control means that controls only the one controlled object in response to a command. There is. Further, the command includes a condition part indicating a condition related to the state of the controlled object, and a control part indicating details of control to be performed in response to whether the judgment result of the condition is true or false.

[Operation] According to the control device of the present invention, the above-mentioned command is given to all of the control means at the same time, and all of the objects to be controlled are controlled at the same time. Further, the control means determines whether the condition in the condition determination part is true or false, and, depending on the determination result, executes control corresponding to either the truth or falsehood indicated in the control part.

[Example] Fig. 2 shows a memory L S to which the control device of the present invention is applied.
It is a block diagram of I test equipment. Parts corresponding to those in FIG. 5 are designated by the same reference numerals. RA that stores the test program
A command is given to APG16A from M1.4A. A,
PG16A includes the following parts. That is, D.U.
an X address generation section 22 that generates X, Y, and Z addresses of the T (memory LSI) 20; Y address generation section 24. and a Z address generation section 26, a data generation section 28 that generates data to be written to the DUT 20, and the DUT 20.
This is a control signal generating section 30 that generates control signals (write signals and read signals) to be applied to. Address, data, and control signals generated by APG 16 are provided to DUT 20 by I10 device 18. The I10 device 18 also has functions such as comparing read data from the DUT 20 and write data. host computer 12
provides control signals to RA, M], 4A, APG 16A, and I10 device 18 so that the test on DUT 20 is properly executed. RAM1.4A to A
Instructions corresponding to each of the generation units 22 to 3o are independently and simultaneously given to the PGI 6A.

FIG. 1 is a block diagram showing the detailed configuration of the X address generating section 22. As shown in FIG. Note that the Y and Z address generation section 24
．． 26 and the data generating section 28 also have the same configuration as the X address generating section 22. First, the configuration will be explained according to FIG. The X address generating section 22 includes three registers, namely, an A register 46, a C register 56 . and a program counter (hereinafter referred to as PC) 66. By performing predetermined control 2 on these registers, for example, loading, incrementing, shifting data, etc., the A register 4
6. Obtain the desired data. In this way, X.

A test pattern is generated by combining the address data obtained by the Y and Z address generators 22-26. In FIG. 1, A register 46. C register 56. and instructions 32.34. to control the PC 66. and 36 are respectively given to the X address generation section 22 at the same time. These instructions include three elements described below. The first element is a condition part indicating a condition related to the state of the controlled object, ie, the register state. This condition is a preset condition such as, for example, "Is the value held in a register equal to a predetermined constant?" or "Is the value held in two predetermined registers equal to each other?" The second element is the control part.

In other words, there is a control part that indicates the control (operation a) to be performed on the register when the condition shown in the first element holds true (true), and a control part that shows the control (operation a) to be performed on the register when the above condition does not hold (false). It is composed of two parts: a control part that shows the control (operation b); The third element is a data portion indicating data to be given to the register. A comparator 68 having an output signal line corresponding to the type of register state condition receives the values held in each register 46, 56, 66 and a predetermined constant from a constant supply means (not shown),
If a certain register state is true, set it to "1"; if it is false, set it to "1".
"O" is output to the output signal line corresponding to the above condition. Therefore, by detecting the output of the output signal line corresponding to the condition, it is possible to determine whether the condition is true or false. As shown in Figure 2,
By connecting the necessary number of output signal lines between the Y and Z address generators 22, 24, 26 and the data generator 28, each of the two generators can tell each other whether the necessary conditions are true or false. It is possible to judge. Therefore, in the selection means 40, 50, 60, X, Y, Z7F
The necessary conditions can be selected from among the conditions in the I/S I generation section and the data generation section. The decoder 38 decodes the first element (condition part) of the instruction and selects the output signal line corresponding to the condition indicated by the first element using the selection means 40 to obtain a signal. Then, it is given to the selection means 42. The selection means 42 selects operation a if the applied signal is "1", selects operation a if it is "0", and supplies it to the decoder 44.

The decoder 44 performs a control operation on the A register 46 according to the given operation a or b. At this time, command 3
The data portion of 2 is given to the A register 46. As a result of the above control operation, the value held in the A register 46 is provided to the comparator 68. According to this value, the comparator 68 sets the output of the signal line according to the register state to "0".
Or set it to "1". Although only the A register 46 and the portion that controls it have been described, the same operation is performed for the C register 56 and PO66. Since the registers 46, 56, and 66 are controlled, they are called controlled objects. Also, what controls this controlled object is called a control means.

For example, the control means 45 for the A register 46 consists of decoders 38, 44 and selection means 4.0.42. Similarly, control means 55 and 65 are provided for the C register 56 and PO 26, respectively, which are to be controlled.

The first important thing about the control device of the present invention is that the control means controls only one controlled object (register), and there are a plurality of control units including such controlled objects and control means. Give commands to all control means at the same time,
This means controlling each of the controlled objects at the same time.

In contrast, in conventional control devices, one operating means is
The operation target specified by the operand part of the instruction given to it is selected, and the operation specified by the opcode part of the instruction is performed on the operation target.

For this reason, in the past, a selection means for selecting the operation target was required, and the selection required 8-times of composing. Therefore, unlike the conventional art, the present invention has the advantage of speeding up the control operation by eliminating the need for selection means for selecting a controlled object and operation time.

The second important point in the present invention is that the command given to the control means includes a condition part indicating a condition related to the state of the controlled object, and a control to be performed in response to the truth or falseness of the result of this condition judgment. It also includes a control part that indicates the content. Therefore, since the control means can fetch the condition part and the control part at the same time, it can judge the condition and immediately execute control according to the result of the judgment. On the other hand, conventionally,
A conditional branch instruction given to the control means requires a jump and a new instruction to be fetched depending on the result of the conditional judgment. Therefore, there is a drawback that fetch operation time is required. Further, as a result of a conditional branch instruction, if one branch requires the execution of an unconditional branch instruction while the other branch does not require it, a difference will occur in the number of instruction steps executed after the branch. In other words, there is a drawback that the control operation time varies depending on the result of the conditional branch. In the conventional control device, even if an instruction pre-fetch is performed, the fetch itself is necessary, and unlike the present invention, the fetch operation accompanying a conditional branch instruction cannot be removed. Another disadvantage is that complex hardware is required for instruction prefetching.

In contrast, as described above, the present invention, unlike the conventional art, eliminates the need for fetch operations associated with conditional branch instructions, thereby making it possible to shorten operating time.

FIG. 3 is an explanatory diagram showing an example of a program given to the X address generation section 22. As shown in the figure, the command includes a condition part, a control part (operation a.

b), and a data part. Note that in the same step, control is executed for all registers simultaneously.

Note that the commands in the columns of operations a and b will be explained in advance.

TNC: Increment (increase register contents by 1) LOAD+ Load (store data in register) DEC: Decrement (decrease register contents by 1) NOP: No operation (do nothing) Program shown in Figure 3 does the following:

That is, for the X address, the write address is O,
I, 2. After outputting 3 in sequence, 3. 2. 1. Output O sequentially. Each step will be explained in detail below.

(Step 1) Since the condition of the command in step 1 is "always", operation a is performed unconditionally. Increment PO26. Load A register 46 with 0. C register 56
Load 3 into.

(Step 2) The condition for PO 66 is "The contents of A register 46 are equal to the contents of C register 56."

If this condition is true, increment PO26 and =1
1 If it is false, do nothing. Step 2 will be repeated unless PO66 is incremented. The condition for the A register 46 is also "are the contents of the A register 46 equal to the C register 56?" If this condition is true, nothing is done, and if it is false, the A register 46 is incremented. Since the condition for the C register 56 is "always", operation a is performed and no processing is performed. As a result, in step 2, the contents of the A register are incremented by 1 from 0 to 3. At the next point in time when the contents of the A register become 3, PO66 is incremented and the process moves to step 3.

(Step 3) The condition for PO 66 is "Is the content of A register 46 O?" If this condition is true, PO66 is incremented, and if it is false, nothing is done. The condition for the A register 46 is also: [Is the content of the A register 46 O?].

If this condition is true, no processing is performed, and if it is false, the A register 46 is decremented. Since the condition for the C register 56 is "always", operation a is performed and no processing is performed. As a result, in step 3, the contents of the A register are decreased by 1 from 3 to O. At the next point in time when the contents of the A register become 0, PO26 is incremented, thereby completing the process of step 3 and proceeding to the next step (not shown).

FIG. 4 is a flowchart corresponding to the program of FIG. 3. This flowchart shows the processing in each step as being performed in sequence, so it cannot be said to accurately represent the processing in FIG. 3, but it is shown for reference in order to understand the processing contents. It should be noted that in reality, as explained in FIG. 3, the processes in each step are executed simultaneously.

In the above embodiment, only the X address was described, but the Y
, Z address operates in exactly the same way. For example, if the Z address is fixed and the process shown in FIG. 3 is performed for both the X and Y addresses, the X and Y addresses are incremented by 1 from 0 to 3 as write addresses, and then,
As read addresses, the X and Y addresses can be decreased by 1 from 3 to 0. To simplify the explanation,
Although the above embodiment shows a very simple program, in reality a program that generates a more complex pattern will be executed.

In the description of the embodiment shown in FIG. 1, the configuration is such that each of the address generation section and the data generation section is provided with a PC. Therefore, in order to control all address generation sections and data generation sections at the same time, it is necessary to give the same command to all PCs. However, in reality, 1
It is sufficient to use one PC in common for all address generation sections and data generation sections, and in this case, it is sufficient to provide one PC on one side. Therefore, the configurations of the address generation section and the data generation section can be made simpler, and the instructions given to the control means can be made shorter.

Although preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments described herein.
It will be apparent to those skilled in the art that various modifications and changes can be made as necessary without departing from the spirit of the invention.

[Effects of the Invention] As explained above, according to the control device of the present invention, the control means controls only one controlled object, and the above-mentioned command is given to all of the control means at the same time, thereby controlling the controlled object. Control everything at the same time. Therefore, unlike the conventional method, there is no need for the control means to select an object to be controlled, so that the operation can be made faster. Further, the command given to the control means includes a condition part indicating a condition related to the state of the controlled object, and a control part performed in response to the truth or falsity of the result of determining the condition. Therefore, the control means can immediately execute condition judgment and control corresponding to the condition judgment. Therefore, unlike in the past, the control means does not need to fetch a new instruction in response to condition judgment, which has the advantage of shortening the operating time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing details of the X address generation section in an embodiment of the control device according to the present invention, and FIG.
Memo 1.5 to which the control device of the present invention is applied; a block diagram showing an embodiment of the LSI test device; FIG. 3 is an explanatory diagram of an example program given to the X address generation section;
FIG. 4 is a flowchart corresponding to the program example shown in FIG. 3, and FIG. 5 is a block diagram showing the configuration of a portable memory LSI test device. 32.34, 36: Instruction 46.56, 66: Controlled object (register) 45.55
, 65: Control means

Claims (2)

[Claims] (1) A control device comprising a plurality of control units each including one controlled object and control means for controlling only the one controlled object in response to a command, wherein all of the above control means are simultaneously controlled. A control device characterized in that it gives the above command and simultaneously controls all of the control targets. (2) The command includes a condition part indicating a condition related to the state of the controlled object, and a control part indicating the content of the control to be performed in response to the true or false determination result of the condition, and the control means The control according to claim 1, wherein the control unit determines whether the condition in the condition part is true or false, and, depending on the determination result, executes control corresponding to either the truth or falsehood indicated in the control part. Device.