JPH0290078A - Ic testing apparatus - Google Patents

Abstract

PURPOSE:To operate a plurality of algorithm pattern generators (ALPG) in parallel and to make it possible to generate a high speed pattern by providing operating means, and changing the repeating number of loops flexibly. CONSTITUTION:A timing generator 27 outputs operating clocks 28-1 and 28-2 for an ALPG (a) and an ALPG (b), selecting signals 29-1 and 29-2, a waveform forming clock 30 and a comparison timing signal 31. In synchronization with the clocks 28-1 and 28-2, the results of microprograms are outputted from operating parts (c) and (d) as 15-1 and 15-2. The selecting signals 29-1 and 29-2 are inputted into output switching gates 24 and 25 from the generator 27, and ALPG high speed pattern data 32 are obtained. The data 32 are converted into application waveforms in a waveform forming device 33 and applied to a memory under test 34. The data read out of the memory 34 are sent into a comparator 37 together with expected value data 36 through a delay device 35. Pass or fail is judged in the comparator 37.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC testing device, and particularly to an IC testing device suitable for testing high-speed memories.

[Conventional technology]

A conventional IC testing device is provided with a plurality (N) of microprogram type algorithmic pattern generators (ALPG) as pattern generators, as described in Japanese Patent Laid-Open No. 62-85678.

The configuration is such that the output can be extracted sequentially.

As a whole, it becomes an IC test device that generates patterns at a speed N times faster than the operating speed of each individual pattern generator.

FIG. 2 shows a schematic internal configuration of one conventional pattern generator, which is mainly composed of a sequence control section 1 and an arithmetic processing section 2. As shown in the figure, the sequence control unit is of a microprogram type, and includes an instruction memory 5 for storing microprograms and a program counter 5 for determining the read address 4. It consists of a counting section 6 that counts the number of loop repetitions, a loop control section 7 that counts the number of loop repetitions, and an address selection section 10 that selects the next address 9 based on the output signal 8 from the counting section.

The instruction data 12 read out from the instruction memory in synchronization with the operation clock 11 is composed of an operation instruction 13 and a sequence instruction 14.
It becomes more. Among these, the arithmetic commands are sent to the arithmetic processing section, and after arithmetic operations and logical operations are performed, they are output as an algorithmic pattern 15. The sequence instruction consists of a loop control signal 16 such as the number of loop repetitions and a count instruction that is supplied to the loop control section, a branch address 17 that is supplied to the address selection section, and the like.

In this way, ALPG has a feedback loop like the following address 9 in hardware in order to realize movements including branch operations such as nine loops and repeats according to the program, making it difficult to increase the speed. There is. Therefore, a method has been proposed in which a plurality of nine ALPGs shown in FIG. 2 are executed in parallel, as described in the known example.

[Problem to be solved by the invention]

However, in the above-mentioned conventional technology, no consideration has been given to efficiently generate a test pattern having a loop (variable loop) structure in which the number of repetitions decreases by one each time it is executed by the parallel operation of a plurality of ALPGs.

An object of the present invention is to provide an rCC test tube that can generate a high-speed pattern by operating a plurality of 0ALPGs in parallel even if the test pattern is written using a variable loop.

[Means to solve the problem]

The above purpose is to set the loose repetition number to an arbitrary value according to a program in the loop control section of each of a plurality of ALPGs.
This is achieved by providing a ninth arithmetic means for changing the number of repetitions of the loop so that the number of repetitions of the loop can be changed flexibly.

[Effect]

FIG. 1 shows the internal configuration of one ALPG which has a calculation section and a nine-loop control section. To execute the variable loop, f′i,
First, the arithmetic unit 18 executes the sequence instruction 14 to store the initial value 19 of the repetition number of the variable loose.Finally, the instruction to transfer the repetition number 161r to the counting unit 6 is executed and the value is stored in the counting unit.

Thereafter, all instructions included in the variable loop are executed one step at a time, and the number of loop executions is counted each time the branch instruction at the end of the loop is reached. When the branch instruction is executed, the loop count value 8 is input to the address selection unit 10, and it is determined whether the loop should be continued or exited. This is how the variable loop finishes its first execution nine days later.

Furthermore, by executing an outer loop or an unconditional branch instruction, execution moves to the address before the variable loop, resulting in a second variable loop execution, but at this time, the number of iterations of that loop is 1. It's different from the last time. Therefore, the instruction to add the difference M2O to the first repetition number stored in the arithmetic unit is executed before entering the second variable loose. After that, the second repetition number is 1
By executing the instruction to transfer to the 6ft counter 6,
This variable loop will be executed with a different number of iterations than the first time. The same operation as the second time is repeated from the third time onwards.

In this way, before executing a variable loop, by adding or subtracting 'X by the ratio value specified by the sequence command to the number of @ repetitions, it is possible to execute a variable loop in which the number of loop repetitions is reduced to an arbitrary number. can. As a result, ALPG f:i
With a configuration in which several tests are executed in parallel, even test patterns written in a 1' loop structure can be generated without problems.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 3 to 7.
jl[Explain further.

FIG. 5 is an overall diagram of an example of an IC test device constructed from two ALPGs. This figure shows the pattern generator in Figure 1 as AI, P
This is a high-speed IC testing device having a high-speed pattern generation section based on a parallel existential method, which uses two G (a) 21 and ALPG (b) 22, a signal selection section 23, all AND gates 24 and 25, and an OR gate 26.

The timing generator 27 has ALPG (a) and AL
PG (b) operation clock 28-1-28-2, ALPG
Selection signal 29-1 for (a) and ALPG (b)
・29-2, waveform generation clock 30 and comparison timing M
No. 31 is output. ALPO operation clock 28-1/2
The speed 8-2 is 1/2 of the speed required for the high-speed pattern output 52.

As shown in FIG. 7, the operating clocks 28-1 and 28
The results of each microprogram processing executed in parallel by ALPG (a) and (b) in synchronization with -2 are output from the arithmetic processing units (a) and (b) as shown in 15-1 and 15-2. Ru.

Selection signals 29-1 and 2 from the previous timing generator 27 are sent to gates 24 and 25 for sequential selection switching of these outputs.
9-2 is input, and ALPG & speed pattern data 52 as shown in FIG. 7 is obtained.

High-speed Bakun data 32 is printed by a waveform generator 35. The data read from the memory under test is sent to the comparator 37 together with the next expected value data 56 through the delay device 35t, and a pass/fail determination is made.Afterwards, the result of the determination is stored in the fail memory 381C.

The computer 39 executes a test pattern program for a pattern generator created for one IC test device in ALPG.
Before executing the test, analyze the program structure in advance, convert and create a test program for ALPG (a) and ALPO (b), and connect each ALPG to data bus 4.
Transfer using 0t. The computer also sends various data to other parts of Figure 5, and performs the sesotoag work necessary for test execution, test execution control, and analysis of data in the 7ail memory.

Next, as a test program to be executed, a program that generates a test pattern called a fast walking pattern written in a variable loop structure will be described as an example.

FIG. 5 shows, along with a flowchart, the contents of a microprogram for 32 bits of memory under test (n+1).

■: Clear all cells of the memory under test in loop L1 with 32 repetitions.

■: One of the cleared memory cells is set as a test cell, and its memory address (address A-1) K data 16
Write.

■: Perform a nibbling start cell, read and check the data at an address larger than the test cell (address A-1+j), and then check whether the check has been completed to the cell at the final address (address A-51). Then, process step (2) is repeated as loop L2.

■=1) Read the test cell address (address A-1),
After checking the influence of access to the disturb cell, 2) write and clear data O1't- to the test cell address. Then, all cells except the cell with the final address are tested as test cells, and it is determined whether the test cell is finished or not. If it is not finished, the current test cell address (A4 address 1) is checked.
plus 1 (i-1+1') L.

The process returns to processing step (2) as loop L3.

(2)=1) Write data 11' to the test cell with the final address (A=address 31), and then 2) read and inspect the test cell address.

3) After that, write data IQI to the test cell address and clear it.

Note that for the sake of simplicity, the instructions (2) and (3) are described in one step by combining two instructions and three instructions, respectively.

By executing the process (2), the inspection of all test cells is completed, and the program of the 7 earth walking pattern shown in FIG. 3 is completed. However, to be more precise, it is called a back pattern inspection, and the first walking pattern is completed by executing steps ① to ② with the data °0' and °1'' reversed, but this is omitted here.

Here, among the three loops appearing in this pattern, the number of repetitions of loop L2 decreases by one each time the outer loop L3 is executed, indicating that it is a variable loop.

Complete this fast walking program with two A's.
When executing LPGs (a) and (b) in parallel operation, the program cannot be allocated to two ALPGs as is, and it is necessary to convert the program for multiple ALPGs. This conversion is performed on the computer 59 based on a certain algorithm, resulting in the results shown in FIGS. 4(a) and 4(b). This program (a) and (b)'t
The high-speed pattern data 32 becomes the same pattern as shown in FIG. 3 by allocating and operating the instruction memories of the fifth factor ALPGs (a) and (b), respectively.

As a result of the conversion, the variable loop L2 is divided into four variable loops L2' as shown in the figure, but since they are originally the same loop, one loop control unit is shared.

Now, on computer 39, t) ALPG (a) and (
(b) The test program converted for S has a test sequence including a variable loop as shown in Figure 4, and in order to execute it, the A
LPG is required. Figure 6 shows the loop control section 7 in Figure 1.
This is an embodiment of the present invention, and its operation will be described in detail below, taking as an example the case from the loose L2' at the end of the variable loop in FIG.

Before starting execution of loose L2', perform the following initial settings. That is, a second multiplexer 45 controlled by a 5 selection signal 44 is assigned to the loop L2' and is located in the nine loop control unit, and is applied to a holding register 41 that holds the number of loop repetitions and a counting register 42 that counts down as the loop is executed. The loop repetition initial value 43 (14) is taken in in synchronization with the operating clock 28 through the first multiplexers 47 controlled by the selection signal 46, respectively. This initial setting is performed before entering loop L3'. Three L2′ are executed in order from the end,
Execution moves to L2' at the end.

In L2' at the end, when the branch instruction is executed, the remaining number of repetitions, 8, is decremented by 1 by the decrementer 48, and the first multiplex? 47 and stored in the count register 42. In this way, when the output 8 of the counting register is OK,
The address selection section 10 shown in FIG.
'The address of the next step is selected and the entire loop is completed.

Thereafter, the loop L5' moves to the actual child of the first L2', but the number of repetitions of I, 2 / must be the value t, which is the number of repetitions of the last L2' minus 2. Therefore, the previous time (L at the end) stored in the holding register 41
The number of repetitions of 2') is input to the arithmetic unit (adder) 49, and at the same time the increase/decrease value 20(
-2) is input, addition'x is performed, and the result is stored in the counting register 42 and the holding register 41. If the first loose L2' is executed nine times later, it will be repeated two times less than the last loose L2'.

By repeating the same operation thereafter, it is possible to generate a variable loop sequence in which the number of loop repetitions changes at arbitrary intervals.

As mentioned above, in this embodiment, by simply adding a holding register with a loop control unit 1iK, a multiplexer, and an adder, a test pattern written in a test program including a variable loop structure can be generated by parallel operation of two ALPGs. . Note that in this example, a test device with two ALPGs is shown, but of course this number can be any number N greater than or equal to two.
It can be configured by

〔Effect of the invention〕

According to the present invention, the conventional memo with a plurality of ALPG+
7. Each ALPG of the IC test equipment is equipped with an ALP that can execute not only a test program with a loop structure with a constant number of repetitions but also a loop structure with a loop structure where the number of repetitions changes by an arbitrary number.
G'2 is used, and by creating test programs to be executed on each ALPG in advance on a computer and storing them in the instruction memory of each person's LPG, multiple parallel test patterns of all ALPGs with variable loop structures can be created. It is now possible to generate friends in action.

As a result, the present invention has the advantage that by using a pattern generator in which a plurality of 0ALPGs operate in parallel, a memory test can be easily performed using the 7-earth walking pattern, etc., which was difficult to perform in the past.

[Brief explanation of drawings]

Figure 1 is an internal configuration diagram of a pattern generator showing the main points of the present invention, Figure 2 is an internal configuration diagram of a conventional pattern generator, and Figure 3 is an internal configuration diagram of a conventional pattern generator.
The figure is an explanation (8) showing an example of a microprogram for generating a fast walking pattern, which is one of the memory test patterns. Fifth
The figure is an explanatory diagram of one embodiment of the present invention, the fa6 diagram is an internal configuration diagram of the part corresponding to the loop control section of the first cause, and the timing dynamics f'F diagram of the main signals in Figure 7 #i in Figure 5. . 1... Sequence control section, 6... Counting section, 7...
Loose control unit, 14... Kukens instruction, 18...
Arithmetic unit, 20...Repetition number increase/decrease value, 41...Holding register, 49... Arithmetic unit. Fig. 4 Fig. 6 Fig. 6 Flow Noah 2g-2 ALP over) system selection signal 9-I AtP# (a) IIMM i-5 q-2 Pulli

Claims (1)

[Claims] 1. Sequence control means that decodes a test program that describes a test pattern and sends out a command signal in synchronization with an operating clock, and arithmetic processing that generates a test pattern by performing arithmetic processing according to instructions from the sequence control means. a plurality of algorithmic pattern generation means, a selection means for sequentially selecting the outputs of the algorithmic pattern generation means according to a selection signal, and supplying the outputs of the algorithmic pattern generation means to the IC under test based on the outputs of the algorithmic pattern generation means; means for generating a waveform in synchronization with a waveform generation clock; means for comparing the output from the IC under test with an expected value in synchronization with a comparison timing signal; the operation clock, the selection signal, the waveform generation clock; In the IC testing device comprising timing generation means for generating the comparison timing signal, the sequence control means is provided with means for changing the number of loop repetitions to an arbitrary value described in the program during program execution. IC testing equipment.