JPH0943317A - High speed pattern generating method and high speed pattern generator using this method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the generation of a high speed pattern without using an element that can conduct high speed motion, by taking out a main pattern and plural sub patterns by conducting time division multiplexing at a multiplexing circuit. SOLUTION: A main pattern generation command and subtraction numbers P1-P3 for regulating predetermined patterns are generated every one sequence control from a sequence control part 110. The main pattern generation command is inputted into a main pattern generating part 121, and a main pattern is generated. At the same time, subtraction numbers P1-P3 are given to sub pattern generating parts 122-124, and at the generating parts 122-124, main pattern generated at the main pattern generating part 121 in an order succeeding the main pattern is generated using subtraction number P1-P3 and as a pattern to be given to a tested IC from the sub pattern generating part 122-124. The main pattern and plural sub patterns are taken out by being conducted with time division multiplication at a multiplication circuit 500, and a high speed pattern signal that changes according to predetermined pattern generation order is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed pattern generator used for testing pass / fail of an IC such as a memory composed of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 9 shows the configuration of a conventional IC test apparatus. In the figure, 100 is a pattern generator, 200 is a data selector, 300 is an IC under test, and 400 is a logical comparator. The pattern generator 100 includes a sequence controller 110.
And the pattern generator 120.

As shown in FIG. 10, the sequence controller 110 includes a program counter / controller 111, a program counter 112, and an instruction memory 1.
13, loop counter 114, initial value storage register 11
5 etc. Instruction memory 1
Reference numeral 13 includes a sequence control instruction storage area 113A and a pattern generation instruction storage area 113B, which are accessed by an address signal given from the program counter 112, and the sequence control instruction is read from the sequence control instruction storage area 113A. This sequence control instruction is decoded by the program counter controller 111, the address to be accessed next is determined, the address signal is given from the program counter 112 to the instruction memory 113, and the sequence control instruction is read from the instruction memory 113.
In this way, every time the sequence control instruction is read, the instruction memory 113 determines the address to be accessed next according to the control instruction written in the sequence control instruction, and this is repeated to repeat the pattern from the pattern generation instruction storage area 113B. The generated instruction is read.

One of the reasons for adopting the method of reading the pattern generating instruction while determining the address to be accessed next according to the sequence control instruction is to temporarily write the pattern generating instruction into the program step by step to generate the pattern generating instruction. When the method is adopted, the program becomes large in size, and there is a problem that it takes a lot of time and labor to manufacture the program. Therefore, generally, a programming method is adopted in which a predetermined test pattern is generated a predetermined number of times using a loop instruction. Therefore, the number of times of each loop is stored in the initial value storage register 115 at the start of execution of pattern generation, the number of loops of the loop is counted by the loop counter 114, and when the loop is rotated a predetermined number of times, the next loop instruction is executed. To work.

The pattern generation command read from the pattern generation command storage area 113B is stored in the pattern generation unit 120.
And the pattern generation unit 120 generates a test pattern signal and an address signal according to the pattern generation command.
The data selector 200 selects an address signal, a data signal, or the like to be applied to the IC under test 300 from the signals generated by the pattern generating section 120, and after shaping the waveform of these signals,
It is given to the IC 300 under test. In addition, the data selector 20
0 selects expected value data from the test pattern signal and supplies it to the logical comparator 400.

In the logical comparator 400, the IC under test 300 is tested.
The IC under test 300 is tested by logically comparing the data read from the data with the expected value data from the data selector 200 and detecting the occurrence of a mismatch.

[0007]

In the conventional pattern generator 100, since the instruction memory 113 needs to operate at a speed higher than the pattern generation frequency, it is difficult to speed up the sequence controller 110. . In particular, in order to increase the pattern generation speed, the instruction memory 113, the program counter,
The controller 111, the program counter 112, the loop counter 114, and the like must all be replaced with elements that can operate at high speed. In addition, the pattern generator 12
Since 0 has to be replaced with an element capable of high-speed operation and a pipeline structure of an ultra-multistage has to be adopted, much cost is required, and even if it is realized, it is expensive and large in size.

Further, even if the cost is increased, there is a limit to the operating speed of the element capable of operating at high speed. Therefore, it is difficult to increase the pattern generation rate from 100 MHz in the prior art to several 100 MHz. A first object of the present invention is to provide a high speed pattern generator capable of generating a high speed pattern several times faster than before without using an element capable of high speed operation.

A second object of the present invention is to provide a high speed pattern generator capable of easily creating a program for generating a high speed pattern.

[0010]

A high-speed pattern generation method according to the present invention causes an instruction memory to output a pattern generation command with arguments for defining a plurality of patterns following a main pattern, and the main pattern generation unit executes a main pattern generation unit in accordance with the pattern generation command. A pattern is generated, the main pattern generated in the main pattern generation unit is given to a plurality of sub pattern generation units, the main pattern is changed according to the above argument in the plurality of sub pattern generation units, and the main pattern is delayed to follow the main pattern. We propose a high-speed pattern generation method in which multiple sub-patterns to be generated are generated in the same phase as the main pattern, and the main pattern and multiple sub-patterns are time-division-multiplexed by a multiplexing circuit and extracted to change according to a predetermined pattern generation order. It is a thing.

Further, according to the present invention, in a pattern generator having a sequence control instruction and an instruction memory for storing a pattern generation instruction, and generating a test pattern signal to be given to an IC under test according to a pattern generation instruction read from the instruction memory, The main pattern generation instruction and the main pattern generation instruction are changed from the pattern generation instruction storage area of the instruction memory to generate an argument (parameter) for defining a sub pattern to be generated in a predetermined order following the main pattern. Then, the main pattern generation command is given to the main pattern generation unit, and the main pattern generated in the main pattern generation unit is
A high-speed pattern generator characterized in that a high-speed pattern signal is obtained by generating a plurality of sub-patterns having an order that should follow the main pattern and time-division multiplexing the main pattern signal and the sub-pattern signal. It is a proposal.

According to the structure of the present invention, the circuit from the sequence controller to the input of the main pattern signal and the sub pattern signal to the multiplexing circuit can be composed of a circuit which operates at the same speed as the conventional one. . Moreover, even if these circuits are operated at the same speed as in the conventional case, the pattern generation speed can be increased to several times the speed of multiplexing by performing time division multiplexing by the multiplexing circuit. Therefore, according to the present invention, it is possible to obtain the practical benefit of being able to provide the high-speed pattern generator at a low cost.

Further, according to the configuration of the present invention, since the main pattern generating instruction is added with the argument to generate the sub-pattern, the program creator only needs to define the main pattern to create the program. A program for pattern generation can be easily created.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a high speed pattern generating method and a high speed pattern generator according to the present invention will be described with reference to FIG. In FIG. 1, reference numeral 130 indicates a high speed pattern generator according to the present invention. A high speed pattern generator 130 according to the present invention includes a sequence controller 110 and a pattern generator 1.
20 and a multiplexing circuit 500 that time-division-multiplexes the test pattern generated by the pattern generator 120.

That is, since the present invention employs a configuration in which a high-speed pattern signal is obtained by multiplexing, it is necessary to generate pattern signals by dispersing them in a number corresponding to the number of multiplexing. Therefore, in the present invention, the sequence control unit 110 causes the main pattern generation instruction MAIN for each sequence control and arguments (parameters) P1, P2, P3 for defining a predetermined pattern following the main pattern.
Generate.

The main pattern generation command MAIN is input to the main pattern generation unit 121 to generate a main pattern. Along with this, the arguments P1, P2, P3 are given to the sub-pattern generators 122, 123, 124, and the main patterns generated by the main pattern generator 121 are supplied to the sub-pattern generators 122, 123, 124 as arguments P1, P2, P3. Are used to generate patterns to be given to the IC under test 300 from the sub-pattern generators 122, 123 and 124 in the order following the main pattern.

The structure and operation of each unit will be described in detail below. As shown in FIG. 2, the sequence control unit 110 stores a main pattern generation instruction MAIN and a plurality of arguments P1, P2, P3 from the pattern generation instruction storage area 113B of the instruction memory 113 for each sequence control instruction.
Occurs. FIG. 3 shows an example of a pattern program for generating this pattern generation instruction. START #
0 means that the pattern generation is started from the head address output from the program counter 113. NOP is executed at address # 0. NOP means to increment the address by 1. Therefore, in the next row, the address changes to # 1. In the second line, the label LB1 is repeated the number N set by the loop instruction LOOP1. The number of repetitions N is the initial value storage register 1
It is defined by the set value stored in 15.

X <0 (1, 1 described in the first and second lines
2, 3) and X <X + 4 (1,2,3) represent pattern generation instructions. Here, in particular, X <0 and X <X + 4 indicate main pattern generation instructions. X <0 indicates an instruction for initializing the X address register to 0, and X <X + 4 indicates an instruction for adding +4 to the value of the X address register and storing the operation result in the X address register. (1,2,3) is the argument P1,
P2 and P3, and the sub-pattern generators 122 and 12
3124 shows the value to be added to the main pattern.

The relationship between the main pattern generation command MAIN when the pattern program shown in FIG. 3 is executed, the main pattern generated by this main pattern generation command MAIN, and the sub patterns generated by the sub pattern generation units 122-124. Indicates. The main pattern generation command is given to the main pattern generation unit 121 shown in FIG. 1, and the sub-pattern generation units 122, 123, and 124 receive arguments P1 and P, respectively.
By giving 2, P3, the main pattern generator 1
21 is X = 0 as an X address pattern, and the sub pattern generators 122, 123, 124 are X = 0 + 1, X = 0.
+2 and X = 0 + 3 are output. FIG. 4 shows a case where the loop instruction LOOP1 shown in FIG. 3 is repeated 10 times. Therefore, the pattern generation instruction generated in steps 2 to 11 shown in FIG. 4 is X described in the loop instruction LOOP1.
<X + 4 (1, 2, 3) occurs. By giving this pattern generation command X <X + 4 to the main pattern generation unit 121, the main pattern generation unit 121 outputs X = 4 as the main pattern, and each sub pattern generation unit 12
2, 123, and 124 are patterns X = 4, X = 4 + 1, X = 4 + 2, and X = 4 + as shown in the second cycle t of FIG.
3 is output.

In this way, the main pattern generator 1
21 and the sub-pattern generators 122, 123, and 124, the main pattern X = 0, X = 4, X = 8 for each step.
... followed by a pattern having a continuous order X = 1, X =
2, X = 3 and X = 5, X = 6, X = 7, and X = 9, X
= 10 and X = 11 are output. FIG. 6 shows a main pattern generator 121 and sub pattern generators 122, 123, 12
4 shows a concrete example. Main pattern generator 12
1 is four registers REG1, REG2, REG3, R
It can be configured by EG4, one adder ALU, two multiplexers MUX1 and MUX2, and a mask gate MASK.

The sequence control unit 1 is provided in the register REG1.
Main pattern generation instruction X <0 or X <X + from 10
4 or the like is input and the value of X is stored. Register REG
An argument is given to 2 from the sequence control unit 110.
The argument 0 is stored in the register REG2 of the main pattern generation unit 121. The multiplexer MUX1 initially selects the register REG1, adds the value of X stored in the register REG1 and the value stored in the register REG2, and stores the addition result in the register REG3. When the pattern generation instruction is X <0, X is initialized to 0 and stored in the register REG1. Therefore, the adder ALU has X = 0 + 0.
And stores X = 0 in the register REG3. The value of X stored in the register REG3 is the multiplexer MUX.
2 and the masking gate MASK to output to the output terminal TA through the pattern delay circuit 125. The maximum value of the pattern applied to the IC under test 300 is set in the register RG4. When the value of the register REG3 exceeds the set value of the register REG4, the mask gate MA
SK has a value greater than or equal to the setting value of the register REG4 under test I
It is prevented from being applied to C300. The pattern delay circuit 125 converts the test pattern generated by the main pattern generating unit 121 into the sub pattern generating units 122, 123, 12
4 is delayed by the same time as the delay time in
It is provided to output the test patterns to A to TD in the same phase.

Register R of main pattern generator 121
When the pattern generation command X <X + 4 is input to EG1,
X = 4 is stored in this register REG1. As a result, the adder ALU calculates X = 4 + 0 and stores the calculation result in the register REG3. Therefore, the main pattern is X = 4. Next, the sub pattern generators 122 to 12
The configuration and operation of No. 4 will be described. Since the sub pattern generators 122 to 124 have the same configuration, only the sub pattern generator 122 will be described here. The sub-pattern generation section uses registers REG2, REG3, REG4
3 registers and 2 multiplexers MUX1,
It is composed of the MUX 2 and the mask gate MASK. In the multiplexer MUX1, main patterns X = 0, X = 4, X generated by the main pattern generator 121 are generated.
= 8 ... Is input. The argument P1 is input to the register REG2 from the sequence control unit 110 (FIG. 2). In this example, the case of P1 = 1 is shown. This argument P1 = 1 is stored in the register REG2. (Sub-pattern generator 12
Arguments 2 and 3 are stored in the register REG2 of 3 and 124). When the main pattern generation unit 121 generates the main pattern X = 0, the adder ALU calculates X = 0 + 1 and stores the calculation result X = 1 in the register REG3. Therefore, the sub pattern X = 1 is output to the output terminal TB. Next, when the main pattern generation unit 121 outputs the main pattern X = 4, the sub pattern generation unit 122
The adder ALU calculates X = 4 + 1 and stores the calculation result in the register REG3. As a result, the output terminal TB
The sub-pattern X = 5 is output to. In this way, in each of the sub-pattern generators 122 to 124, the main pattern signal X = which is generated by the main pattern generator 121 in each step 1, 2, 3 ... 0, X = 4, X = 8 ...
Pattern signals X = 0, X = 1, arranged in a desired order
X = 2, X = 3, X = 4, X = 5, X = 6, X = 7 and X = 8, X = 9, X = 10, X = 11 in each cycle t
It outputs to the output terminals TA to TD every -1, t, t + 1 ....

The patterns output to the output terminals TA to TD are input to the input terminals IA to ID of the multiplexing circuit 500 shown in FIG. The multiplexing circuit 500 includes input terminals IA, IB,
Flip-flops 501, 502, 50 for IC and ID
3, 504 are connected to each of these flip-flops 50
Patterns 1 to 504 generated by the pattern generator 120, such as X = 0, X = 1, X = 2, and X = 3, are latched by the clock CLK1 shown in FIG. 8A. Each flip-flop 5
Each latch output of 01 to 504 is output to the clock CLK shown in FIG. 8C in the 4-input 1-output type multiplexer 506.
It is selected and taken out in the cycle of 2, and further timed by the flip-flop 507 and output to the output terminal TQ. The output terminal TQ has a high-speed pattern signal H of 4 × speed shown in FIG. 8D.
The IP is output according to a predetermined order. Reference numeral 505 shown in FIG. 7 denotes a counter for counting the clock CLK2, and the count output of the counter 505 controls the switching of the multiplexer 506.

[0024]

As described above, according to the present invention, the flip-flops 501 to 50 constituting the sequence control unit 110, the pattern generation unit 120 and the multiplexing circuit 500.
Even if 4 is composed of a circuit which operates at the same speed as the conventional one, it is possible to generate a high-speed pattern signal having a speed several times that of the multiplexing circuit 500. Therefore, the multiplexing circuit 500
If the multiplexing number N is selected as N = 4 as in the above-described embodiment, a circuit operating at 100 MHz is used to obtain 400 MHz.
It is possible to generate a high-speed pattern signal. Further, by increasing the number of multiplexing N, it is possible to generate a pattern signal at a higher speed.

Further, according to the present invention, the main pattern generation instruction is provided with an argument, and the sub-pattern for multiplexing is generated by this argument. Therefore, the program creator defines only the main pattern and executes the program. Should be created. Therefore, there is an advantage that a program for high-speed pattern generation can be easily created. Further, according to the present invention, the main parts such as the sequence control unit 110 and the pattern generation unit 120 may be configured by a circuit equivalent to a conventional circuit, so that it can be manufactured at low cost. Furthermore, since it is not necessary to adopt an ultra-multi-stage pipeline structure, there is a practical advantage that the entire structure can be made small.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a block diagram for explaining the configuration of a sequence controller used in the embodiment shown in FIG.

FIG. 3 is a diagram for explaining an example of a program for operating the sequence control unit shown in FIG.

FIG. 4 is a diagram for explaining a relationship between a pattern generation instruction generated when the program shown in FIG. 3 is executed and a pattern generated by this pattern generation instruction.

FIG. 5 is a waveform diagram for explaining the operation of the present invention.

FIG. 6 is a block diagram for explaining a specific embodiment of a main pattern generating section and a sub pattern generating section used in the present invention.

FIG. 7 is a block diagram for explaining a specific embodiment of the multiplexing circuit used in the present invention.

8 is a waveform chart for explaining the operation of the multiplexing circuit shown in FIG.

FIG. 9 is a block diagram for explaining an entire conventional technique and a memory test apparatus.

FIG. 10 is a block diagram for explaining the configuration of a conventional sequence control unit.

[Explanation of symbols]

 110 Sequence Control Unit 120 Pattern Generation Unit 121 Main Pattern Generation Unit 122 to 124 Sub Pattern Generation Unit 125 Pattern Delay Circuit 130 High Speed Pattern Generator 500 Multiplexing Circuit

Claims (3)

[Claims] 1. A pattern generating instruction with an argument that defines a plurality of sub patterns following a main pattern is output from an instruction memory, and a main pattern generating section generates a main pattern according to the pattern generating instruction.
The main pattern generated by the main pattern generation unit is given to a plurality of sub pattern generation units, the main pattern is changed by the plurality of sub pattern generation units according to the above argument, and the main pattern is delayed to be a plurality of sub patterns that should follow the main pattern. Is generated in the same phase as the main pattern, and the main pattern and a plurality of sub-patterns are time-division multiplexed by a multiplexing circuit and taken out to generate a high-speed pattern that changes according to a predetermined pattern generation order. 2. A test pattern signal is generated from a pattern generation unit according to a pattern generation instruction read from an instruction memory provided in a sequence control unit,
In the pattern generator used in the memory test device for applying the test pattern signal to the memory under test to test the operation of the memory under test, the main pattern generation instruction for generating the main pattern from the instruction memory and the main pattern generation instruction Read the arguments that define a plurality of patterns to be generated in a predetermined order, generate the main pattern from the main pattern generation unit according to the main pattern generation command, and generate the main pattern generated from the main pattern generation unit into a plurality of sub patterns. A plurality of sub-patterns are generated in the plurality of sub-pattern generators corresponding to the main pattern in a predetermined order following the argument, and the plurality of sub-patterns and the main pattern are generated. With a multiplexing circuit A high-speed pattern generator which generates a high-speed pattern having a speed several times faster than the read speed of the pattern generation instruction by division multiplexing. 3. The high-speed pattern generator according to claim 2, wherein the main pattern generated by the main pattern generating section is delayed by the pattern delay section, the delay being equal to the delay time in the sub-pattern generating section. A high-speed pattern generator characterized in that the main pattern and the sub-patterns output from the plurality of sub-pattern generators are matched in phase and supplied to the multiplexing circuit.