JPS63185000A - Memory ic checking device - Google Patents

Abstract

PURPOSE:To improve throughput by providing an updating circuit and updating X and Y maximum value registers and X and Y maximum value address registers only at the time of detecting a fail bit of an address and acquiring information for defect mode classification in real time during a test. CONSTITUTION:Updating circuits 22X and 22Y or the like are provided which update contents of an X counter 16X, a Y counter 16Y, an X maximum value register 18X, a Y maximum value register 18Y, an X maximum address register 20X, and a Y maximum address register 20Y each time when a fail bit is detected during the test of a wave test memory IC. Since the number of fail bits on each line in the X direction and the Y direction and their maximum value and addresses are obtained in real time, acquired information is used as information for defect mode classification to start the defect analysis processing just after termination of the test for fail bit detection. Thus, the time from the test to the defect analysis is shortened to improve the throughput.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory IC testing device that tests a memory IC.

[Prior Art] In a conventional memory IC testing apparatus, when a fail bit of a memory IC under test is detected, a fail bit map is created by recording a mark at a corresponding address of the fail memory.

After the creation of such a fail bit map is completed, information on failure modes and types for failure analysis is obtained by software processing based on this fail bit map.

This classification information includes the number of fail bits in the X- and Y-direction lines within the specified address range, their maximum value, and the address of the line that has the maximum value.

[Problems to be solved] However, with such software processing, it takes a long time to acquire failure mode classification information, increasing the time from testing to failure analysis, and reducing the throughput of memory IC inspection equipment. The problem was that it couldn't be improved.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a memory IC testing device that is capable of acquiring failure mode classification information in real time during testing and that improves throughput.

[Means for solving the problem] In order to achieve this objective, the present invention provides a memo U I
In a memory IC testing device that performs a C test, an X counter and an X counter are used to count fail bits for each line in the
X maximum value register and X maximum value address register for holding the maximum number of fail bits of a line in the direction and the address of that line, respectively; and the maximum number of fail bits of a line in the Y direction and the address of that line, respectively. X maximum value register and X maximum value address register for
It includes an update circuit that updates a counter, an X maximum value register, an X maximum value register, an X maximum address register, and a Y maximum address register.

[Function] - With the configuration described above, the number of fail bits, their maximum value, and address for each line in the X and Y directions can be obtained in real time during a memory IC test, so the test for detecting fail bits can be performed easily. Immediately after completion, failure analysis processing can be started using the obtained information as failure mode classification information.

In this way, since the conventional software processing step for acquiring classification information is eliminated, the time from testing to failure analysis is shortened, and the throughput y) of the memory IC4Q inspection device is significantly improved.

[Embodiment Code] An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing the main structure of a memory IC testing device according to the present invention.

In this figure, 10 is a memory IC to be tested, and 12 is a comparison logic unit that detects a fail bit by comparing the readout signal of the memory IC10 with the expected value EX, and outputs a fail pulse FP at the time of detection. .

14 is a fail memory in which a fail bit map is developed, and when a fail pulse FP occurs, the address information IKJA that is supplied to the memory ICl0 at that time is
A mark (for example, "1") is written to an address corresponding to DDR.

The configuration described so far is the same as the conventional one. There is also a pattern generator for generating the address information ADR1 expected value EX, etc., but this is also the same as the conventional one, so it is omitted in the figure.

Although the fail memory 14 can be omitted, it is provided in this embodiment to enable failure analysis using a fail bit map.

16x and 16y are X for counting the number of fail bits for each line in the X direction and Y direction, respectively.
counter and X counter.

18x and 18y are an X maximum value register and an X maximum value register for holding the maximum values of fail bits of lines in the X direction and Y direction, respectively.

Further, 20X and 20y are an X maximum value address register and an X maximum value address register for holding the address of the line with the maximum number of fail bits in the X and Y directions, respectively.

22x and 22y respectively control the counter 16x116y and the register 18xs 18y in real time each time a fail bit is detected (every time a fail pulse FP occurs) during the test of the memory IC 10.
This is an update circuit that updates t 20x and 20y.

In addition, fail memory 14, each counter 16x116y
And each register 18x118y120xs20y can be accessed from a central processing unit (CPU) not shown.

24 is an internal address generator. This is a memory IC
After testing l0, change the target address range and
It is used to generate the address information necessary when recalculating the maximum fail bit value and its address.

28x and 26y respectively address information ADR (
This is a multiplexer for selecting one of X and Y two-dimensional address information (X and Y two-dimensional address information) or X1Y address information generated by the internal address generator 24 and supplying the selected one to the update circuits 22x and 22y.

The input selection of this multiplexer 28xs2By is controlled from the CPU side.

FIG. 2 is a circuit diagram showing an example of the circuit configuration of the update circuit 22X122'I.

30x and 30y are increment circuits that perform increment control of the X counter 16x and the X counter 16x, respectively. When a fail pulse FP is generated, these read the value at the position of the X1Y counter 16x11E3y corresponding to the line specified by the address information given through the multiplexers 28x and 2By, and set the value obtained by adding 1 to the value at the same position. It is something to do.

However, multiplexer 2 is installed on the internal address generator 24 side.
When E3X, 26y are controlled, update circuit 30x
130y reads and outputs the counter value, but updating of the counter value is inhibited from the CPU side.

32x and 32y are respectively increment circuits 3
This is a comparator that compares the output value (updated value) of 0x130y with the values of the X1Y maximum value registers 18x and 18y, and outputs an update signal when the former exceeds the latter. This update signal is given to the load control circuit 34x134y.

36x and 38y are registers in which the CPU sets address ranges from which failure mode classification information is to be obtained.

Comparators 38x and 38y each compare the address information given from the multiplexer 26x126y with the address range set in the register 38x138y, and output a match signal if the address is within the address range. This coincidence signal is transmitted to the load correct arrival circuits 34x, 34.
given to y respectively.

The load control circuits 34x, 34Y include a comparator 32x1
The update signal is sent from 32y, and the comparison F438x1
When a match signal is sent from the increment circuit 38y, the output values of the increment circuits 30x and 30y are set in the X and Y maximum value registers 18x and tsy, respectively, and the address information given from the multiplexer 26x1'26y is set to X%. Set in the Y maximum value registers 20x and 20y, respectively.

Next, the operation of acquiring failure mode classification information in real time during the test of the memory ICl0 will be described.

Before starting the test of memory ICl0, fail memory 1
4. Each counter 18x11E! y, each register 18x1
18y120x120y is cleared. Further, the multiplexer 28x128y is controlled to select address information ADH, and the address range is set in the register 22x122y.

After that, during the test of the memory ICl0, the fail pulse F
When P occurs, it is recorded in the fail memory 14. At the same time, the x, X counter 16x s 16 Y is incremented by the increment circuit 30 X N 30 y.

Also, the address at this time is within the address range set in the registers 38x and 36y, and the increment circuit 3
The output value of 0x13oy is the X, Y maximum value register 18x,
If the value of tsy is exceeded, the load control circuit 34x13
4y sets the new fail bit maximum value in the X1Y most populated registers 18x and 18y, and
The address information at that time is set in the X1Y maximum value address register 20 xs 20 y.

In this way, when the test for all addresses in the memory ICl0 is completed, a fail bit map is completed on the fail memory 14, and the number of fail bits for each line in each of the XNY directions X1Y counter 16xslE3
Obtained by Y.

Also, within the address range set in registers 38x and 3ey, the maximum number of fail bits for lines in the X and Y directions and the address of that line are displayed in each register.
Obtained at 8X% i8y, 20X% 20y.

In this way, the failure mode classification information is obtained at the same time as the test, so the failure analysis program can be immediately run on the CPU.
It can be executed on the side and perform analysis processing such as classification of memory rcio failure modes.

In addition, in the failure analysis process, the address range is changed,
When the failure mode classification information within the address range is required, registers 18xt 18y120x120y are cleared under control from the CPU side,
A new address range is set in registers 22x, 22y, incrementing of increment circuit 30x130y is suppressed, and multiplexer 26x12
8y is switched to the internal address generator 24 side.

Thereafter, when the internal address generator 24 is activated, the maximum value of the fail bits of the lines in the X direction and the Y direction is determined within the address range set in the registers 3E3x and 3ey by the operation of the update circuit 22x122y as described above. and its address can be found quickly.

Further, as in the past, other necessary information can also be obtained from the fail bitmap by software processing.

Although one embodiment has been described above, the present invention is not limited thereto.

For example, the circuit configuration of the update circuit 22x122y may be modified in various ways as long as high speed performance is not impaired, and implementation as firmware is also permitted.

Furthermore, in the embodiment described above, the number of fail bits, its maximum value, and address are acquired as failure mode classification information, but other information may also be acquired at the same time.

[Effects of the Invention] As is clear from the above description, according to the present invention, information for failure mode classification can be obtained in real time during testing without using software processing, which improves the throughput of memory IC testing equipment. can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing a main part configuration of an embodiment of a memory IC testing device according to the present invention, and FIG. 2 is a circuit diagram showing an example of an internal circuit configuration of an update circuit in FIG. 1. 10... Memo UIC112... Comparison logic section, 14.
...Fail memory, 16X...X counter, 16y
...X counter, 18x...X maximum value register,
18y...Y maximum value register, 20x...X maximum value address register, 20y...Y maximum value register, 2
2x122y...Update circuit, 24...Internal address generator, 26 xs 2 B Y...Multiplexer.

Claims (2)

[Claims] (1) In a memory IC testing device that tests memory ICs, an X counter and a Y counter are used to count fail bits for each line in the X and Y directions.
A counter and an X to hold the maximum number of fail bits of a line in the
Maximum value register and X maximum value address register, Y
A Y maximum value register and a Y maximum value address register for holding the maximum number of fail bits of a line in the direction and the address of that line, respectively, and the memory under test I
an update circuit that updates the X counter, Y counter, X maximum value register, Y maximum value register, X maximum address register, and Y maximum address register each time a fail bit is detected during the test of C. A memory IC inspection device characterized by: (2) The update circuit has a register in which address ranges in the X direction and Y direction are set, and only when a fail bit of an address within the address range set in this register is detected, the 2. The memory IC testing device according to claim 1, wherein a maximum value address register, a Y maximum value register, and a Y maximum value address register are updated.