JPS63222399A - Auxiliary ram test circuit - Google Patents

Abstract

PURPOSE:To shorten the test time of a RAM by executing the change of writing data and the comparison of the writing data and reading data during one shift in. CONSTITUTION:Respective scanning paths are independently disposed so as to execute a shift operation and a data input. In the mass production step of the RAM 9, the data output of the RAM 9 is inputted to a comparator 13 in parallel, this input is compared with the parallel input of writing expected data from the scanning path 8c and the data output of the RAM 9 is checked according to the coincidence detection thereof. In a development step, at the time of checking the writing data at every bit of a designated address, the data output of the RAM 9 is directly inputted to the path 8c in parallel, input data is outputted serially by one and one bit to a terminal 7c and the writing data is checked at every bit. Further, a test using effectively all cycle series is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the testability design of semiconductor devices.

[Conventional technology]

First, I will explain the scan path. FIG. 4 is a configuration diagram showing an example of a scan path type test auxiliary circuit. In the figure, 1 is a scan register, 2 is a parallel input terminal, 3 is a parallel output terminal, 4 is a mode switching terminal, 5 is a serial input terminal, 6 is a clock input terminal, and 7 is a serial output terminal. A plurality of scan registers 1 are connected in series to form a shift register.

Next, the operation will be explained.

By setting the mode switching terminal 4 to serial mode, a serial shift is performed every time a clock is applied to the clock input terminal 6, a shift out bit is output to the serial output terminal 7, and data is shifted in from the serial input terminal 5. do. On the other hand, by setting the mode switching terminal 4 to the parallel mode, data applied to the parallel input terminal 2 is taken into the scan register every time a clock is applied to the clock input terminal 6. In either mode, the data held by the scan register is output to the parallel output terminal 3.

The scan canvas can operate as described above, so test data can be shifted in in serial mode and applied to the circuit under test through the parallel output terminal, and response data from the circuit under test can be fetched into the scan register in parallel mode and can be run in serial mode. It can be shifted out to the serial output terminal. Therefore, the number of terminals required for testing is small (for example, in the case of the circuit shown in Figure 4, only four terminals are required: mode switching terminal 4, serial input terminal 5, clock input terminal 6, and serial output terminal 7). The device can be constructed at low cost and is used as a test auxiliary circuit.

Next, a test auxiliary circuit for random access memory (hereinafter referred to as RAM) using this scan canvas will be explained.

FIG. 5 is a circuit diagram showing an example of a conventional RAM test auxiliary circuit. Here, a RAM having n address bits and m data bits is shown. In the figure, 8a, 8b,
8c is a scan canvas similar to that in FIG. 4, 5a and 5b are serial input terminals, 6 is a clock input terminal, 7a and 7c are serial output terminals, 9 is a RAM, 10 is an address terminal, 1
1 is a data input terminal, and 12 is a data output terminal. Scan canvas 8a has address terminal 10d, scan canvas 8
b is connected to the data input terminal 11, and the scan canvas 8c is connected to the data output terminal 12.

Next, the operation will be explained.

To read data from the RAM 9 during a test, set the read address one bit at a time to the serial input terminal 5a while applying a clock to the clock input terminal 6, and when the address is aligned on the scan canvas 8a, read the RAM. After setting the scan canvas 8C in parallel mode and taking in the output data appearing at the data output terminal 12, the scan canvas 8C is set in the serial mode and a clock is applied to the clock input terminal 6, thereby outputting the RAM output data from the serial output terminal 7c. Read out one bit at a time. Therefore, n+m shift operations are required to read data.

To write data to the RAM 9 during testing, a clock is applied to the clock input terminal 6 while setting the write address to the serial input terminal 5a and the write data to the serial input terminal 5b one bit at a time, and the scan canvases 8a and 8b are When the address and data are complete, the RAM write operation is performed. Therefore, in order to align the address and data, a shift operation for the number of bits, whichever is larger, m or n, is required.

To test RAM, it is necessary to write and read at least once per address. Shift operations for the number of bits, whichever is larger, m or n, are required.

[Problem that the invention seeks to solve]

Since the conventional RAM test auxiliary circuit is configured as described above, during testing, it is necessary to perform a shift operation several times per address, that is, in the above example, at least the number of bits of m or n, whichever is larger, is required. Therefore, there is a problem that the test time increases and the test cost of the semiconductor device increases.

The present invention has been made to solve the above-mentioned problems, and aims to shorten test time by reducing the number of shifts required when testing a RAM, and to obtain an inexpensive semiconductor device.

[Means for solving problems]

In the RAM test auxiliary circuit according to the present invention, the scan canvases connected to the address terminal, data input terminal, and data output terminal of the RAM are provided independently so that shift operations and data input can be performed independently, and the scan canvases are connected to the data output terminal. A comparison circuit is provided to determine whether the parallel output of write expected data input to the connected scan paths and the parallel output of write data of the RAM match.

[Effect]

In the present invention, by adopting the above-mentioned configuration, it is possible to conduct a test using effectively all cycle sequences, and it is possible to shorten the RAM test time.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

1 shows a RAM test auxiliary circuit according to an embodiment of the present invention. In the figure, 3a, 3b.

8c is the same scan path as in Fig. 4, scan path 8
a serially inputs the address signal input to the terminal 5a using the first clock signal 6a, outputs the input address data in parallel to the address terminal 10, and then outputs the input address data to the address terminal 10 in parallel.
9, and scan path 8b is connected to terminal 5b.
The write data input to the second clock signal 6b
The input write data is output in parallel to the data input terminal 11 to write the data to the specified address, and the scan path 8c
is connected to the data output terminal 12, serially inputs the same expected write data as the write data inputted to the terminal 5c using the third clock signal 6c, and outputs the inputted expected write data in parallel. 5a, 5
b, 5c are serial input terminals, 6a, 6b, 6c are clock input terminals, 7a, 7b, 7c are serial output terminals,
9 is a RAM, 10 is an address terminal, 11 is a data input terminal, 12 is a data output terminal, and 13 is the input of the parallel output of the write data of the RAM 9 and the parallel output of the write expected data of the third scan path. , a comparison circuit that compares the two inputs and detects a match, 1
4 is a comparison result output terminal.

Next, the operation will be explained.

The circuit shown in Figure 1 is connected to the address terminal, data input terminal, and data output terminal of the RAM so that each scan path can be independently shifted and input data. , at the mass production stage of RAM, the data output of the RAM is input in parallel to the comparator circuit 1-3 as described above, and the input and scan path 8C are
Compare the expected data written from the parallel input with the
By detecting the coincidence, the data output of the RAM can be checked. Further, the circuit of FIG. 1 can perform the same operation as the conventional circuit of FIG. 5. That is, in the development stage of RAM, it is necessary to check the write data for each bit of the specified address. In such a case, the data output of the RAM is directly input in parallel to the scan canvas 8C, By serially outputting data one bit at a time to the output terminal 7C, write data can be checked for each bit. Furthermore, this circuit allows tests to be performed effectively using full period sequences.

First, the full period series will be explained using FIG. 2. n
A complete periodic sequence of bits is a sequence of n consecutive bits from 0 to 2.
It is a bit sequence that contains all the values of '-1 only once. Second
The diagram is 0001001101011110000 4
The full period sequence of bits is shown. In the figure, 000
It can be seen that the bit sequence 1001101011110000 contains all four consecutive bits from 0 to 15 (-2'-1) only once (see decimal representation). Generally, it is known that a full period sequence of n bits exists.

Next, it will be explained that if this full cycle sequence is applied to the circuit shown in FIG. 1, it is possible to effectively test the RAM.

Figure 1 shows R with n address bits and m data bits.
It shows AM. Since a RAM having such a configuration is considered to be m RAMs each having n address bits and 1 bit of data connected, only 1 bit of 0 and 1 needs to be considered as data during testing.

The following explanation will be given assuming that n=4 and m=5 in FIG.

The entire cycle sequence shown in FIG. 2 is applied to the scan path 8a in FIG. 1. In other words, while applying a clock to the clock input terminal 6a, 0001001101011110
By shifting in the bit series 000 from the serial input terminal 5a, all addresses from θ to 15 in the RAM address space can be specified (however, as shown in FIG. Street number, number 12,
, , , address 1). This means that
This shows that the address can be updated with just one shift-in. Therefore, if the write data can be changed and the read data can be compared during one shift-in for updating the address, the RAM can be tested in a short time.

It has already been shown that only one bit, 0 and 1, needs to be considered as data during testing. Therefore, it is only necessary to consider two types of 5(-m) bit data, 01010 and 10101, and since these can be mutually transferred to the other state with one shift-in, the scan path 8
I use it to set it to b or 8C. In other words, by controlling the serial input terminal 5b and the clock input terminal 6b, it is possible to set write data (any one of 01010 and 10101) to the scan path 8b during one shift-in for address update. By controlling the serial input terminal 5c and the clock input terminal 6C, the expected read data (any one of 01010 and 10101) can be set in the scan path 8C during one shift-in for updating the address. be able to.

Since the comparison circuit 13 is connected to the scan path 8C, it is possible to instantly compare the read data from the data output terminal 12 of the RAM and the write expected data held by the scan path 8C, and the comparison result is Since the comparison result is output to the output terminal 14, a shift operation for reading is not necessary.

In this embodiment, the test can be effectively performed using the full cycle sequence, so the test time can be shortened and the test cost can be reduced.

In the above embodiment, a RAM having 4 bits of address and 5 bits of data is shown, but this can also be applied to a general RAM having n bits of address and m pinpoints of data.

Furthermore, although the above embodiment shows a test auxiliary circuit for one RAM, for multiple RAMs, the circuit shown in FIG. 1 can be connected in series as shown in FIG. The effect of this can be obtained.

(Effects of the Invention) As described above, according to the RAM test auxiliary circuit according to the present invention, during one shift-in for updating an address using a full cycle sequence, write data can be changed, and write data and Since the read data is compared, the number of shift operations required when testing the RAM can be avoided without reducing the number of shift operations, which has the effect of shortening the test time and reducing production costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a RAM test auxiliary circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a 4-bit full cycle sequence, and FIG. 3 is a diagram showing a RAM test auxiliary circuit according to an embodiment of the present invention. FIG. 4 is a configuration diagram showing an example of a scan path, and FIG. 5 is a configuration diagram showing a conventional RAM test auxiliary circuit. In the figure, 1 is a scan register, 2 is a parallel input terminal, 3 is a parallel output terminal, 4 is a mode switching terminal, and 5
, 5a, 5b, 5c are serial input terminals, s, 6a, 6
b, 6c are clock input terminals, 7.7a, 7b, 7c,
7d, 7e, 7f are serial output terminals, 8a, 8b, 8
c, 8d, 8e, 3f are scan paths, 9 is RAM, 1
0 is an address terminal, 11 is a data input terminal, 12 is a data output terminal, 13. 13c and 13r are comparison circuits, and 14.14c and 14f are comparison result output terminals. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a RAM (Random Access Memory) test auxiliary circuit, an address signal is serially inputted using a first clock signal, and the inputted address data is outputted in parallel to the address terminal of the RAM to determine the address of the RAM. Serially input write data using a first scan path for specifying and a second clock signal, output the input write data in parallel to the data input terminal of the RAM, and write data to the specified address. and a second scan path connected to the data output terminal of the RAM to serially input expected write data identical to the write data using the third clock signal, and output the input expected write data in parallel. a third scan path; a comparison circuit that receives as inputs the parallel output of the write data of the RAM and the parallel output of the expected write data of the third scan path, and compares the two inputs to detect a match; A RAM test auxiliary circuit characterized by comprising: