JPS6373451A - Logical device - Google Patents

Abstract

PURPOSE:To shorten the time needed for change of addresses and data by showing the next address and data via an address counter and an input data counter for each clock input. CONSTITUTION:The flip-flops 110 and 111 function as shift registers and shift the input data received from a scan-in terminal 112 in response to clocks. An address counter 102 and an input data counter 103 work as shift registers in a scan pass mode and then as counters as they are in a RAM test mode respectively. The input data selected by a selection circuit 105 and to be supplied to a RAM 101 is compared with the output data received from the RAM 101 by a comparator 106. A selector 109 transmits the scan pass data in a scan pass mode and then the output of the comparator 106 in a RAM test mode respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Denominator] The present invention relates to a logic device that includes a logic circuit and a RAM and can be easily tested.

[Conventional technology]

FIG. 5 is a diagram showing a test circuit for a logic device including a conventional logic circuit and a memory circuit, as disclosed in, for example, Japanese Unexamined Patent Publication No. 56-168269. In this figure, 101
Ha Tess!・The target RAM 502 is the RAM1
Address register 503 that stores the address value of 01
504 is an output data register that stores the value read from the RAM 101, and 505 is a flip-flop in the logic circuit, which is used as an input data register during testing (not used historically). 113 is the RAM 101
112 and 114 are terminals for scan-in and scan-out, respectively.

Next, the operation will be explained.

This conventional logic device test circuit has the functionality expanded so that the scan-in/scan-out method used for testing logic circuits can also be applied to testing memory circuits.

During testing, when writing data to RAM10I-, address register 502. The address value and data value to be subjected to the RAM test are stored in the input data register 503 using the scan path, and the RAM l is stored using the write enable control terminal 113.
By setting 0I to write enable mode, desired address data in the RAM 101 can be written.

Next, when reading data from RAM 101, write enable control 113 is used to control RAMIO.
If I is set to read enable mode and the address value to be tested is stored in the address register 502 using the scan path, the output data
Data at the specified address in RAMIOI is read to 04. Then, by shifting this data by 1 and scanning it out, the output value can be investigated, and I'tA
You can also test M101.

[Problem that the invention seeks to solve]

The conventional logic device described above is said to require fewer shifts to test RAMiQl, but it is necessary to set the address register 502 and input data register 503 each time the address and input data are changed. In addition, there is an address register 502, an input data register 503, and an output data register 50.
There were problems such as restrictions on the placement of 4.

This invention was made to solve these problems, and there is no restriction on the arrangement of address registers and input data registers, so the output data register can be omitted, and the memory circuit can be tested in a shorter time. The purpose is to obtain a logical device that can perform

[Means for solving problems]

The logic device according to the present invention includes an initializable address counter whose output is connected to the address input terminal of the RAM, and an initializable input data counter that outputs input data to be input to the data input terminal of the RAM. and,
A fixed input data circuit outputs fixed input data to be input to the data input terminal of the RAM, and one of the output of this fixed input data circuit and the output of the input data counter is selected and input to the data input terminal of the RAM. a comparator that compares the data output from the data output terminal of the RAM with the data output from the selection circuit; It also includes a selector for switching between an input data counter and a comparator.

[Effect]

In this invention, the address counter and the input data counter indicate the next address and data each time a clock is input, and the time required to change the address and data can be shortened.

Also, as input data to the RAM by the selection circuit,
It is selected whether to use the output of the input data counter or the output of the fixed input data circuit.

Further, when reading data from the RAM in the RAM test mode, the comparator outputs the RAM test result by making the initial value of the address counter and the selection of input data by the selection circuit the same as when writing.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a logic device of the present invention. In this figure, the same reference numerals as in FIG. 5 indicate the same parts, 102 is an address counter that specifies the address of the RAMIOI, 1o3 is an input data counter that outputs data to be written to the RAM 101, and 104 is the RA
A fixed input data circuit 105 generates fixed input data to be written to the MIOI, and a selection circuit 105 determines whether the input data to be written to the RAM 101 should be input data to the input data counter 103 or fixed input data to the fixed input data circuit. Select. A comparator 106 compares input data and output data of the RAM 101. 107,108
is a switch and is on in scan path mode, RAM
Turn it off when in test mode. 109 is a selector,
Bus switching is performed in scan path mode and RAM test mode. Flip-flops 110 and 111 are logic circuits, which are serially connected circuits in the scan path mode.Furthermore, the flip-flops in the address counter 102 and the input data counter 103 are also connected in the scan path mode.
11 and is connected serially.

In addition, FIG. 1 shows the logic device when testing is performed using the scan path mode and when testing the RAM1Qi, and the circuit when the RAM 101 is used as a normal system is omitted.

The flip flora 7'110, 111 operates as a shift register in both the scan path mode and the rtAM test mode, and flips the input data from the scan-in terminal 112 each time a clock is input. . Switches 107 and 108 are turned on during the scan path mode and turned off during the RAM test mode. The flip-flops in the address counter 102 and the input data counter 103 operate as a shift register in the scan path mode, and operate as a counter using flip-flops in the RAM test mode.

The selection circuit 105 is configured, for example, as shown in FIG. Decode circuit 2 of flip-flop 201
02 and a selector 203.

The number of flip-flops 201 is fixed input data times f
1101, for example, fixed input data circuit 1
If there is one flip-flop 201, there are two types of RAM input data, so only one flip-flop 201 is required. However, when there are two to three fixed input data circuits 104, two flip-flops 201 are required. Here, the flip-flop 201 operates as a shift register in the scan path mode, and outputs the data set in the scan path mode even if a clock is input in the RAM test mode.

The fixed input data circuit 104 is a circuit used when fixed data is written to all addresses of the RAM 101, and may be configured as desired according to the number of input data of the RAM 101 (for example, as shown in FIG. 3 (aL The configuration is as shown in (b).These figures show the case where the number of input data to the RAM 101 is n bits, and in Fig. 3 (a), the fixed input data is 0101... In the case, the third
Figure (b) shows the case of 0011, 0011...

Comparison W106 compares the output data of the selection circuit 105, that is, the input data to the RAM 101 and the output data of the RAM 101, regardless of the scan path mode or the RAM test mode.

The selector 109 is configured to pass the data of the scan path when in the scan path mode, and to allow the output of the comparator 106 to pass when in the RAM test 1 mode.

Next, the operation when performing a RAM test will be explained.

First, switches 107, 108 are turned on, flip-flops 110, 111 . The flip-flops in the address counter 102 and the flip-flops in the input data counter 103 are used as amplifiers, and the selector 109 is set to the scan path mode to form an equivalent circuit as shown in FIG. At this time, the flip-flop in the selection circuit 105 also functions as a shift register. Third, this scan path mode is a mode in which general logic circuits other than the RAM 101 can also be tested.

In this scan path mode, initial setting data for the address counter 102 and selection data for the selection circuit 105 are sent from the scan-in terminal 112, and if the input data counter 103 is selected by the selection circuit 105, Initial setting data for the input data counter 103 is also sent. At this time, the RAM 101 is also operating, but since it is separated by the selector 109, it does not affect the scan path.

Next, after the initial setting of the input data counter 103 is completed, the switches 107 and 108 are turned off, the selector 109 is switched, and the comparator 106 is connected, equivalently shown in FIG. 4(b).
Assume that the circuit shown in Figure 1 is in RAM test mode.

In this state, write enable control terminal 1
13, put RAMl0I in the write enable state, and operate with the same clock as in the scan path mode, the address counter 102 will count up every clock and specify the next address sequentially from the initialized address value. To go.

On the other hand, the input data to the RAM 101 may be the value of the input data counter 103 or the output of the fixed input data circuit 104 depending on the state of the flip-flop 201 in the selection circuit 105. if,
When the value of the input data counter 103 becomes the input data of the RAM 10I, the value of the input data counter 103 is counted up in the same way as the address counter 102, so different data can be input to each address. On the other hand, when the output of the fixed input data circuit 104 is input, fixed input data is written to all addresses of RAM10I.

Next, the scan path mode is set again, and the flip-flop 201 in the address counter selection circuit 105, if necessary, the input data counter 103 is loaded with RAM.
Enter the same value as the initial setting value when writing data to 101. After completing the input, switch to the RAM test mode again and set the write enable control AM101 to the read enable state. When a clock is input to this 1, data at the address specified by the address counter 102 is output from RAM1o1,
This becomes one input data of the comparator 106.

At the same time, the output of the input data counter 103 or the output from the fixed input data circuit 1o4 selected by 11o5 in the selection time is sent as the other input data of the comparator 106. The comparator 106 compares these two data for each pin and outputs the determination result. The result determined in this way is scanned out directly or through the flip-flop 111 at the subsequent stage, and output to the outside. In other words, the RAM 101 has been tested.

〔Effect of the invention〕

As explained above, the present invention includes an initializable address counter whose output is connected to an address input terminal of a RAM, and an initializable input data that outputs input data to be input to a data input terminal of a RAM. A counter, a fixed input data circuit that also outputs fixed input data to be input to the data input terminal of the RAM, and one of the output of the fixed input data circuit and the output of the input data counter is selected to output the data of the RAM. A selection circuit that inputs to the input terminal, a comparator that compares the data output from the RAM data output terminal with the data output from the selection circuit, and a comparator that inputs the input to the input terminal corresponding to the scan path mode and RAM test mode. Since it is equipped with a selector that switches between the input data counter and the comparator, it is possible to fully test the functions of the RAM in a short time, and there are no restrictions on the placement of the address counter, input data counter, etc. This has the effect of increasing the degree of freedom in designing the logical device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the logic device of the present invention, and FIG.
3 is a diagram showing the configuration of an embodiment of the selection circuit, FIG. 3 is a diagram showing the configuration of an embodiment of the fixed input data circuit, and FIG.
), rb) are diagrams showing the circuit in the scan canvas mode and the circuit in the RAM test mode shown in FIG. 1, and FIG. 5 is a diagram showing a conventional logic device. In the figure, 101 is a RAM 11o2 is an address counter, 103 is an input data counter, 104 is a fixed input data circuit, 1o5 is a selection circuit, 106 is a comparator, 107
, 108 is a switch, 109°203 is a selector, 11
0, 111, and 201 are flip-flops, 112 is a scan-in terminal, 113 is a write enable control 114 is a scan-out terminal, and 2o2 is a decoding circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 2 Figure 3 Procedure correction sound (spontaneous) 1. Indication of the incident: Patent Application No. 81-220224 3,
Relationship with the case of the person making the amendment Patent Applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address 2 Marunouchi, Chiyoda-ku, Tokyo Chome 2-3-5
, Claims column 2 of the specification to be amended, Detailed description of the invention column and Drawing 6, Contents of the amendment (1) The claims of the specification are amended as shown in the attached sheet. (2) Delete "the output" from page 5, line 5 and page 13, line 18 of the specification. (3) Similarly, 1 circuit on page 7, line 1, 105 is ``[circuit'', W, and there may be several circuits. 105 is corrected. (4) Correct the same (I゛ fixed input data circuit on page 7, line 3) as “fixed input data circuit 1041.” (5) Similarly, correct the decode circuit 202 of 1 flip-flop 201 on page 8, lines 18-19. is corrected to ``a decoding circuit 202 that decodes the output of one flip-flop 201.'' (6) Fig. 1 is corrected as shown in the attached sheet. Multiple state memory circuits in a circuit can be connected in series to scan in/out data.
An initializable address counter connected to the address input terminal of the engineering RAM in the logic device that enables output, and initializable input data that outputs input data to be input to the data input terminal of the RAM. a counter, a fixed input data circuit which also outputs fixed input data to be input to the data input terminal of the RAM, and one of the output of the fixed input data circuit and the output of the input data counter is selected and the a selection circuit for inputting data to a data input terminal of a RAM; a comparator for comparing data output from a data output terminal of the RAM with data output from the selection circuit; and a scan path mode. A logic device comprising a selector that switches its input between the input data counter and the comparator in response to a RAM test mode.

Claims (1)

[Claims] It has a logic circuit and a RAM, and a large number of state memory circuits in the logic circuit are connected in series to perform data scan/in.
an initializable address counter whose output is connected to the address input terminal of the RAM; and an initializable address counter that outputs input data to be input to the data input terminal of the RAM. An input data counter, a fixed input data circuit that also outputs fixed input data to be input to the data input terminal of the RAM, and one of the output of this fixed input data circuit and the output of the input data counter is selected. a selection circuit for inputting the data to the data input terminal of the RAM; a comparator for comparing the data output from the data output terminal of the RAM with the data output from the selection circuit; 1. A logic device comprising: a selector that switches its input between the input data counter and the comparator depending on the time.