JPH02287734A - Scan path circuit - Google Patents

Abstract

PURPOSE:To restore the states of respective flip-flops for a scan path to states before scan-out operation by selecting the output of a scan-path line which is specified with a control signal by selectors provided to the flip-flops respectively. CONSTITUTION:The flip-flops 2 - 4 for the scan path are provided with auxiliary flip-flops 5 - 7 which hold temporarily the contents of the flip-flops 2 - 4 for the scan path before scanning operation and the selectors 8 - 10 which select outputs, specified with the control signal, among the output of the scan-path line and the outputs of the auxiliary flip-flops 5 - 7 and input them to the flip- flops 2 - 4 for the scan path. Consequently, the states of the flip-flops can be restored to the states before the scanning operation in a time of only one clock and the scanning operation processing time can be shortened greatly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scan path circuit that is incorporated into a logic device such as an information processing device in order to facilitate testing of the logic device.

[Conventional technology]

Conventionally, in this type of scan path circuit, as shown in FIG.
It has a shift register-like configuration in which the data held in each flip-flop 22-24 is read out to the outside, and vice versa, predetermined data is set in each flip-flop 22-24 from the outside. The scan-in operation was performed as follows. In addition, in FIG. 3, 25 is a scan-in signal,
26 is a scan out signal, 27 is a scan mode signal, 28 is a clock, and each flip-flop 22
~24, D is the data input terminal, O is the data output terminal,
C is a clock terminal, and M is a mode selection terminal.

First, in the scan-out operation, each flip-flop 22
After switching the switching mode signal 27 applied to the mote selection terminals M of 1 to 24 from logic "0" to logic "1", clocks 28 are sequentially supplied. The data held in the flip-flop 23 is transferred to the flip-flop 23.
The data held in the flip-flop 22 is transferred to the flip-flop 22, and the data held in the flip-flop 22 appears on the scan-out signal 26. Similarly, at the next clock, the data originally held by the flip-flop 23 appears on the scan-out signal 26, and at the next clock, the data originally held by the flip-flop 24 appears at the scan-out signal 26. appear. FIG. 3 shows only the part related to the scan operation, and in reality, during normal operation when the scan mode signal 27 is held at logic "0", data at a predetermined location in the information processing device 21 is transferred to each flip-flop 22. ~24,
By the scan-out operation described above, the information processing device 21
It becomes possible to read the internal state to the outside.

On the other hand, in the scan-in operation, like the scan-out operation, the scan mode signal 27 applied to the mode selection terminal M of each flip-flop 22 to 24 is switched from the logic "0°" to the logic "I" state, and then the clock 28 A scan-in signal 25 is input in synchronization with the . As a result, the scan-in signal 25 is held in the flip-flop 24 at the first clock. Similarly, when the scan-in signal 25 is input in synchronization with the next clock, it is held in the flip-flop 24, and the data held in the flip-flop 24 is transferred to the flip-flop 23. Furthermore, when the scan-in signal 25 is input in synchronization with the next clock, the value of the first input scan-in signal 25 is sent to the flip-flop 22, and the next value is sent to the flip-flop 2.
3, the last input value is held in the flip-flop 24, and the scan-in operation is completed. The data held in each of the flip-flops 22 to 24 is not shown in FIG. 3, but is given to a predetermined location within the information processing device 21, so that the state inside the information processing device 21 can be read from the outside. It becomes possible to set.

Issue C to be Solved by the Invention M) The conventional scan path circuit is configured and operates as described above, but it has the following problems. That is, if it is necessary to return the contents of each flip-flop to the state before the scan-out operation after reading the data of each flip-flop by the scan-out operation, the data read by the scan-out operation must be written again by the scan-in operation. It often takes a lot of time to return to the original state.

The present invention solves these conventional problems, and its purpose is to provide a scan path circuit that can quickly return the state of each flip-flop to the state before the scan-out operation.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a scan path circuit in which a shift register is constructed by connecting a plurality of scan path flip-flops in series via a scan path line, in which a shift register is provided for each scan path flip-flop. , an auxiliary flip-flop that inputs and holds the output of the scan path flip-flop before the scan operation starts; and a selector that inputs the output of the side specified by the control signal within the scan path flip-flop.

[Effect]

In the scan path circuit of the present invention, when performing scan-in or scan-out, the selector provided for each scan path flip-flop selects the output of the scan path line specified by the control signal. The flip-flops are configured like a shift register, and before the start of the actual scan operation, the auxiliary flip-flop provided for each flip-flop for the scan path reads the output of the corresponding flip-flop for the scan path, that is, the content before the scan operation. Enter and hold. When returning the contents of each scan path flip-flop to the state before scan out after the scan-out operation, each selector selects the output of the corresponding auxiliary flip-flop using a control signal and manually inputs the output to the corresponding scan path flip-flop.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of main parts of an embodiment of the scan path circuit of the present invention, showing only the parts related to the scan operation. The scan path circuit of this embodiment is provided in the information processing device 1, and includes flip-flops 2 to 4 for a plurality of scan paths and auxiliary flip-flops 5 to 7.
and selectors 8 to 10 are the main components.

The mode selection terminals M of flip-flops 2 to 4 for the scan path receive the scan mode signal 13, the clock terminal C receives the clock 14, and the data input terminals of the selectors 8 to 10 corresponding to the flip-flops receive the scan mode signal 13. The outputs are respectively input, and the scan mode signal 13 is set to logic "'
In the state of 1P, the clock 14 changes from logic ``0'' to logic ``'1''.
When it changes to '°, the outputs of selectors 8 to 10 are set internally at that timing. Also, each flip-flop 2~
The data output terminal O of the flip-flop 4.4 is connected to the data input terminals of the auxiliary flip-flops 5 to 7 corresponding to the own flip-flop, and the data output terminal ○ of the flip-flop 4.3 is connected to the scan path line 17.16. Selector 9
．． It is also connected to one input of 8. The scan-out signal 12 is taken out from the data output terminal O of the flip-flop 2.

The scan mode signal 13 is input to the clock terminals C of the auxiliary clip-flops 5 to 7, and the outputs of the corresponding flip-flops 2 to 4 for the scan path are input to the data input terminals thereof. “
The outputs of the scan path clip-flops 2 to 4 are held internally at the timing when the logic changes from 0' to logic "1". Data output terminal 0 of each auxiliary flip-flop 5-7 is connected to the other input of the corresponding selector 8-10. Note that the scan-in signal 11 is sent to the selector 1 provided in the flip-flop 4 for the first scan path.
0 is added to the other input.

The selectors 8-10 select one of the two inputs according to the logic state of the control signal 15 applied from the outside and apply it to the data input terminals of the scan path flip-flops 2-4.

FIG. 2 is a time chart showing the signal waveforms of various parts when the scan path circuit of the embodiment of FIG. 1 is operated.The operation of the embodiment of FIG. 1 will be explained below with reference to FIG. do.

When scanning out data held by the scan path flip-flops 2 to 4 in FIG. 1 and scanning in other data from the outside, the control signal 15 is set to logic "
The selectors 8 to 10 select the scan path line 16, 17 or the scan-in signal 11 by holding the state at 0, and in the normal state, the logic is "o".
The scan mode signal 13 is set to logic "1" as shown in FIG. As a result, the flip-flops 2 to 4 for the scan path become scan mode, and the auxiliary flip-flops 5 to 4 as shown in FIG.
Flip-flops 2 to 4 for scan path corresponding to 7
The data held by the device is input and stored internally. with this,
Flip-flop 2 for scan path before scanning operation
-4 data could be stored in auxiliary flip-flops 5-7.

Next, when the clock 14 is sequentially supplied, as shown in FIG. Pu 4
The scan-in signal 11 is set to , and the data of the flip-flop 2 is output to the scan-out signal 12 . Similarly, at the next clock, the data of flip-flop 3 is transferred to clip-flop 2, and the data of flip-flop 3 is transferred to clip-flop 2.
The data of the flip-flop 4 is set to the flip-flop 4, the next scan-in signal 11 is set to the flip-flop 4, and the data of the flip-flop 3 held by the flip-flop 2 is output to the scan-out signal 12. Furthermore, at the next clock, flip-flop 2 is switched to flip-flop 3.
The data of flip-flop 4, that is, the next scan-in signal 11, is set to flip-flop 3, the last scan-in signal 11 is set to flip-flop 4, and the scan-out signal 12 is set to flip-flop 4. The data of flip-flop 4 held by flip-flop 2 is output. This completes the operation of scanning out the data held by the scan path flip-flops 2 to 4 while scanning in other data from the outside. To shift to normal operation in this state, although not shown in FIG. 2, it is sufficient to set the scan mode signal 13 to logic "0".This causes the scan path flip-flops 2 to 4 to be scanned in. The information processing device 1 can use the data obtained by the information processing device 1.

Next, when returning the contents of the flip-flops 2 to 4 for the scan path to the state before the scan operation, first, the second
As shown in the figure, the control signal 15 is set from the logic "0" state to the logic "1" while the scan mode signal 13 is held at the logic "1".

As a result, the scan path flip-flops 2 to 4 are placed in the scan mode, and each selector 8 to 10 selects the output of the auxiliary flip-flops 5 to 7. Next, in this state, the clock 14 is set to 1 as shown in FIG.
When the clock is supplied, the flip-flops 2 to 4 for the scan path input the outputs of the selectors 8 to 10, that is, the outputs of the auxiliary flip-flops 5 to 7 that hold the data of the flip-flops 2 to 4 before the scan operation. and hold it inside. With this, the contents of the scan path flip-flops 2 to 4 can be returned to the state before the scan operation was performed. When shifting to normal operation in this state, the scan mode signal 13 and control signal 1 are
5 should both be set to logic "0".

〔Effect of the invention〕

As explained above, the scan path circuit of the present invention includes an auxiliary flip-flop that temporarily holds the contents of the scan path flip-flop before the scan operation;
By providing each scan path flip-flop with a selector that selects the output specified by the control signal from the output of the scan path line and the output of the auxiliary flip-flop and inputs the selected output to the scan path flip-flop. , it is possible to return the state of each flip-flop to the state before the scan-out operation in as little as one clock, making it possible to significantly shorten the scan operation processing time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of the present invention, FIG. 2 is a time chart of the embodiment of FIG. 1, and FIG. 3 is a block diagram of a conventional example. In the figure, 1... Information processing devices 2-4... Flip-flops 5-7 for scan path
... Auxiliary flip-flops 8 to 10 ... Selector 11 ... Scan-in signal 12 ... Scan-out signal 13 ... Scan mode signal 14 ... Clock 15 ... Control signal Patent applicant Ibaraki NEC

Claims (1)

[Scope of Claims] In a scan path circuit in which a shift register is configured by connecting a plurality of scan path flip-flops in series through scan path lines, a scan path circuit is provided for each of the scan path flip-flops, and a scan path circuit is provided for each of the scan path flip-flops, and an auxiliary flip-flop that inputs and holds the output of the campus flip-flop; and an auxiliary flip-flop provided for each of the scan path flip-flops, which is specified by a control signal of the output of the corresponding auxiliary flip-flop and the output of the scan path line. 1. A scan path circuit comprising: a selector whose output on the other side is input to a scan path flip-flop.