KR19990036739A - Test circuit for macro - Google Patents

Abstract

There is provided a test circuit for the macro inside the LSI which minimizes the increase in the number of test terminals and performs the macro test in a short time. The test circuit includes a test route through which a number of macros can be connected and provide data independent of the normal operating circuit, a selection circuit or terminal for selecting a macro to be tested through the test route, and a test Data retention circuitry for holding test data to be provided in the path. Data of different clock cycles provided from the same external terminal are temporarily stored, the stored data is connected to the test path, and the macro selected inside the LSI is tested independently of the conventional circuit.

Description

Test circuit for macro

TECHNICAL FIELD The present invention relates to LSI testing, and more particularly to a test circuit of macro cells integrated in an LSI.

In general, a conventional LSI macro test uses an external terminal using a testing bus or other route that can set and observe the values of a test pattern prepared for a macro independently of a normal circuit (a circuit for normal operation). Set and observe the value directly from

1 is a block diagram illustrating a conventional macro test technique. Here, reference numerals 220 and 221 denote test objects, that is, macro cells. In Fig. 1, the arrows indicate the inputs / outputs for the conventional circuit, and the conventional circuit portion is omitted. The macro has a test input / output terminal and is connected to a circuit inside the macro through these terminals. Reference numerals 216 to 219 denote input test buses, and reference numerals 222 and 223 denote output test buses to which two macros 220 and 223 are connected. Which macro to select and test is controlled in response to the output of decoder 215 based on control signals applied to terminals 205 and 206. Test data is input at the external terminals 201, 202, 203, and 204. The clock is applied to the terminal 207. Reference numerals 208, 209, 210, 211, 212, 213, 214, 225, and 226 denote buffers.

In FIG. 1, the decoder 215 outputs a value of "1" to a terminal indicated by the symbol 0 when the value of the decoding result of the decoder 215 is 0, and a terminal indicated by the symbol 1 when the decoding result is 1. Outputs a value of "1", outputs a value of "1" to a terminal indicated by symbol 2 when the decoding result is 2, and outputs a value of "0" to another terminal. Here, the terminal indicated by the symbol 3 is an empty terminal.

Each of the macros 220 and 221 has four test input terminals TI1, TI2, TI3 and TI4, and two test output terminals TO1 and TO2. The terminal marked C is a clock terminal to which a clock is directly applied at terminal 207 without passing through the test path. The symbol TE represents a test enable. If the value " 1 " is output to TE, the macro is judged to be in the test state and a connection to the test bus is made. In this case, the six terminals of the macros 220 and 221 need to be connected to external terminals via a test bus. For example, in FIG. 1, if three terminals 201, 204 and 228 are typically used, it is necessary to add three terminals for testing. In detail, there is a disadvantage in that it is necessary to add terminals for a test unless the number of macro terminals is at least less than the number of connectable external terminals.

In addition, a method of using a boundary scan register according to the standard of IEEE1149.1 around a macro and a shift register structure as disclosed in Japanese Laid-Open Publication No. 254570/1996, serialize values to macro terminals. There are other ways to shift and set to.

Fig. 2 is a block diagram showing the technique disclosed in Japanese Laid-Open Publication No. 254570/1996, wherein the macro cells 301 and 306 are the shift register groups 305 and 306 for input and the shift register groups 309 and 310 for output. Each is provided. In this configuration, the values provided to the external input terminals 303 are stored in parallel in the input register group 304, and the output results are transferred to the output register group 308 by shifting each macro output value to output terminal group 307. Observation is performed. In Fig. 2, SC represents a scanning clock, and RC and R'C represent command signals.

Each test for a pattern of macro cells requires multiple clock cycles to shift the values. When each of the macro cells 301 and 302 has 50 input terminals, at least 101 cycles are required only for inputting a pattern of test data in order to test the macro cell 302. At least 50 cycles are required even when the macro cell 301 is bypassed or when the output register group 309 of the macro cell 301 is used as the output register group 308.

As described above, in the prior art, in order to set a pattern of test data, it is necessary to shift the values while the number of clock cycles is equal to the number of macro terminals, so that the testing time is long.

As described above, in the conventional macro test technique, when the number of external terminals required for the normal circuit is smaller than the number of terminals necessary for the macro test, it is necessary to add external terminals. In addition, there is a disadvantage that it is necessary to shift while the number of clock cycles corresponds to the number of macro terminals, so that the testing time becomes long.

It is therefore an object of the present invention to provide a test circuit for macros inside an LSI that can make the testing time of a macro test as short as possible without increasing the number of external terminals for testing.

In order to achieve the above and other objects, the present invention is directed to a test route in which a plurality of macros are connected and test data can be provided independently of a normal operating circuit, and to be tested through the test route. A test circuit for a macro inside an LSI test circuit is provided that includes a selection circuit or terminal for selecting a macro and a data retention circuit for holding test data to be provided in a test path. Data of different clock cycles transmitted from the same external terminal is stored, and the stored data is connected to the test path, so that the macro selected inside the LSI is tested independently of the conventional circuit.

In detail, when the number of external terminals required for the macro test is smaller than the number of terminals used in normal operation, data is stored in a memory element connected to the terminal, and one terminal is divided in a time-wise manner. An increase in the number of terminals is suppressed by setting data of different terminals of the macro to be tested. In addition, the test data is basically input in parallel with the test terminals of the macro, and the testing time is minimized by using the memory element only for the insufficient number of terminals.

1 is a block diagram illustrating an example of a conventional macro test technique.

2 is a block diagram illustrating another example of a conventional macro test technique.

3 is a block diagram showing a first embodiment of the present invention;

4 is a block diagram showing a second embodiment of the present invention;

FIG. 5 is a diagram showing an example of a control waveform in the embodiment shown in FIG. 4; FIG.

6 is a diagram showing an example of a control waveform in the case where data is continuously input / output.

7 shows a table representing a pattern of test data for testing macros.

FIG. 8 shows a table showing test data input / output through an external terminal when a test is performed using the test circuit shown in FIG.

<Explanation of symbols for main parts of the drawings>

115, 132, 133, 134: selector

116: decoder

127, 128: test macro

117, 120, and 131: flip flops

129, 130: test bus for output

3 is a block diagram showing a first embodiment of the present invention.

In this embodiment, reference numerals 127 and 128 are macros to be tested. In Fig. 3, the arrows indicate the inputs / outputs for the conventional circuit, and the conventional circuit portion is omitted.

The macro has test input / output terminals and is connected to circuits inside the macro through these terminals. If no delay or specific problem occurs, a normal terminal can be used as the test terminal. Reference numerals 123 to 126 denote test paths for input and are referred to herein as test buses. Reference numerals 129 and 130 denote test buses for output to which two macros 127 and 128 are connected. Which macro should be selected and tested is controlled in response to the output of decoder 116 based on control signals applied to terminals 105 and 106.

Here, the decoder 116 outputs a value of "1" to the terminal indicated by the symbol 0 when the value of the decoding result of the decoder 116 is 0, and "1" to the terminal indicated by the symbol 1 when the decoding result is 1; A value of 1 " is outputted, and if the decoding result is 2, a value of " 1 " Here, the terminal indicated by the symbol 3 is an empty terminal.

Each of the macros 127 and 128 has four test input terminals TI1, TI2, TI3 and TI4, and two test output terminals TO1 and TO2. The terminal marked C is a clock terminal to which the clock at terminal 107 is directly supplied without passing through the test path. The symbol TE indicates a test enable. If the value " 1 " is output to TE, the macro is judged to be in the test state and a connection to the test bus is made. In this case, for example, the input terminal 101 and the bidirectional terminals 104 and 136 can be used during the test. Reference numerals 102 and 103 denote control input terminals added to realize the test circuit of the present invention.

Reference numerals 108 to 110 and 112 to 114 denote input buffers, and reference numerals 111 and 135 denote bidirectional buffers.

Reference numeral 115 denotes a selector, which outputs by selecting an input terminal indicated by the symbol 0 when the input at the terminal G is 0 or an input terminal indicated by the symbol 1 when the input at the terminal G is 1. . The selectors 132, 133, and 134 have the same function. When decoder 116 performs normal operation, i.e., when terminal 0 of decoder 116 has a value of "1", selector 115 selects the control signal of terminal 104 during normal operation, In test mode, a fixed value "0" is output.

The bidirectional buffer 111 or 135 is in the input mode when the bidirectional control input is "0" and is in the output mode when the bidirectional control input is "1". Therefore, the decoder 116 represents a test mode, the bidirectional buffer 111 is in an input mode, and the bidirectional terminal 104 is used to transmit a value to the test bus.

The selector 133 is also used to select a signal to be sent to the bidirectional terminal 136 between the normal circuit output and the output from the test bus. The selector 134 is used to select a signal for controlling the mode of the bidirectional buffer 135 but is fixed to select the control signal of the normal circuit in normal operation and to output in the test mode.

When performing a macro test in the device shown according to the prior art, the test buses 123 to 126, 129 and 130 are connected to input / output terminals, resulting in six external terminals. In this embodiment, however, values, that is, test data to be input and output, are temporarily stored in flip-flops 117 and 120 on the input side and flip-flop 131 on the output side, respectively. Input test data for test buses 123 and 124 is provided at terminal 103, other input test data for test buses 125 and 126 is provided at terminal 101, and outputs of test buses 129 and 130 are provided. Test data is observed at terminal 136. As such, only three external terminals 101, 103 and 136 are used and only three flip-flops are used. In the embodiment of Figure 3, the symbol D represents the D input, Q represents the output, C represents the clock input, and a D flip-flop that takes the D input value when the input to terminal C changes from "0" to "1". (117, 120, and 131) are used.

In the embodiment of FIG. 3, latches 118, 119, 121, and 122 are used, where symbol D represents D input, Q represents output, and E represents enable input. When the value of E is " 1 ", the input terminal D enters through mode and performs output. These latches retain their previous state until data can be stored in flip-flops through terminals 101 and 104 and provided to the macro as a test pattern. If a test can be made, the test is enabled and stable by these latches. Therefore, the ratchets are unnecessary when the data to be tested is sampled only at the time when the macro is completely synchronized with the macro clock and the test input is not changed at any time other than the time when the macro is to be synchronized.

In this embodiment, input test data provided to the external terminal 101 and stored in the flip-flop 117 once is provided to the test bus 126. Input test data of the external terminal 101 is directly applied to the test bus 125. The value provided to the external terminal 104 and stored once in the flip-flop 120, that is, the input test data, is provided to the test bus 124. Test data of the external terminal 104 is applied directly to the test bus 123. For output, the output test data of the test bus 129 is once stored in the flip-flop 131 and then observed at the external terminal 136, while the output test data of the test bus 130 is directly at the terminal 136. Observed.

In this embodiment, the enable signals of the latches 118, 119, 121, and 122 on the output side are used as control signals for the selector 132, and new input test data is provided to the test bus via the latch on the output side. At this point the output data of the test bus 129 is observed.

In this embodiment, one test clock terminal is required and a control input terminal may be required in some cases, but a normal terminal can also be used. Thus, unlike the number of terminals required for normal operation, the terminal overhead is extremely small. In addition, a minimum number of flip-flops is provided to allow testing with fewer clock cycles while maintaining minimal terminal overhead.

Fig. 4 is a block diagram showing a second embodiment of the present invention, showing only the input / output section up to the testing path.

Reference numerals 412 and 414 denote input test buses, reference numerals 415 to 417 denote output test buses, reference numerals 401 to 403 denote input terminals, and reference numerals 404 to 406 denote inputs. Buffers 407, 408, 418, and 420 represent flip-flops where symbol D represents D input, Q represents output, and C represents clock input. These flip-flops are designed as D-type flip-flops that store and output a value, that is, data when the clock changes from "0" to "1".

Reference numerals 409 to 411 denote ratchets in which the symbol D represents the D input, Q represents the output, and E represents the enable input. If the value of E is " 1 ", the input D enters the pass mode and outputs.

Reference numerals 419, 421, and 422 denote selectors, each of which selects an input terminal represented by symbol "0" when input G is "0" or symbol "1" when input G is "1". Select the input terminal marked with to output.

Reference numeral 423 denotes an output buffer, reference numeral 424 denotes an output terminal, and reference numeral 425 denotes a control signal for switching between test mode and normal mode. In this embodiment, when the control signal 425 is "0", the test mode is set. In Fig. 4, the connection with the conventional circuit is shown by the arrow, and the conventional circuit is omitted.

The latches 409 to 411 retain the previous state until the next data of the input test buses 412 to 414 can be set and the test can be performed, and no change occurs in the input test bus at any point other than the clock synchronization point. If there is no problem, it can be omitted.

In this embodiment, the input test data is provided directly to the external test terminal 401 at the input test bus 412, and the input test data provided at the external terminal 401 once stored in the flip-flop 407 is input test bus. Input test data provided at 413 and provided at the external terminal 401 and stored in the flip-flop 408 via the flip-flop 407 is provided to the input test bus 414. Output data of the output test bus 417 is directly observed at the external terminal 424. The output data of the output test bus 416 is once stored in the flip-flop 420 and observed at the external terminal 424. The output data of the output test bus 415 is once stored in the flip-flop 418 and then transmitted via the flip-flop 420 and observed at the external output terminal 424.

If the number of external terminals that can be used for the macro test is less than half the number of the macro terminals to be used for the test and the number of external terminals cannot be increased, the data input / output is performed in three steps as in the second embodiment. It is necessary to perform the above.

FIG. 5 is a diagram showing examples of input test data and control waveforms used in the embodiment shown in FIG. 4. The waveforms of the test data and control signals to be provided at the external terminals 401, 402 and 403 are shown.

Reference numerals 451, 453, 455, 456, 458, 460, and 461 denote the time points at which the input test data is provided to the external terminal 401, and reference numerals 452, 454, 457, and 459 denote the external terminals ( It represents the time point at which the test clock provided at 402 changes from " 0 " to " 1. "

Here, input test data is provided on input test bus 414 at points 451 and 456, input test data is provided on input test bus 413 at points 453 and 458, and input test data is provided at time points (e. 455 and 460 are provided on input test bus 412.

Input test data is simultaneously provided on input test buses 412-414 at time points 455 and 460 in response to an enable signal provided at external terminal 403, and this state continues until time points 456 and 461. Subsequently, the input test bus is disabled and this state is maintained until the next data is provided. If the racing at the time of change of terminal 401 or 403 becomes a problem at time 456 or 461, the time period during which the input test data provided at output terminal 403 is set to "1" is shortened. It is done.

On the other hand, for the output, a test result is obtained when the input test data provided from the input test buses 412 to 414 are simultaneously updated at the time point 455, and the output data of the output test buses 417, 416, and 415 are Observed immediately before each of the time points 456, 458, and 460.

FIG. 6 is a diagram showing input test data and control waveforms when data is continuously input / output. The waveforms for input test data, test clock, and test enable are shown in order from the top. Referring to FIG. 3 as an example, input test data is provided at the external terminals 101 and 104, a test clock is provided at the external terminal 102, and a test enable signal is provided to the external terminal 103.

FIG. 6 shows an example in which the input test data to each test bus can be set up to a total of two steps, a single data setting step to flip-flop and a direct data input step from an external input.

Reference numerals 501, 503, 504, 506, 508, 509 and 510 denote the timing of data change, and reference numerals 502 and 505 denote the timing of test clock change from "0" to "1".

In this case, two cycles are used between time 501 and time 504, time 504 and time 507, respectively, while one pattern of input test data for the macro to be tested is provided.

The input test data, once to be stored in the flip-flop, is provided at the external terminals at points 501 and 504, the input test data is provided at the external terminals at points 503 and 506, and the test enabled state is displayed at the time points 503 and 502. 506 is realized. In this way, the input to the macro is updated at the same time.

In the case of the output, the output on the test bus to which the output terminals are directly connected can be observed in cycles of the enabled state, and after one cycle the output of the test bus obtained through the flip-flop can be observed.

After the time point 507, the data stored in the flip-flop can be used as input data as it is, and only the data of the test bus directly connected from the external input terminal is changed every cycle to perform the test. In the case of the output, only data of a test bus directly connected to an external terminal is observed and tested.

In the embodiment of Fig. 3, when the macro 127 is selected and tested, the input test data to TI1 and TI3 is fixed, while the input test data to TI2 and TI4 is updated every cycle, and the output data of TO1. Can be observed every cycle.

As can be seen from the above, in the case of an input terminal, a control signal or other signal with little change is set using a path through a flip-flop for an efficient test, while a direct path from an external terminal is used. Set the data signal or other signal with a lot of change. In the case of output terminals, output terminals connected to sections that can be tested with a fractional pattern in detecting defects are observed from the path through the flip-flop, while requiring multiple patterns to detect the defects. The output connected to the part to be observed is observed from the path which can observe an output directly from an external terminal, and test efficiency improves.

The method of providing the test pattern of FIG. 6 will be described below with reference to the circuit of FIG. 3 as an example.

FIG. 7 is a table showing a test pattern for testing the macro 127, and FIG. 8 is a table showing values input / output through external terminals when the test is performed using the test circuit shown in FIG. .

7 and 8 indicate cycle numbers, and the left columns of FIGS. 7 and 8 represent macro terminals and external terminals, respectively. The cycle number is incremented each time the data entry changes. For the values in the table, the symbol "1" represents a value of 1, "0" represents a value of 0, P represents a pulse whose value changes from 0 to 1 again, and X represents no observation. Indicates.

In Fig. 8, after the fifth cycle, a continuous test mode is set in which the input data is updated every cycle to observe.

In the case of data in the first cycle of FIG. 7, data to terminal TI1 is set in the first cycle of terminal 101 in FIG. 8, data to terminal TI2 is set in the second cycle of terminal 101, and terminal TI3. The data to the terminal 104 is set in the first cycle of the terminal 104 and the data to the terminal TI4 is set in the second cycle of the terminal 104. Data of terminal TO1 is observed at terminal 136 in the second cycle, and data of terminal TO2 is observed at terminal 136 in the third cycle.

For data in the second cycle of FIG. 7, data to terminal TI1 is set in the third cycle of terminal 101 in FIG. 8, data to terminal TI2 is set in the fourth cycle of terminal 101, and the terminal Data to TI3 is set in the third cycle of terminal 104 and data to terminal TI4 is set in the fourth cycle of terminal 104. Data at terminal TO1 is observed at terminal 136 in the fourth cycle.

The data in the third, fourth, and fifth cycles of FIG. 7 correspond to the data in each of the fifth, sixth, and seventh cycles of FIG. 8. Input data to terminals TI1 and TI4 are provided to terminals 101 and 104, respectively. Data at terminal TO1 is observed at terminal 136.

In the LSI test circuit of the present invention, when the number of terminals provided with macro test data directly from an external terminal is smaller than the number of terminals used in normal operation, the number of terminals is stored by storing the input test data in a memory element connected to the terminal. Can be suppressed and one terminal is distributed in a timed manner to set the data for the different terminals of the macro to be tested. In addition, the test data is basically provided in parallel with the macro test terminal, and the memory device is used only for the insufficient number of terminals, thereby efficiently minimizing the testing time.

In addition, when allocating the macro terminal connected to the external terminal and the macro terminal directly connected to the external terminal through the memory element, the testing time can be further efficiently reduced by directly connecting the frequently changing macro terminal to the external terminal.

Claims (8)

In the test circuit for testing the macro inside the LSI, A test route through which a plurality of macros are connected and capable of providing data independent of a normal operating circuit, a selection circuit for selecting a macro to be tested through the test route, and providing to the test route A data holding circuit for holding test data to be made, wherein data of different clock cycles provided from the same external terminal are temporarily stored in different data holding circuits, the stored data being provided in parallel to the test path, and the LSI Internally selected macros are tested independently of the conventional circuitry. A test circuit, characterized in that. In the test circuit for testing the macro inside the LSI, Holds a test path capable of connecting a plurality of macros and providing data independent of a normal operating circuit, a terminal for selecting a macro to be tested through the test path, and test data to be provided to the test path A data holding circuit for storing data of different clock cycles provided from the same external terminal temporarily in different data holding circuits, the stored data being provided in parallel to the test path, and the macro selected inside the LSI Independent of the conventional circuit A test circuit, characterized in that. The method of claim 1, The test path holds the previous value until the required test data is stored in the data holding circuit which holds a value connected to the test path and a data update timing signal is supplied to the test path to input a value equal to the value. Connected to a circuit for A test circuit, characterized in that. The method of claim 1, A portion of the test path is directly connected to the external terminal without going through the data retention circuit so that data can be directly set from the external terminal to the macro terminal, and also another portion of the test path to set data from the data retention circuit. To do the test using A test circuit, characterized in that. The method of claim 1, At least one of the data retention circuits has a mode for passing input data through output data, A part of the test path is directly connected to the data retention circuit from the external terminal in the mode of passing the input data to the output data, so that data can be directly set from the external terminal to the macro terminal, and further from the data retention circuit. Doing tests using other parts of the test path to set up data A test circuit, characterized in that. The method of claim 1, A test output path and an output holding circuit for temporarily holding an output from the test output path, wherein the data held in the output holding circuit can be observed from the same external terminal at different clock cycles. A test circuit, characterized in that. The method of claim 6, Part of the test path is directly connected to the external terminal without going through the output holding circuit, and can directly observe the data of the macro output terminal. A test circuit, characterized in that. The method of claim 6, A portion of the test path is directly connected to the external terminal via a selector without passing through the output retaining circuit and capable of directly observing data at the macro output terminal. A test circuit, characterized in that.