TW396540B - Macro test circuit - Google Patents

Abstract

The invention discloses a macro test circuit for large scaled integrated circuit (LSI), which can reduce the increase of the terminal number of the macro test circuit and complete the macro test in short time period. The test circuit includes a test row which is connected to multiple macros with data supplied independent on a general action circuit; a selection circuit or a terminal used for selecting macro being tested via the test row; and a data holding circuit used for holding the test data and sending the data to said test row. The data of different pulse periods delivered from the same external terminals is stored, the stored data is connected to said test row, and said macro selected from the LSI is tested independent on the general circuit.

Description

V. Description of the invention (1) The present invention relates to a kind of LSI, which wins 2 丨 丨 β ^ Set the test unit of the macro unit in the lake 3, especially about-species (-^ νΛ ^ :; set test The test bus is used to be independent of the normal action macro two skins. The "shape value 'can be -Ht AL * 1? Tower is set up or turned, and I I, to set directly from the external terminal and Observation 觐: ¾ 觐 test, using the straight 221-generation technology diagram 'here' number 22〇 is related to the general circuit in Figure 1 'arrow represents: = / wheel-out terminal' for testing, And through this terminal, the bus, the circuit phase S in the set; numbers 216 to 219 indicate the rotation test • and 222 and 223 represent the output test bus, and the output test: the bus system and two macros 22. Connected to 221; based on the addition; = 2 out of the control signal 'macro pair of J206—response to the output of the decoder 215, the selection and testing of the macro is controlled; the test data is from external terminals 201, 202 , 203 and 204 inputs, and the pulse system is provided to a terminal 207, numbers 208, 209, 210, 211, 212, 213, 214, 225 And 226 represents the buffer. Here, 'when the decoder 21 5 decodes the result, its value is 0, and this decoder 215 outputs a value.'] To the terminal whose generation number is 0; when the decode result is If the value is 1, it will output a value "丨" to the terminal with the generation number 丨; when the decoding result is 2, it will output a value "丨" to the terminal with the generation number 2; and output a value of 0 to Other terminals; here, the terminal indicated by the code 3 is an empty terminal.

V. Description of the invention (2)

Both the macros 220 and 221 have 4 input test terminals Til, TI2, TI3 f TI4 ′ and two output test terminals τ〇ι and ⑺? ; The terminal code-named is the k-pulse terminal (clock terminal) 'that is, the pulse is directly provided to the terminal', which is not provided to the terminal via the test column at terminal 2 07; the signal te means to start the test, when a value "! " Output to TE, you can determine that this macro is in a test state ’and complete the connection with the test bus. In this example, the 6 terminals of the macro 220 and 221 must be connected to the external terminals through this test bus. For example, in Figure 1, if 3 terminals 2 0 1, 2, 0 4 and 2 2 8 are used, , You must add 3 terminals for testing; specifically, the disadvantage is that as long as the number of macro terminals is not less than the number of external terminals that can be connected, you need to increase the number of terminals used for testing. More than this ’other methods include: using an IEEE’ Institute of Electrical and Electronic

Engineers) i149. 丨 Standard boundary scan register ("scan register") to surround the macro, or a shift register structure as disclosed in Japanese Patent Laid-Open Publication No. 2 54 570/1996, for Continuously shifting and setting the value of the macro terminal.

// First paragraph: The figure is a block diagram showing a technique disclosed in Japanese Patent Laid-Open Publication No. ^ 54 ^ 0 ^ /) 996. Here, the macro unit 3 (n and 302 are individually and temporarily shifted). Register groups 305 and 306—both provided for rotation, and 309 and 310—are provided for output; in this configuration, the value of the input external input terminal 303 is stored in parallel in the input temporary Register group 304, the output result is transferred to the output register group 308 by moving the value of each macro output, and the output terminal group 307 completes the inspection. Here

C: \ Program Fi1es \ Patent \ 2126-2194-P. Ptd page 5 V. Description of the invention (3) In the figure, SC represents the scanning pulse, and RC and R, C represents the indication signal. Each test of this macro unit's graphics requires a large number of pulses to move the value; in the case that the macro units 301 and 302 are provided with 50 round-in terminals, the test unit is intended to test 302, the test data for only one graphic input requires at least 101 cycles, and that is, in the case where the macro unit 301 is a bypass, or the macro unit 30 is rotated out The register group 309 is also used as 308, and a minimum of 50 periods is also required. As mentioned above, in the conventional technology, the test data for setting a pattern must be shifted when the number of pulse cycles is equal to the number of macro terminals, thus increasing the test time and causing disadvantages. As described above, in the conventional macro testing technology, when the number of external terminals required for a general circuit is less than the number of external terminals required for a macro test, the number of external terminals must be increased. It is necessary to complete the shift between macros and sub-numbers, but this shift is disadvantageous due to the long test time. In view of this, the object of the present invention is to provide a macro test circuit located in LS j, and the test circuit can reduce the test time of the macro test as much as possible without increasing the number of external test terminals. In order to achieve this and other objectives, the present invention provides / a kind of macro test circuit located in the L SI, and the macro test circuit includes: a test sequence 'the test sequence is connected to a plurality of macros, and wherein The supply of test data can be independent of the general operating circuit; a selection circuit or terminal, through which the test line is selected for macro testing; and a data holding circuit for

Explanation of March (4) Submitted to the test bar with no test data. The data of the same clock cycle is stored by the same external terminal, and the data is connected with this test row, and the selection located in the LSI is equal to: The test is independent of the general circuit. In particular, in the case where the number of external terminals required for the macro test is less than the number of terminals used for the / 艨 action, the data is stored in the phase-speed memory unit at the end of the disk and one end is used The time-sharing method is to set different data of the macro 2 and test it, so the increase in the number of terminals is reduced. What's more, the test data are parallel input macro test terminals, and the memory cell weight is used for a few terminals, so the test time is reduced. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. An example of known macro testing technology; Figure 2 shows other examples of conventional macro testing technology; Figure 3 is a first embodiment of the present invention; Figure 4 is a second embodiment of the present invention; Figure 5 FIG. 4 is an example of the control waveform of the embodiment shown in FIG. 4; FIG. 6 is an example of the control waveform of continuous data input / round out; FIG. 7 is a test data chart of a test macro; and Figure 8 shows a chart of testing performed by using the test circuit of Figure 3 to input / output test data through external terminals.

V. Description of the invention (5) Simple explanation of symbols 101 input terminal 102 control input terminal 103 control input terminal 104 bidirectional terminal 105, 106, 107 Terminal I 0 8, 1 0 9, 11 0 input buffer 111 bidirectional buffer 112 , 113, 114 input buffer II 5 selector 11 6 decoder 11 7 flip-flop 11 8, 11 9 latch 120 flip-flop 121, 122 latch 1 2 3, 1 2 4, 1 2 5, 1 2 6 test bus 1 27, 1 28 macro 1 29, 1 30 test bus 131 flip-flop 132, 133, 134 selector 135 bidirectional buffer 136 bidirectional end T 11, TI 2, TI 3, TI 4 input Test terminal T01, T02 clock terminal TE start test C pulse input terminal Q output terminal D input terminal E start input terminal G terminal 201, 202, 203, 204 external terminal 205 '206' 207 terminal 2 08 '20 9' 210 ' 211 '212, 213, 214 Buffer 2 1 5 Decoder 2 1 6, 2 1 7, 21 8, 21 9 Input test bus 2 2 0, 2 21 Macro 2 2 2, 2 2 3 Output test bus

C: \ ProgramFiles \ Patent \ 2126-2194-P. Ptd page 8

225, 226 buffer 228 terminal 301, 302 macro 303 external input terminal 304 input register group 305, 306 shift register group 30 7 output terminal group 308, 309, 310 output register group RC , R 'C indication signal SC scan pulse 401, 402, 403 input terminals 404, 405, 406 input buffers 407, 408 flip-flops 409, 410, 411 latches 41 2, 41 3, 41 4 input test bus 415 , 416, 417 output test bus 418, 420 flip-flop 419, 421, 422 selector 423 output buffer 424 output terminal 451, 453, 455, 456, 458, 460, 461 Timing time (input test data) 452, 454, 457, 459 timing time (test pulse) 501, 503, 504 '506, 507, 5 08, 509, 510 timing time (data change) 5 0 2, 5 0 5 timing time (pulse change) P pulse X not It is necessary to observe that the present invention will be described with reference to the drawings. Fig. 3 is a first embodiment of the present invention. In this embodiment, 127 and 128 are macros to be tested; in FIG. 3, the front part refers to the general input / output circuit, and the general selection circuit is omitted.

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The macro has been tested for input / output and is connected to the circuit inside the macro through this terminal. If there are no delays or other special problems, general terminals can be used as test terminals; numbers 123 to 126 indicate test rows for input, and are referred to herein as test buses; numbers 129 and 130 refer to The test bus for output is connected to the two macros 127 and 128. Based on the control signals applied to the terminals 105 and 106, the response of the macro to the output of the decoder 116 is controlled. Here, when the decoding result by the decoder 116 is 0, the decoder 116 outputs a value " 1 " to a terminal from the code 0; when the decoding result is 1, the code is 1 output a value " 1 " to a terminal; when the decoded result is 2 ', a value from the code 2 is output "i " to a terminal ·, and a value " 0" to other terminals ; The terminal code 3 here is an empty terminal. Both the macros 127 and 128 have 4 input test terminals τιι, τΐ2, TI3 fTI4 'and two output test terminals 1 < 〇1 and 忉 2; the terminal code c is a clock terminal, that is, The pulse is provided directly to the terminal, not at terminal 107. It is provided to the terminal through the test column; the signal τ e refers to the start of the test. When a value " 1 " is output to TE, the macro can be determined. Attach to a test state and complete the connection with the test bus. In this example, for example, input terminal 101 and bidirectional terminals 104 and 136 can be used for testing, while numbers 102 and 103 refer to the input terminals for control, which are added for understanding the present invention. Test the circuit. The numbers from 1 to 8 to 11 0 and 11 2 to 11 4 represent the input buffers; and 11 1

5. Description of the invention (8) and table 135 bidirectional buffer. The number 11 5 represents _, Ai Chikan. "The round-in with code number 0. When the input value of terminal G is 0," the input terminal is used for output-output. The selectors U2 and 133 are the decoder 116. In the case of normal operation, the selector 115 selects the terminal ^ 1 " When performing the normal operation, a fixed value " 〇 " Decentralized in: Dry: When the input is "°", the bidirectional buffer 111 or 135. When a two-way control turn is "1", it is tied to the output core. Therefore, when the decoder 11 6 refers to the dry The rabbit, the head is called the drawing bucket, and the .M-direction buffer 111 is placed in the wheel-in grip. This double-value is to the test bus. "'And this bidirectional terminal 1.4 is used to transmit η 出 ί 外 # ΐ Ξ ΐ 133 in the general circuit output and test bus ^ out Sunma Tian / Lu used to select a signal transmitted to the bidirectional terminal U6; The selector moves Λ _ _ its mode signal, but fixed output, circuit control signal in test mode, and test mode 〖2 ==. Know the configuration of the operation and do-macro test, test confluence = 123 to 12, 129, and 130 are connected to the input / output terminals, and accordingly ϋ = 6 external terminals are required. However, in this embodiment, the test data of the input and output test data is prepared. 丨, μ w ^ The values of Τ ^ ^ 117 ^ ΙΟΠ and 卄 are temporarily stored on the input side and d are 117, 120 'on the output side and temporarily stored in the flip-flop ΐ3ι. The input test bus 123 and 124 input test f㈣ Input 103

V. Description of the invention (9) 2 ′ and other input test data of input test buses 125 and 126 are provided by the fund; With this method, only 3, 103 and 136, and 3 flip-flops are required. In the embodiment in FIG. 3, the _ flip-flops 117, 120, and 131 are used, where the code is publicly substituted into the input terminal of the meter, and C represents a pulse input terminal / when the value of input terminal c is 0 ; Change to ,, 1 ", including the value of D input. ^ Locks 118, 119, 121, and 122 are used in the embodiment of Figure 3,, D represents the D input, Q represents the output, and e represents the value of a start input "" When this input D is in the pass mode, and is stored in the flip-flop by the terminal mm〇4 is available: Available as a test pattern. When a test can be completed时 ， # by these latches, = the test system is stably started and completed; and this latch is fully synchronized with the pulse input only once when investigating the instance, so this latch is not necessary in the case of planning to test the macro. And even if the test input is changed by any method, there is no problem with the different timing method of synchronous timing. In this embodiment, one is added to the external terminal 丨 〇1 and the test data once stored in the flip-flop 11 7 Is provided to the test bus 丨 26, while the external input test data is directly Supply to the test bus 125; add to the terminal 104 and pass the value stored in the flip-flop 丨 20 or input test data to the test bus 1 24; test data of the external terminal 〇04 are straight. Supply to , Test the bus 123; for the output, when the test bus of the test bus 130 is tested directly by the external terminal 1 3 6 to test the test bus 丨 2 9

5. Description of the invention (10) The terminal 136 of the data department was stored in the flip-flop 131 once before inspection. In the example, 'as provided on the wheel-in side via this latch-a new wheel mt ^ ^ ^ ^ ^ II11 8 Wide section: the start-up U' is used as the selector 1 3 2 control U ' And the output data of the test bus 129 is timing observation. There must be one clock terminal for testing. It may be too small, and even if the minimum number of terminals is maintained to maintain the minimum value of the upper terminal, there is = inverter layer: person, as a test. 1 = 4 in a smaller number of pulse periods. Fig. 4 shows a path between the second embodiment of the present invention, showing only the input / output portion. And the number of test roads 41 2 to 41 4 indicates the rotation test output output test bus; 401 to 403 represent _, and 15 to 417 represent the input buffers M07, 408, and 418; and 404 to 406. D stands for β input terminal, Q stands for wheel output terminal, and c flip-flop, among which the flip-flops are designed to be used as D flip-flop, the pulse input terminal; when this is reduced to " ", storage And output the value or data, that is, when the pulse is changed from "" to the numbers 4 0 to 4 11 to indicate latching, where, represents the wheel out end, and E represents a start-in end; ^ represents the D input, and Q, This input terminal D is in the pass mode, and the value of: is " 1 " The numbers 419, 421 and 422 represent the selector, and the output. When the input value of terminal G is 0, one dollar is selected. Device: input terminal of wind horse 0; or prepared

V. Description of the invention (π) ::: When the input value is 1, the input terminal with code number 1 is used to release 425 table number table-output buffer '424 indicates-output terminal, and the silver number is used to switch tests Mode and-general mode. Here, when “25” is “〇”, it is set to test the circuit of the model. You are connected to the general circuit by a row, and the other circuit is omitted in the figure. Latch 409 to 411 will maintain the previous state-until the next one; output test buses 412 to 414, and can complete the test, and = any change in the bus 5 ... step timing is different Z ,, 'In case of problems In the case of the private target, the input test data is directly connected to the input test bus 412 on the external terminal 401; the external terminal 401 a once stored the input test data of i ft07. Supply to the test bus 41 3; 3 to the external terminal 4G1 and store it in the flip-flop through the flip-flop cap. The input test data is provided to the input test bus 414: the output data of the output J machine bus 41 7 is directly Observed from the external terminal 424 钤 钤 ° 1 The output data of the test bus 416 was stored in the flip-flop 42 (), 'and at = observed; the output data of the output test bus 415 was stored in ^ f = 18, and passed The flip-flops 420 are transmitted in sequence, and observed at the child 424. 丨i Output ^ Under the condition that the number of external terminals that can be used for the macro test is less than one and a half of its external terminals, and the number of external terminals cannot be increased, the data input / output must be at three or more levels. a Shang Yuancheng, just C: \ Program Files \ Patent \ 2126-2194-P.ptd the 14th

Fig. 5 shows examples of input test data and control waveforms used in the embodiment shown in Fig. 4 '. The test data and control signal waveforms are supplied from external terminals 401, 402, and 403. V. Description of the invention (12) As in the second embodiment. The numbers 451, 453, 455, 456, 458, 460, and 461 indicate the timing of the test data supplied to the external terminal 401, and 452, 454, 457, and 459 indicate the timing of the test pulse. The test pulse is provided by " When "0" is changed to "1", it is supplied to the external terminal 402.

Here, input test data is supplied to input test bus 414 at timing times 451 and 456; input test data is supplied to input test bus 413 at timing times 453 and 458; and input test data is supplied to input at timing times 455 and 460. Test bus 412. ”This input test data is simultaneously supplied to the input test buses 412 to 414 at the timing of 455 and 460, and responds to the enable signal supplied to the external terminal 403 ′, and this state will continue individually until the count g Time 456 and 461. Next, this input test bus is disabled, and this state is maintained until the next data is added. When the time 456 or 461 is timed, the change is accelerated at 401 or 403. In the case of timing time, problems will occur. The time period for input test data set to "1" for 0 months to external terminal 4 03 should be shortened. ^ On the other hand, regarding the output, when the input test data is supplied to the input test buses 412 to 414, the held test results are updated at the same time as the time 455. Observe the rotation data on the output data buses 417, 416, and 415.

Figure 6 below shows' Wheel rotation when inputting / outputting this kind of data continuously> Material and control waveform 'Inputting the waveform of test data' The test pulse canonical test type 2 test enable is sequentially displayed from above; see Figure 3 is used as the "child" turn-in test data to be supplied to the external terminals i 0 1 and 丨 04, this test ^ is supplied to the external terminal 丨 〇2, and the test enable signal is supplied to the external 1 η meaning. | 嗰 子 Figure 6 shows an example of the situation; the input test data input to each test confluence can be set up to two levels in total: a single data setting level to the flip-flop and a direct data input level from an external input 5 (η ,,

504, 506, 507, 508, 509, and 510 indicate the time and time when the data changed, and 502 and 505 indicate that the test pulse is changed from " 0 ". Timing time. In this example, 'between 501 and 504, and between 504 and 507, two types of cycles are used, in which the pattern for the macro is provided, and the input test data is stored in the flip-flop. Enter the test data and supply it to the external terminal at the timing time of 501; this input test data is supplied to the external terminal at the timing of time ", and understand this enabled state at the timing of 503 and 5 0 6 1.

= Output and 5, during the period of enabling state, the test bus can be observed ^ ^ output to the output terminal, which is directly connected; and through the flip-flop, you can also check that the test bus includes one cycle slower . -The data stored in the flip-flops after their time 507 is also valid as output data because the daggers are effective.

V. Description of the invention (14): The data of the two-terminal connection test bus is changed every cycle to complete the second & ϋ turn out and & only the data of the test bus directly connected to the external terminal can be observed To complete the test. In the example shown in Fig. 5i, when the macro 1 2 7 is selected to complete the test, the input test data of input and output of TI3 is fixed; and the input test data input to T12 and T14, P 丨 II __ handle M Λ Α ^ ^, the parent period is updated, and the output asset at T01 can be observed in each period. Taxi = soil description can clearly understand that, regarding the input terminals, the control signal or other signals that change the test efficiency are used through positive definite; and the data signals or other signals with many changes are connected to the external terminals set up. Regarding the output terminal: 'Yes, if there is an error, the output terminal should be checked; while the output connected to an area requires most maps to observe the error, the output is observed by the column, where the 3' to detect External terminals were observed to enhance testing effectiveness. , ^ Can directly refer to the circuit diagram in Figure 3 as an example, and then follow the method of test pattern supply.卩 The 7th figure in the 6th figure will be described as a table showing the test for the giant and the 8th figure, showing when using the test as shown in Figure 3 ^ test pattern 'test' input / output via external terminals value. 'The circuit is completed. The first column of Figures 7 and 8 indicates the number of cycles, and the bar at the left end of the figure corresponds to the macro terminal and the outside, and in Figures 7 and 8, the number of cycles is as Every now and then, the selling round increases and increases;

Country I: C: \ ProgramFiles \ Patent \ 2126-2194-P.ptd on page π 5. In the numerical value in the description of the invention (15), the code is " 1 ", which represents the value of 1; and the code is " 〇 " 'represents the value of 0; p represents a pulse, and the value of the pulse changes from 0 and then returns from 1 to 0; and X represents no need to observe. In Figure 8, in the fifth cycle and after, a continuous test mode is set. The input data is updated every cycle to complete the observation.

In the data of the first cycle in FIG. 7, the data of the input terminal τιι is set in the first cycle of terminal 101 in FIG. 8, and the data of the input terminal TI2 is set in the second period of terminal 101 The data of the input terminal TΙ3 is the data set in the first cycle of terminal 104, and the data of the input terminal T4 is the data set in the second cycle of terminal 104; the data output from terminal T〇1 'In the second cycle, it is observed from terminal i 36, and the data output from terminal T02 is observed from terminal 136 in the third cycle. In the data of the second period in FIG. 7, the data of the input terminal τ n is set ^ The data of the third period of the terminal 10 1 in FIG. 8, and the data of the input terminal τΐ 2 is set in the first period of terminal 10 The data of four cycles, the data of input terminal τι 3 is the data of the third cycle set at terminal 丨 04, the data of terminal τΐ4 is input, and the data of the fourth cycle of terminal 104 is from terminal τ〇ι The output data is observed from the terminal 丨 3 in the fourth cycle. Department ϊ The data in the third, fourth, and fifth cycles correspond to the data in the fifth, the third, the fourth, and the fourth cycles in Figure 8, respectively, such as the data from the mountain τ, the drought ^ k, and the cycle; input to The input materials of terminal /, TI4 are individually supplied to terminal 101 plate 104. The data output from terminal T01 is provided by terminal 136 = and in the LSI test circuit of the present invention, it is directly supplied by external terminals

Macro test data to the terminal +, and the number of terminals is less than one. By storing the input test data to the § Ji Yi body connected to the terminal, it is possible to suppress the increase in the number of terminals. One end is the separation time to set the data for testing. The test data is basically input to the macro test terminal in parallel, and = a small number of terminals that effectively reduce the test time. Only use memory elements. Through the distribution of the macro element r of the memory element, • directly connected to the external terminal; "= =" matching ", which can effectively shorten the test time by directly connecting this frequently changed macro exon. 〃 r H, although the present invention has been disclosed in the preferred embodiment as above, but it limits the present invention. Anyone who is familiar with this technology cabin can change and moisten within the scope of God and He; The attached application patent shall prevail. Protection of the Moon

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Claims (1)

6. Scope of patent application J. A type of macro test circuit ~ test series, which is based on the general action circuit and is supplied to select a test macro; and is expected to be sent to this test series, with the same pulse cycle data The stored data is selected in parallel. The macro test is unique. 2. A kind of macro test electricity ~ a test line, which is provided in a general action circuit and a data holding circuit. From the same external material, it is temporarily stored in different parallels and sent to the test line, and the test system is independent of the general circuit. Road, which is located with a plurality of giants: one selects electricity and one data is held therein, and is temporarily stored in the test line and is located in a general circuit, which is located with a plurality of giants; one terminal is provided by a holding test terminal. The data holding is located on the connection path of the large-scale accumulation set, which is different from the outside through the circuit, and the bit 0 is connected to the large-scale accumulation set for selecting the data, the different circuits, the body circuit, and the data are used for this test. The information provided by the holding terminal is held in a large integrated circuit, and the data is selected for testing to be sent to the pulse cycle and the options in this storage include independent columns, which are not used for testing, and the body circuit 'includes Independent macro; test data is macro test 3. As described in the scope of the patent application, the test circuit, basin test line is connected to a circuit for holding the previous value, straight, center, The newly tested data is stored in this data holding circuit, and this data is held as needed—connected to the value of the test row, until a data update path is held and supplied to the test Column to enter the same value. D | τ Yinjian signal 4. According to the test circuit described in item 丨 of the scope of patent application, the test line of the vertical part is directly connected to the external terminal, and 'two middle, one has a circuit. The official and industrial data are held to set φ directly from the external terminal. Eight L Lee range = to the macro terminal, #hold the circuit set to just try. ^ 5. If applying for S # wait for the circuit to formula;. Part of the test 'is the method of the external sample, the data M & the test is listed in it, and the test 6. If you apply for the remaining Test rounds are listed, and the output data is held in rounds. The output data can be in different pulses. 7. If the test line that applies for the @@ is a straight circuit and can be viewed directly. 8. If the test line for the special part has a circuit, but after one material. There is at least one benefit range that is listed in this terminal. It can be directly tested by other parts of the benefit range and one output. Among them, the punch period, the profit range is connected to the macro range, and the direct connection selector is connected. , And the other parts of the test series, the data is entered into it by the source ', and the other parts of the test series are used to complete the test circuit described in item 1, wherein the module passes the input data to the output data model. It is connected to the data holding circuit through the mode of inputting data to rotating data, and this is set by the external terminal to the macro terminal. The data is set by the data holding circuit to complete the test. The test circuit described in item 1 further includes a holding power 4 'from the test in the output holding circuit from time to time. The held 2 is observed from the same output terminal. The test circuit described in item 6, the :: terminal, does not go through this round — the holding part has the data of the output terminal. ‘There are the test circuits described in 6 items, from the basin to the external terminals’ without going through the wheel: and directly Dehong: 丨 ρ 勒 ’Observed f