JPS61240174A - Scanning circuit - Google Patents

Abstract

PURPOSE:To make scanning FF adaptable even to a non-synchronous circuit, by selecting the input of scanning FF by providing a data selector. CONSTITUTION:A data selector 11 selects data Data 1 and a non-synchronous clock NSCK 1 corresponding to such a mechanism that a scanning type signal STP comes to 0 at the testing time of a data bus and comes to 1 at the testing time of a non-synchronous clock bus to supply both of them to the data terminal D of a scanning flip-flop SFF 1. A data selector 12 generates a scanning test clock STCK or clock NSCK 1 applied corresponding to a scanning mode signal SM coming to 1 at the time of scanning test and coming to 0 at the time of usual operation to apply the same to the clock terminal of a flip-flop SFF. Therefore, when the signal SM is brought to 1 and the signal STP is brought to 0 or 1, the testing of a data bus or the testing of the non-synchronous clock and scanning FF can be also adapted to a non-synchronous circuit.

Description

[Detailed Description of the Invention] [Summary] A data selector for switching between data and an asynchronous clock is provided on the data input side of a flip-flop constituting a scan circuit, and a clock selector for switching between an asynchronous clock and a scan test clock is provided on the clock input side of the flip-flop. By providing this, it can be applied to asynchronous circuits.

[Industrial application field]

The present invention relates to a scan circuit. A scan circuit is used to test combinational circuits such as gate circuits.
Predetermined data is stored in advance and compared with input data to determine whether the circuit under test is correct or incorrect. This scan circuit has many flip-flops (FF),
By sequentially scanning these FFs and re-extracting the temporarily set internal state, data indicating the location of the failure is generated.

The present invention relates to such a scan circuit.

[Prior Art and Problems to be Solved by the Invention] Generally, in a scan circuit, data is set and retrieved in synchronization with an externally applied clock. Therefore, it is originally designed to be applied to synchronous circuits.

However, some communication-related devices operate using internal clocks. When a scan circuit is used to test a circuit that operates using an internally generated clock, data is provided to the scan circuit using a separate, unique clock.

However, since conventional scan circuits are designed to be applied only to synchronous circuits, they cannot be applied to testing asynchronous circuits, resulting in a problem that their scope of use is extremely narrow.

[Means and operations for solving the problems] FIG. 1 is a diagram showing the principle of the present invention. The data input side of the scan flip flop 1 is connected to the data selector 11.
However, there is also a clock selector 12 on the clock input side.
Each is provided.

The scan input data Si is input from the terminal 13 to the flip-flop 1 in response to the scan shift clock SCK from the terminal IS.

First, scan type signal STP "0" is input from terminal 14, and scan mode signal SM "1" is input from terminal 16.
, the data selector 11 selects Data, and the clock selector 12 selects the scan test clock 5TCK. As a result, the data and the asynchronous clock N5CKI are switched by the data selector 11.

Similarly, if the scan type signal STP is set to "1", the asynchronous clock N5 is set by the clock selector 12.
CKI and scan test clock 5TCK are switched.

Therefore, the flip-flop 1 can also be applied to asynchronous circuits.

〔Example〕

Hereinafter, the present invention will be explained by way of examples with reference to the accompanying drawings.

FIG. 2 is a configuration diagram showing an embodiment of the present invention.

In the circuit shown in FIG. 2, a data selector 11 is connected to a data input terminal 11 of a scan flip-flop 1, a clock selector 12 is connected to a clock input terminal 12, and
The data selector 11 switches between the data Datal and the asynchronous clock N5CK1, and the clock selector 12 switches between the asynchronous clock N5CKI and the scan test clock 5TCK.

The data selector 11 includes a first AND gate 111 having an inverting input, a second AND gate 112, and an OR gate 113.

Similarly, the clock selector 12 includes a first AND gate 121, a second AND gate 122, and an OR gate 12.
3.

On the other hand, this scan flip-flop 1 (SFFI)
In addition to input from the data selector 11 and clock selector 12, scan data Si is input from the terminal 13.
and terminal 1. The scan shift clock SCK, which is the clock 7, is input from ", 1'.

Furthermore, the first AND gate 111 of the data selector 11 receives data from the combinational gate circuit 3, which will be described later.
and the inverted input of the scan type signal STP from the terminal 14, and the above-mentioned STP and the clock N5CKI from the asynchronous system are input to the second AND gate 112, respectively.

The scan type signal STP is 0'' when testing a data bus, and is 1 when testing an asynchronous clock bus.

The first AND gate 121 of the clock selector 12 has
The asynchronous clock N5CKI and the inverted input of the scan mode signal SM are input to the second AND gate 122, and the scan test clock signal 5TCK from the terminal IS and the scan mode signal SM from the terminal 15 are input, respectively.

The scan mode signal SM is always "1" when performing a rescan test using the circuit of the present invention, and is "0" when performing normal operation. Further, the scan test clock signal 5TCK is a clock for operating the flip-flop 1.2 when performing a scan test, and according to the present invention, the asynchronous clock N5CKI is switched to this 5TCK.

The scan flip-flop 2, like the previous flip-flop 1, has a data selector 21 and a clock selector 22 (FIG. 3) connected to its input side.

The truth table of the data selector 11 and clock selector 12 connected to the input side of the flip-flop 1 is as shown in Table 1.

Table 1 In Table 1, SM is a scan mode signal input to terminal 15, and STP is a scan type signal input to terminal 14.

That is, the system mode is a mode during normal operation, and in that case, the scan mode signal SM is "0".

The scan mode is a mode during testing, and the scan mode signal SM is "1" and when the test content is a data bus test, the scan type signal STP is "1".
0'', and in the case of an asynchronous clock test, the scan type signal STP is 1''.

Hereinafter, the circuit of the present invention having the above configuration will be explained based on FIG. 3.

FIG. 3 is an application diagram of an actual test using the circuit of FIG. 2.

In Figure 3, 3 and 4 are combination 6 combination gate circuits, PA
TH is a signal between gate circuits 3 and 4. A scan flip-flop l and its selector 11.12 and a scan flip-flop 2 and its selector 21.22 according to the present invention are connected between the Goethe circuits 3 and 4, respectively.

In advance, input data Si for scanning from terminal 13 to terminal 1.
Serial input is performed using the shift clock SCK from 7. Next, the scan test is performed in two parts.

First, in order to test the data bus, the scan type signal SPT is set to "0" and input from the terminal 14, and the data selector 11 selects [) atal. Further, the scan mode signal SM is set to l'', and the clock selector 12 selects the scan test clock 5TCK. Similarly, the data selector 21 and the clock selector 22 each select [)ata2.5TCK.

As a result, the first AND gate 11 of the data selector 11
1 can be output to the OR gate 113 if Data is input, and can be output to the second AND gate 1 of the clock selector 12.
22 becomes able to output to the OR gate 123 when 5TCK is input.

Next, a pulse clock is input from terminal 1'' to move the two flip-flops 1 and 2. This causes the Q
The output signal passes through the gate circuit 4゜3.
It becomes l + 2.

This Data, 2 passes through the selected data selectors 11 and 21 as described above, and is latched into the flip-flops 1 and 2, respectively.

Finally, the latched data is serially output from terminal 2° using the scan shift clock SCK.

Second, in order to test the asynchronous clock path,
Set scan type signal STP to “1”, NS, CK1
and N5CK2, the same operation as above is performed.

〔Effect of the invention〕

As described above, according to the present invention, a data selector for switching between data and an asynchronous clock is provided on the data input side of a scan flip-flop, and a clock selector for switching between an asynchronous clock and a scan test clock is provided on the clock input side. Therefore, the scan circuit can be applied to the testing of asynchronous circuits, and its range of use has expanded significantly.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a configuration diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing an application of the present invention. 1.2...Scan flip-flop, 3.4...
Combinational gate circuit, 11.21...Data selector, 12.22...Clock selector, Data, Data2...Data from gate circuit, N5CKI, N5CK2...Asynchronous clock from gate circuit, SM ...Scan mode signal, STP...Scan type signal, 5TCK...Scan test clock, SCK...
- Shift clock for scanning, St...input data for scanning, So...output data for scanning. Figure 1 Figure 3

Claims (1)

[Claims] A plurality of flip-flops are inserted between the logic circuits under test,
In a scan circuit that passes the scan data input from the first flip-flop between the logic circuits under test by scanning each flip-flop, and tests the logic circuit under test using the output result of the final flip-flop. The data input side of the flip-flop is connected to a data selector that switches between data and the clock of the asynchronous logic circuit, and the clock input side of the flip-flop is connected with a clock that switches between the clock of the asynchronous logic circuit and the scan test clock. A scan circuit characterized in that a selector is connected.