JPH06148290A - Boundary scanning register - Google Patents

Abstract

PURPOSE:To facilitate the test of a boundary scanning register itself by performing the same independently of other circuit. CONSTITUTION:A multiplexer 30 selectively changes over the data input DI connected to a circuit to be tested, the shift input SI connected to the shift output SO of a front stage boundary scanning register subjected to cascade connection and the feedback input RI connected to data output DO. A first flip-flop 31 stores and holds the output of the multiplexer 30 and a second flip-flop 32 stores and holds the output of the first flip-flop 31 when the output of the flip-flop 31 is issued as the data output DO. The operation of the boundary scanning register can be tested by changing over the multiplexer 30 to the soft input SI or feedback input RI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first flip-flop in which a multiplexer for switching between a data input DI and a shift input SI is connected to the input, the input is stored and held, and the output is a shift output SO. And a second flip-flop that stores and holds the data output DO when the output of the first flip-flop is output as the data output DO. For the purpose of testing the circuit under test, the data input DI and the The data output DO is connected to the circuit under test, and the plurality of boundary scan registers are cascade-connected with respect to the shift input SI and the shift output SO, and the boundary scan register is operated as a shift register.
In particular, the present invention relates to a boundary scan register in which a test of the boundary scan register itself can be performed independently of other circuits such as a user circuit, and thus the test can be performed more easily.

[0002]

2. Description of the Related Art Conventionally, in order to facilitate testing of integrated circuits, a test method called a scan path method using a boundary scan register is often used. This is to use the boundary scan register for inputting or outputting a circuit under test such as a user circuit, setting the logical state of a net in the circuit, or reading the logical state.

The boundary scan register is connected to a portion for setting the logical state and reading the logical state as described above.

In addition, a large number of boundary scan registers connected in this way are set when setting their logical states.
1 by switching the multiplexer provided inside
Composed of two large shift registers. Therefore, the logical state of each boundary scan register can be set by inputting a serial data pattern to the shift register.

On the other hand, when reading out the logical state of each of the boundary scan registers, the multiplexers inside the boundary scan registers are switched to constitute one long shift register. The logical states stored in the shift register are serially shifted. As a result, the logical state of each of the boundary scan registers can be sequentially read from the outside.

FIG. 4 is a circuit diagram of a part of an integrated circuit incorporating a conventional boundary scan register.

A total of s boundary scan registers F1 to Fs are connected to the circuit under test 12 of the integrated circuit 10 shown in FIG. The circuit under test 12
When performing the test of, the desired logic state of the net of the circuit under test 12 is read as the signals W1 to Ws to the input DI of the boundary scan registers F1 to Fs. On the other hand, at the time of the test, the logical state of the desired net in the circuit under test 12 is set by outputting the outputs D0 of the boundary scan registers F1 to Fs to the corresponding nets in the circuit under test 12 from the signals Y1 to Y1. This is done by outputting as Ys. Also, the boundary scan register F1
Reading the logic state stored in ~ Fs, or
The setting of the boundary scan registers F1 to Fs is carried out by cascade connection of the respective shift input SI and shift output SO.
1 to Fs are operated by operating as a shift register. At the time of reading the logical state, the logical states stored in the boundary scan registers F1 to Fs thus operating as shift registers can be sequentially read from the output Zm by switching the multiplexer 14. Further, the data for setting each of the boundary scan registers F1 to Fs while operating as the shift register in this manner is sequentially input from the input Xn.

Here, the terminals X1 to Xn are used as ordinary input terminals. At the time of testing, the terminal Xn is also used as an input terminal for testing as described above. The terminals Z1 to Zm are used as normal output terminals. At the time of testing, the terminal Zm is also used as an output terminal for testing as described above. The terminal T is a mode switching terminal which is set to "1" in the test mode. The terminal CK is the boundary scan register F1.
It is a terminal for inputting a predetermined clock signal during the above-described test using ~ Fs. The multi-plexer 14 switches whether the output terminal Zm is used as a normal output terminal or the test output terminal.

FIG. 5 is a circuit diagram of an example of the conventional boundary scan register described above.

The boundary scan registers F1 to Fs shown in FIG. 4 have a circuit as shown in FIG. 5, for example. The boundary scan registers F1 to Fs shown in FIG. 5 include a multiplexer 30a connected to the input side and a first flip-flop 31.
And a second flip-flop 32 and a multiplexer 33 connected to the output side.

The multiplexer 30a switches between the data input DI and the shift input SI. The output of the multiplexer 30a is connected to the input D of the first flip-flop 31.

The first flip-flop 31 stores and holds the input selected by the multiplexer 30a. The output of the first flip-flop is output as the shift output SO and is also input to the input D of the second flip-flop 32.

When the output of the first flip-flop is output as the data output DO via the multiplexer 33, the second flip-flop stores and holds the output content.

The multiplexer 33 switches between the output Q of the second flip-flop 32 and the data input DI, and outputs this as the data output DO.

As shown in FIG. 4, the boundary scan registers F1 to Fs shown in FIG.
In regard to the shift input SI and the shift output SO, a plurality of the boundary scan registers are cascade-connected. Further, by operating the plurality of the boundary scan registers F1 to Fs cascade-connected in this way as a shift register as a whole, as described above, the individual boundary scan registers F1.
.About.Fs can be set, and the logical states of the respective boundary scan registers F1 to Fs can be read.

Specifically, the test of the circuit under test 12 in the integrated circuit 10 having the boundary scan registers F1 to Fs as shown in FIGS. 4 and 5 is performed as follows.

That is, first, the setting of the initial state of the circuit under test 12 is performed by the boundary scan registers F1 to F1.
In order to use Fs, the input of the mode switching terminal T is set to "1" (test mode). After that, Yi (i = 1 to s) values of a predetermined data pattern are sequentially input from the test input terminal Xn in a serial format. This is performed while sequentially inputting pulse signals to the clock signal CK of FIG.

Then, the mode switching terminal T is set to "0".
Then, the settings made in the boundary scan registers F1 to Fs are output as the signals Y1 to Ys to the circuit under test 12 by raising the clock signal CK2 in FIG. After the signals Y1 to Ys are applied and the circuit under test 12 performs a predetermined operation, the circuit under test 12
Performs a predetermined output to the output terminals Z1 to Zm, and the logic state of a predetermined net is output as corresponding signals W1 to Ws.

The signals W1 to Ws are stored in the boundary scan registers F1 to Fs in synchronization with the rising edge of the clock signal CK. The logical states stored in the boundary scan registers F1 to Fs are
By setting the mode switching terminal T to "1" again and operating the boundary scan registers F1 to Fs as shift registers, while sequentially inputting pulse signals to the clock signal CK, the test output terminal Zm
It is possible to sequentially read from.

The circuit under test 12 can be tested by repeating such a series of operations and operations.

As described above, the circuit under test 12 of the integrated circuit 10 described with reference to FIGS. 4 and 5 is described.
As described above, the test can be performed using the boundary scan registers F1 to Fs.

On the other hand, the boundary scan register F
The test of 1 to Fs itself can be diagnosed from the operating state when all of the multiplexers 30a and the first flip-flops 31 incorporated therein are operated as shift registers as described above. is there.

Further, these boundary scan registers F
1 to Fs as a test of each of the second flip-flop 32 and the multiplexer 33, the boundary scan register F1
This is performed in parallel with the test of the circuit under test 12 using .about.Fs. Alternatively, when the content of the circuit under test 12 is clear, the logic state of the data output DO of each of the boundary scan registers F1 to Fs can be changed through the circuit under test 12 to the output terminals Z1 to Z1. It is also possible to perform a test while confirming the logic state output from Zn.

[0024]

However, the test of the boundary scan registers F1 to Fs itself as described above is performed by the boundary scan registers F1 to Fs.
If the circuit contents of the circuit under test 12 tested by using Fs are not clear, there is a problem that it is difficult to do this.

Further, depending on the circuit contents of the circuit under test 12, it may take a long time to confirm the data output DO of each of the boundary scan registers F1 to Fs, or the circuit under test 12 may be checked. There was a problem that many external input settings had to be made. That is, in order to confirm each of the data outputs DO of the boundary scan registers F1 to Fs, there are cases where many test patterns must be input to the circuit under test 12.

The present invention has been made to solve the above-mentioned conventional problems, and tests the boundary scan register itself independently from other circuits such as the user circuit and the circuit under test as described above. To be able to do so,
An object of the present invention is to provide a boundary scan register that can perform the test more easily.

[0027]

The present invention is a data input D
A multiplexer for switching between I and the shift input SI is connected to the input, stores and holds the input, and outputs the data of the first flip-flop whose output is the shift output SO and the output of the first flip-flop. DO
And a second flip-flop for storing and holding the data output DO, the data input DI and the data output DO for the purpose of testing the circuit under test.
Is connected to the circuit under test, and a plurality of the boundary scan registers are cascade-connected with respect to the shift input SI and the shift output SO to operate as a shift register. The feedback input RI is switched together with the input DI and the shift input SI, and the data output DO is inputted, and the feedback inverter gate having the output connected to the feedback input RI is provided. It has achieved the task.

[0028]

There are various boundary scan registers F1 to Fs used for testing the circuit under test 12 as described with reference to FIG. The one described above with reference to FIG. 5 is one of them.

The boundary scan registers F1 to Fs described above with reference to FIG. 5 are characterized mainly by including the first flip-flop 31 and the second flip-flop 32 as described above. is there.

According to the boundary scan registers F1 to Fs, the first flip-flop 31 is provided.
At the data input DI input from the circuit under test 12 and other boundary scan registers F1 to Fs.
In addition, it is possible to store and hold the shift input SI when operated as a shift register. Therefore,
Since these data input DI and shift input SI can be held until they are read from the shift output SO, it is possible to have a margin such as a read timing from the shift output SO.

Further, the boundary scan registers F1 to Fs described above with reference to FIG. 5 store what is output as the data output DO via the multiplexer 33 in the second flip-flop 32. Is possible. Therefore, it is possible to have a margin in setting the output timing of the data output DO.

As described above, the first flip-flop 3
The boundary scan registers F1 to Fs as described above, which are provided with 1 and the second flip-flop 32, have various advantages. However, in the boundary scan registers F1 to Fs, as described above, the second flip-flop 32 and the multiplexer 3 are included.
In the test of No. 3, there was a problem that the data output DO had to be confirmed via the circuit under test 12 of FIG.

In order to solve such a problem, the present invention provides the first flip-flop and the second flip-flop as described above.
The present invention was made by finding an improved structure of a boundary scan register including a flip-flop.

FIG. 1 is a block diagram showing the gist of the present invention.

As shown in FIG. 1, the boundary scan register of the present invention includes at least a multiplexer 30, a first flip-flop 31, a second flip-flop 32, and a feedback inverter gate 35.

The multiplexer 30 is connected to the data input DI for inputting a signal from a desired node of the circuit under test 12 described above with reference to FIG. The shift input SI and the feedback input RI are switched.

The data output DO is input to the input of the feedback inverter gate 35. or,
The output of the feedback inverter gate 35 is connected to the feedback input RI of the multiplexer 30.
Therefore, the logic state of the data output DO from the second flip-flop 32 can be stored and held in the first flip-flop 31 via the multiplexer 30. The logic state stored and held in the first flip-flop 31 can be read from the shift output SO. Furthermore, the logic state read from the shift output SO can be confirmed from the outside via the next-stage boundary scan register or the next-stage boundary scan register which are cascade-connected as described above. It is possible.

Therefore, it is possible to read the operating state of the second flip-flop 32 from the shift output SO through the multiplexer 30 and the first flip-flop 31, which has been difficult to confirm the operating state. It will be possible. Further, as described above, it is possible to sequentially shift in the other boundary scan registers cascade-connected to confirm the operation state thereof from the outside.

Therefore, according to the present invention, it is possible to test the boundary scan register itself without passing through the circuit under test 12 in FIG. That is, the second of the boundary scan register
All parts including the flip-flop 32 can be self-diagnosed without depending on the circuit under test 12 or the like. Therefore, it goes without saying that the test pattern input to the circuit under test 12 is not required during the test of the boundary scan register itself.

The first flip-flop 31 is
The output of the multiplexer 30 is input. The first flip-flop 31 retains its logical state when the output of the multiplexer 30 is output as the shift output SO or when it is output as the data output DO via the second flip-flop 32 or the like. be able to. The first flip-flop 31 is not limited to a single flip-flop. A plurality of flip-flops may be used or a multiplexer or the like may be provided.

When the output of the first flip-flop 31 is output as the data output DO, the second flip-flop 32 stores and holds it. The second flip-flop 32 is not limited to one including only a single flip-flop. A plurality of flip-flops may be used or a multiplexer or the like may be provided. The first flip-flop 31 and the second flip-flop 32 are substantially the same as those described above with reference to FIG.

In the present invention, the multiplexer 30 is used.
Is not specifically limited. For example, the multiplexer 30 may be configured to selectively switch three inputs by using a total of two multiplexers for selectively switching two inputs as in the embodiment described later. Further, the multiplexer 30 may selectively switch three or more inputs.

[0043]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a circuit diagram of a part of an integrated circuit using the boundary scan register of the embodiment to which the present invention is applied.

In FIG. 2, among the integrated circuits to which the present invention is applied, in particular, the boundary scan registers F1 to Fs to which the present invention is applied are shown in a s-cascade-connected portion. In FIG. 2, these boundary scan registers F1 to Fs are the same as those in FIG.
Corresponding to the same number. The signals W1 to Ws and Y1 to Ys of FIG. 2 are also the same as those of the same symbols in FIG. 4 and are connected to the circuit under test 12.

The boundary scan registers F1 to Fs shown in FIG. 2 have the same data input DI and data output D as those shown in FIG. 4 and FIG.
O, shift input SI, shift output SO, clock signal C
K and a mode switching terminal T are provided. Further, in the boundary scan registers F1 to Fs to which the present invention shown in FIG. 2 is applied, the second mode switching terminal T2 is used.
It also has

FIG. 3 is a circuit diagram of the boundary scan register of the above embodiment.

One of the boundary scan registers F1 to Fs shown in FIG. 3, to which the present invention is applied, Fi.
Is different from the conventional boundary scan register shown in FIG. 5 in the configuration of the multiplexer at its input portion. That is, the conventional boundary scan register uses only one multiplexer 30a as compared with the boundary scan register Fi of this embodiment.
Comprises a multiplexer 30b and another multiplexer 30c. Each of these multiplexers 30b and 30c selectively switches two inputs,
It is what is output.

First, when the input of the mode switching terminal T is set to "1" (test mode), the multiplexer 30b outputs the output of the other multiplexer 30c to the input D of the first flip-flop 31. Is output. Also, the multiplexer 30b outputs the data input DI to the input D of the first flip-flop 31 when the input of the mode switching terminal T is set to "0" (normal operation mode). The multiplexer 30b
Corresponds to the multiplexer 30a in FIG.

When the input of the second mode switching terminal T2 is set to "1" (register test mode), the multiplexer 30c switches and outputs the feedback input RI to one input of the multiplexer 30b. or,
The multiplexer 30c selects and outputs the shift input SI to one input of the multiplexer 30b when the second mode switching terminal T2 is set to "0" (normal test mode).

In the structure of the present embodiment, the input of the second mode switching terminal T2 is set to "0" (normal test mode), so that the mode switching terminal T is switched while the operation shown in FIG. It can be operated in the same way as the conventional boundary scan register shown in FIG. That is, the test of the circuit under test 12 can be performed in the same manner.

On the other hand, according to the boundary scan register Fi of the present embodiment, the input of the second mode switching terminal T2 is set to "1" (register test mode) and the mode switching terminal T is set. Enter "1"
Setting the logical state of the data output DO to
It can be inverted by the feedback inverter gate 35 and written to the first flip-flop 31 via the multiplexers 30b and 30c.

Therefore, by operating the cascaded boundary scan registers F1 to Fs as shift registers, the multiplexers 30b and 30c and the first flip-flop 31 as well as the second flip-flop 32 and the multiplexer are operated. Three
3 can also be tested in the form of self-diagnosis without passing through the circuit under test 12 in FIG. Therefore, according to the self-diagnosis of the boundary scan registers F1 to Fs of this embodiment, not only the test pattern conventionally added to the circuit under test 12 of FIG. 4 becomes unnecessary but also The test time can be shortened and the test efficiency can be improved.

For example, in the boundary scan registers F1 to Fs shown in FIG. 3, first, the test mode switching terminal T is set to "1" (test mode), and the input of the second mode switching terminal T2 is set to "1". 0 ”(normal test mode). Also, the clock signal CK2
No clock pulse is input to. After that, while setting the test input DSI to "0", the clock signal CK
Input clock pulses sequentially. As a result, all the first scan lines of the boundary scan registers F1 to Fs.
“0” is set in the flip-flop 31. Further, if a change in the state of the test output DSO can be confirmed at the time when more than s clock pulses are input to the clock signal CK, the boundary scan registers F1 to F are detected.
It can be confirmed that the operation of each of the first flip-flops 31 of s is normal.

After that, when a one-pulse clock is input to the clock signal CK2, all the second flip-flops 3 of the boundary scan registers F1 to Fs are input.
"2" is also set to 2. Further, the mode switching terminal T is set to "1" and the second mode switching terminal T2 is set.
Is set to "1", and thereafter, by inputting a one-pulse clock to the clock signal CK, the logical state of the second flip-flop 32, that is, "0" is set to "1" by the feedback inverter gate 35. It can be inverted and stored in the first flip-flop 31.

If the second mode switching terminal T2 is set to "0" after the inverted logical state of the second flip-flop 32, that is, "1" is stored in this way, the clock is changed. As the clock pulse is sequentially input to the signal CK, the one stored in the first flip-flop 31 can be sequentially read.

In this way, all the first flip-flops 31 of the boundary scan registers F1 to Fs.
After confirming that "0" or "1", which is the inverted value of "0", is stored in the second flip-flop 32, it is confirmed that all the first flip-flops 31 and To 2 flip-flops 32,
This time, it is possible to confirm by writing "1" or "0" which is the inverted value of "1" or by sequentially shifting the written one. That is, the written “1” and the “1” are written in the feedback inverter gate 35.
Then, it is possible to confirm "0" which is inverted to "0" and written in the first flip-flop 31 by sequentially shifting similarly.

In this way, by confirming the logic state of "0" or "1" stored in all the first flip-flops 31 and all the second flip-flops 32,
It is possible to self-diagnose the operation of all the boundary scan registers F1 to Fs.

[0059]

As described above, according to the present invention, the test of the boundary scan register itself can be performed independently from other circuits such as a circuit under test such as a user circuit, and thus the test can be performed more efficiently. An excellent effect that it can be easily performed can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the gist of the present invention.

FIG. 2 is a circuit diagram of a part of an integrated circuit using the boundary scan register of the embodiment to which the present invention is applied.

FIG. 3 is a circuit diagram of the boundary scan register of the embodiment.

FIG. 4 is a circuit diagram of an integrated circuit using a conventional boundary scan register.

FIG. 5 is a circuit diagram of the conventional boundary scan register.

[Explanation of symbols]

 10 ... Integrated circuit 12 ... Circuit under test 30 ... 3-input multiplexer 30a-30c ... 2-input multiplexer 31 ... First flip-flop 32 ... Second flip-flop 35 ... Feedback inverter gate DI ... Data input DO ... Data output SI ... Shift input SO ... Shift output RI ... Feedback input F1 to Fs ... Boundary scan register T ... Mode switching terminal T2 ... Second mode switching terminal

Claims (1)

[Claims] 1. A first flip-flop having a multiplexer for switching between a data input DI and a shift input SI, which is connected to the input, stores and holds the input, and whose output is a shift output SO, and the first flip-flop. A second flip-flop for storing and holding the data output DO when outputting the output of the flip-flop as the data output DO, and for the purpose of testing the circuit under test, the data input DI and the data output DO are The shift input SI and the shift output SO are connected to the test circuit.
With regard to and, in the boundary scan register in which a plurality of the boundary scan registers are cascade-connected to operate as a shift register, the multiplexer switches the feedback input RI together with the data input DI and the shift input SI, A boundary scan register having a feedback inverter gate to which a data output DO is input and whose output is connected to the feedback input RI.