JPH0566244A - Scan path apparatus and semiconductor integrated circuit device containing the same - Google Patents

Abstract

PURPOSE:To obtain a scan path apparatus which achieve a testing of an RAM built into a semiconductor integrated circuit device in a short time. CONSTITUTION:A group 10 of scan registers for addresses, groups 20 and 30 of scan registers for data and a selector 50 are connected in series between a serial input terminal SIB and a serial output terminal SOB to form a scan path with a bypassing function. A shift clock SCK applied to the group 10 of scan registers for addresses is separated from a shift clock applied to the groups 20 and 30 of scan registers for data to control the groups 10, 20 and 30 of scan registers so that the groups 20 and 30 of scan registers for data stop a shifting action while the group 10 of scan registers for addresses performs a shifting operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanpath device and a semiconductor integrated circuit device including the same, and more particularly to a testability design method.

[0002]

2. Description of the Related Art A scan path is a RAM (Random).
It is used as a test auxiliary circuit (or a test circuit) for testing a semiconductor integrated circuit device such as an access memory. A basic scan path will be described as a first conventional technology, a scan path with a bypass function will be described as a second conventional technology, and a scan path using a full cycle sequence for address setting will be described as a third conventional technology.

(1) First Prior Art (a) Basic Scan Path Structure FIG. 47 is a block diagram showing the structure of a test auxiliary circuit (scan path) for a RAM.

A plurality of address scan registers (hereinafter referred to as AD scan registers) are provided around the RAM 2.
10a, a plurality of data input scan registers (hereinafter,
A DI scan register) 20a and a plurality of data output scan registers (hereinafter, referred to as DO scan register) 30a are arranged. The RAM 2 and the scan registers 10a, 20a, 30a are formed on the same semiconductor chip together with other logic circuits (not shown). These scan registers 10a, 20
a and 30a connect the other logic circuit on the semiconductor chip and the RAM2 during the normal operation, and when the RAM2 is tested, the other logic circuit on the semiconductor chip and the RAM2.
And are separated from each other.

Scan registers 10a, 20a, 30a
Is connected in series between the serial input terminal SIC and the serial output terminal SOC, and constitutes a scan path (one type of shift register). At the time of testing the RAM2, test data such as address signals and data are transferred to the address input terminals A0 to Am-1 and the data input terminals DI1 to DIn of the RAM2 by the shift function of the scan path.
Via RAM to RAM2. The test result of the RAM2 is taken into the DO scan register 30a of the scan path via the data output terminals DO1 to DOn of the RAM2.

(B) AD Scan Register FIG. 48 shows a circuit configuration of the AD scan register 10a. The AD scan register 10a is an N channel MOS
Transistors N51-N53 and inverters G51-
Including G54. The inverters G51 and G52 form a ratio type latch circuit, and the inverters G53 and G54 also form a ratio type latch circuit. Inverters G52, G54
Have a driving capability smaller than that of the inverters G51 and G53, respectively.

The AD scan register 10a has a serial input terminal SI, a serial output terminal SO, a parallel input terminal PI1 and a parallel output terminal PO1. Further, the AD scan register 10a receives a parallel clock terminal pck1 that receives the parallel clock PCK1, a serial clock terminal sck1a that receives the first serial shift clock SCK1A for address, and a serial clock terminal sck2a that receives the second serial shift clock SCK2A for address. Have.

During normal operation of the RAM 2, the potential of the serial clock terminal sck1a is set to "L" and the potential of the parallel clock terminal pck1 is set to "H".
As a result, the address signal is transmitted from the parallel input terminal PI1 to the parallel output terminal PO1. At this time, the potential of the serial clock terminal sck2a may be set to either "H" or "L".

At the time of testing the RAM2, the potential of the parallel clock terminal pck1 is set to "L". As a result, the RAM 2 is separated from other logic circuits. Also,
First-phase and second-phase clocks SCK1A, SCK provided to the serial clock terminals sck1a, sck2a
The shift operation is performed by 2A. Thereby, AD
A test address is set in the scan register 10a.

(C) DI Scan Register FIG. 49 shows the circuit configuration of the DI scan register 20a. The DI scan register 20a has the same configuration as the AD scan register 10a in FIG. 48, and the same or corresponding parts are designated by the same reference numerals. DI scan register 2
0a has a serial clock terminal sck1 that receives the first serial shift clock SCK1 and a serial clock terminal sck2 that receives the second serial shift clock SCK2.

During normal operation of the RAM 2, the potential of the serial clock terminal sck1 is set to "L" and the potential of the parallel clock terminal pck1 is set to "H". Thereby, the data is transmitted from the parallel input terminal PI1 to the parallel output terminal PO1. At this time, the potential of the serial clock terminal sck2 may be set to either "H" or "L".

At the time of testing the RAM2, the potential of the parallel clock terminal pck1 is set to "L". As a result, the RAM 2 is separated from other logic circuits. Further, the first-phase and second-phase shift clocks SCK1A, which are given to the serial clock terminals sck1, sck2,
The shift operation is performed by SCK2A. As a result, the test input data is set in the DI scan register 20a.

(D) DO Scan Register FIG. 50 shows the circuit configuration of the DO scan register 30a. In the DO scan register 30a, the same or corresponding parts as those of the AD scan register 10a and the DI scan register 20a are designated by the same reference numerals. DO scan register 30a includes N-channel MOS transistors N61 to N64, inverters G61 to G64, an exclusive NOR circuit G65 and a NOR circuit G66. Further, the DO scan register 30a has an inverted test clock terminal / t for receiving the inverted test clock / TCK.
have ck.

During normal operation of the RAM 2, the potential of the serial clock terminal sck1 is set to "L", the parallel clock terminal pck1 and the serial clock terminal sc
The potential of k2 is set to "H". As a result, the output data of the RAM 2 is transmitted from the parallel input terminal PI to the parallel output terminal PO. At this time, the potential of the inverted test clock terminal / tck may be set to either "H" or "L".

At the time of testing the RAM2, the potential of the parallel clock terminal pck1 is set to "L" and the potential of the inverted test clock terminal / tck is set to "H". As a result, the RAM 2 is separated from other logic circuits. Further, the first-phase and second-phase shift clocks SCK supplied to the serial clock terminals sck1 and sck2
The shift operation is performed by 1 and SCK2. Thereby, the test result is read.

(E) Scan Path Operation FIG. 51 is a timing chart showing the shift operation of the scan path of FIG. Each scan register 10a, 20
a, 30a serial clock terminals sck1, sck1
The first-phase clock is applied to a, and the second-phase clock is applied to the serial clock terminals sck2 and sck2a.

Serial input terminal S of each scan register
The data of I is taken into the node A in the scan register by the clock of the first phase. The data at node A is inverted and transferred to node B by the second clock. The data of the node B is inverted and the serial output terminal S
Given to O.

As a result, a 1-bit shift operation is performed from serial input terminal SI to serial output terminal SO. In this way, the shift operation is performed by the two-phase clock, and the test data is set and the test result is read.

FIG. 52 is a timing chart showing the operation at the time of testing the scan path of FIG. Serial clock terminals sck1 and sc of the scan registers 20a and 30a
The serial shift clocks SCK1 and SCK2 are given to k2, and the other serial shift clocks SCK1A and SCK2A are given to the serial clock terminals sck1a and sck2a of the AD scan register 10a. As a result, the test address is updated.

A read expected value is set to the parallel output terminal PO of the DO scan register 30a. The exclusive NOR circuit G65 compares the data read from the RAM 2 to the parallel input terminal PI with the read expected value. In addition, every time data is read, the inverted test clock / Tck is applied to the inverted test clock / Tck.
CK is given. Therefore, when fail data (wrong data) is read, clock PCK2 obtained by inverting the inverted test clock / tck is generated at the output node of NOR circuit G66. As a result, the data of the parallel input terminal PI is taken into the node A (PO2).

The same data as the data of the parallel output terminal PO is previously set in the node PO2 by the shift operation. Therefore, when the fail data is read, the data at node PO2 is inverted.

After the above operation is performed for a plurality of addresses, the shift operation shown in FIG. 51 is performed again to read the test result from serial output terminal SO. In this way, it can be known whether or not the data different from the expected read value is given to the parallel input terminal PI based on whether or not the data held by the latch circuit is inverted. (2) Second Prior Art FIG. 53 is a block diagram showing a configuration of a semiconductor integrated circuit device including a scan path with a bypass function.

A plurality of circuit blocks 2a are provided on the semiconductor chip 1a. Each circuit block 2a is, for example, R
It includes an AM, a ROM (Read Only Memory) or a multiplier. A test circuit 3a is provided around each circuit block 2a. The test circuit 3a includes a plurality of scan registers 31 and a selector 32 connected in series.
including.

In response to the mode control signal MD, the selector 32 selectively outputs either the input to the scan register 31 at the first stage or the output from the scan register 31 at the final stage. When the selector 32 is set to the “1” side, the selector 32 causes the first stage scan register 3
Select the input to 1. This is called a bypass state. When the selector 32 is set to the “0” side, the selector 32 selects the output of the scan register 31 at the final stage. This is called a non-bypass state.

A plurality of test circuits 3a corresponding to a plurality of circuit blocks 2a are connected in series between the serial input terminal SIC and the serial output terminal SOC, and the semiconductor chip 1
Configure a scan path on a.

Normally, the selector 32 corresponding to the circuit block 2a which is not the test target is set to the bypass state, and the selector 32 corresponding to the circuit block 2a which is the test target is set to the non-bypass state. ..
As a result, the test data passes only the scan register 31 corresponding to the circuit block 2a that is the test target. Therefore, as compared with the case where the test data passes through all the scan registers 31, the number of shift operations is reduced and the test time is shortened.

FIG. 54 is a block diagram showing an example of the configuration of the test circuit when the circuit block is RAM2.

The test circuit 3a includes an address scan register group (hereinafter referred to as an AD scan register group) 10,
It includes a data input scan register group (hereinafter referred to as DI scan register group) 20, a data output scan register group (hereinafter referred to as DO scan register group) 30, and a selector 50. AD scan register group 10, DI
Scan register group 20, DO scan register group 30
The selector 50 is connected in series between the serial input terminal SI and the serial output terminal SO to form a scan path. The common shift clock SCK is applied to the AD scan register group 10, the DI scan register group 20, and the DO scan register group 30, and the selector 5
A mode control signal MD is applied to 0. The selector 50 of FIG. 54 corresponds to the selector 32 of FIG.

The shift clock SCK is a one-phase shift clock or a two-phase shift clock.

When one RAM 2 shown in FIG. 54 is tested, the test circuits corresponding to the other circuit blocks are set to the bypass state. In this state, the serial input terminal SI and the serial output terminal SO of the test circuit 3a corresponding to the RAM 2 are connected to the serial input terminal SIC and the serial output terminal SOC of the semiconductor chip 1a shown in FIG. 53, respectively. Will be equivalent. Therefore, regarding the test time, the shift operation of the test circuit 3a in FIG. 54 may be taken into consideration, and it is not necessary to consider the shift operation of the test circuits of the other circuit blocks.

However, the circuit block to be tested is tested by the shift operation of the scan path. Therefore, there is a problem that the test time increases in proportion to the number of shifts. This problem,
It is also present when the circuit block is RAM. Next, in order to explain the problem of increase in test time, the march test, which is a general test algorithm for RAM, will be described as an example. (3) General March Test The processing procedure of the general march test test algorithm is shown below.

(Procedure 1) "0" is written to all addresses.

(Procedure 2) "0" is added to each address while sequentially increasing the addresses from 0 to the final address.
After reading, "1" is written.

(Procedure 3) "1" is set for each address while sequentially decreasing the address from the last address to the 0th address.
After reading, "0" is written.

(Procedure 4) "1" is written to all addresses.

(Procedure 5) "1" is added to each address while sequentially increasing the addresses from 0 to the final address.
After reading, "0" is written.

(Procedure 6) "0" is set for each address while sequentially decreasing the address from the last address to the 0th address.
After reading, "1" is written.

For example, consider the case of testing the RAM 2 shown in FIG. The address signal A is sent to the RAM2.
(0) to A (n-1), chip enable signal CE, write enable signal WE, and data DI (0) to DI
(M-1) is input, and data DO (0) is output from RAM2.
~ DO (m-1) is output.

In steps 1 and 4, the write operation shown in FIG. 56 is performed. Further, in steps 2, 3, 5 and 6, the read / write operation shown in FIG. 57 is performed. Figure 5
In the write operation shown in 6, the data DI (i) is written in response to the low-active write enable WE. In the read / write operation shown in FIG. 57, the data DO (i) read in response to the low active chip enable signal CE is compared with predetermined expected value data by the external tester at the tester strobe timing, and then the low Data DI (i) is written in response to the active write enable signal WE. Where i is 0
It represents m-1. In the read / write operation shown in FIG. 57, the read operation and the write operation are performed in the same test cycle.

For example, R of 1024 words × 8 bits
Consider AM. In steps 1 and 4, the write operation of FIG. 56 is repeated 1024 times, and steps 2, 3, 5, 6
Then, the read / write operation of FIG.
Repeated times. Therefore, the march test is 61 in total.
It will be realized in 44 test cycles.

A march test for a 2 ⁿ word RAM is generally implemented in 6 × 2 ⁿ test cycles. This trial calculation is applicable when various signals can be directly controlled and observed from the outside like the RAM 2 shown in FIG.

When this march test is performed using the scan path with the bypass function shown in FIGS. 53 and 54, the test of each RAM is performed by the normal scan test. In the scan test, the read operation and the write operation of the RAM 2 can be performed within the test cycle of the shift operation. Therefore, in the following description, only the number of test cycles of the shift operation will be considered.

The following description will be made with reference to FIG. As described above, when the RAM 2 has a configuration of 1024 words × 8 bits, the AD scan register group 10 has 10
DI scan register group 20 includes 8 scan registers, and DO scan register group 30 includes 8 scan registers.

In steps 1 and 4, it is necessary to set the address signal and the write data for each address by the shift operation. Therefore, the DI scan register group 20
It is necessary to perform eight shift operations in order to set the write data in, and ten shift operations in order to set the address signal in the AD scan register group 10. In the following description, it is assumed that one shift operation is also performed in one test cycle. In procedures 1 and 4, this test cycle is repeated 1024 times, so that (10 + 8) × 1024 = 18432 test cycles are required respectively.

Further, in steps 2, 3, 5 and 6, it is necessary to set the write data and the address signal for each address by the shift operation and fetch the read data by the shift operation. Therefore, eight shift operations are required to set the write data in the DI scan register group 20, ten shift operations are required to set the address signal in the AD scan register group 10, and DO is further required. Eight shift operations are required to retrieve the read data in the scan register group 30. In steps 2, 3, 5 and 6, this test cycle is 1024
Since it is repeated twice, (10 + 8 + 8) × 10
24 = 26624 test cycles are required.

As a result, in order to perform the march test, (18432 × 2 + 26624 × 4) = 14336
0 test cycle is required.

As described above, the test cycle required for the scan test is compared with the test cycle required for the general march test (6144 test cycle).
It is about 23 times. That is, even if the scan path with the bypass function is used, an increase in the test time (about 23 times in this example) cannot be avoided if the test of each RAM is performed by the normal scan test. (4) Third Prior Art Next, a test circuit that uses the full-cycle sequence for address setting will be described.

The full-cycle sequence is a special bit string,
By shifting this bit string into the scan path, the test address of the RAM can be set efficiently. "0000111101011001000" is an example of a fourth-order full-cycle sequence.

When this bit string is input to the 4-bit shift register, the data held in the shift register changes every shift operation. As a result, all possible 16 states can be set, albeit in a random order. Assuming that the value held by the shift register is the RAM test address, although in random order,
As shown in FIG. 58, all addresses from 0 to 15 can be set.

The full-cycle sequence shown in FIG. 58 is "000011."
1101011001000 ", and it is assumed that one bit is shifted into the four-bit shift register in this order. Therefore, when the first" 0000 "is shifted in, the address becomes the address 0. , And the remaining 111101011001000 "are sequentially shifted in, the address changes to 8th address, 12th address, 14th address, ... The test cycle required at this time is (4-1) +2 ⁴ = 19 test cycles.

Generally, an nth-order full-cycle sequence is used for testing a RAM having n address lines. In this case, to set all test addresses, (n-1) +2 ⁿ
A test cycle is needed. In the first (n-1) shift operation, the test cannot be started because the address is uncertain. Since the address is fixed in the subsequent 2 ⁿ shift operations, the RAM read operation and write operation can be performed. (5) Random March Test The procedure of the random march test is shown below as an example of a test algorithm that uses the entire periodic sequence for address setting.

(Procedure 1) Addresses are set while shifting in the entire period series, and "0" is written for all addresses.

(Procedure 2) Addresses are set while shifting in the entire period series, and "1" is written after reading "0" for each address.

(Procedure 3) Addresses are set while shifting in the entire period series, and "0" is written after reading "1" for each address.

(Procedure 4) Addresses are set while shifting in the entire period series, and "1" is written for all addresses.

(Procedure 5) Addresses are set while shifting in the entire period series, and "0" is written after reading "1" for each address.

(Procedure 6) Addresses are set while shifting in the entire cycle sequence, and "1" is written after "0" is read for each address.

Note that different full cycle sequences may be used for each of steps 1 to 6.

A test circuit considering this random march test is shown in FIGS. 59 and 60. In the example of FIG. 59,
Corresponding to one RAM 2, one AD scan register group 10, one DI scan register group 20, one DO scan register group 30, and one comparison circuit 80.
Is provided. In the example of FIG. 60, a plurality of AD scan register groups 10 and a plurality of DIs are provided corresponding to a plurality of RAMs 2.
A scan register group 20, a plurality of DO scan register groups 30, and a plurality of comparison circuits 80 are provided.

Here, the test cycle required for the random march test will be considered with reference to FIG.

AD scan register group 10
If the shift-in is performed, the address signal can be updated by one shift operation. Therefore, it is not necessary to shift in all the bits of the address signal for each address as in the general march test.

Further, since the write data and the read data do not change in each procedure, it is necessary to divide the scan path so that the write data does not change due to the shift operation of the entire period series. Therefore, as shown in FIG. 59, the AD scan register group 10 is connected between the serial input terminal SI1 and the serial output terminal SO1, and the DI scan register group 20 and the DI scan register group 20 are connected between the serial input terminal SI2 and the serial output terminal SO2. DO scan register group 3
0s are connected in series. The AD scan register group 10 is supplied with the shift clock SCKA, and the DI scan register group 20 and the DO scan register group 30 are supplied with the shift clock SCKD.

Further, the comparison circuit 80 is provided so that the read out data need not be shifted out. The comparison circuit 80 compares the data (read expected value data) held by the DO scan register group 30 with the read data from the RAM 2 and outputs a PASS / FAIL signal indicating a match / mismatch. Therefore, the shift operation of the DO scan register group 30 is not necessary unless the read expected value data changes.

In the random march test, the write data and the read expected value data do not change while the address is updated in each procedure. Therefore, D
The number of shift operations of the I scan register group 20 and the DO scan register group 30 is the same as the AD scan register group 1
It is very small compared to the number of 0 shift operations.

For example, R of 1024 words × 8 bits
Estimate the test cycle required to test AM. In this case, since the number of words is 2 ¹⁰ = 1024, n = 10
Becomes Therefore, a tenth-order full-cycle sequence is used.

In each procedure, 9 extra shift operations are required before the address is determined. After that, the address can be updated and the test can be performed by one shift operation.

Since the shift operation can be performed in the same test cycle as the read operation or the read / write operation, in steps 1 and 4, the shift operation and the write operation are performed in the same test cycle, and steps 2, 3, 5 are performed. , 6 will be described below assuming that the shift operation and the read / write operation are performed in the same test cycle.

In steps 1 and 4, it takes 9 steps to determine the address.
One shift operation is required, and 1024 test cycles are required. Further, eight shift operations are required to set the write data in the DI scan register group 20, but these shift operations can be performed simultaneously with the nine shift operations until the address is fixed. Therefore, in steps 1 and 4, respectively, 9 + 102
4 = 1033 test cycles are required.

Further, in steps 2, 3, 5, and 6, it is necessary to perform the shift operation 9 times until the address is fixed.
024 test cycles are required. Further, eight shift operations are required to set the read expected value data in the DO scan register group 30, and eight shift operations are required to set the write data in the DI scan register group 20. During the shift operation for setting the read expected value data and the write data, the shift operation can be performed 9 times until the address is determined. Therefore, in steps 2, 3, 5 and 6, each 16 + 10
24 = 1040 test cycles are required.

As a result, in the random march test,
(1033 x 2 + 1040 x 4) = 6226 test cycles are required.

As described above, the test cycle required for the random march test is compared with the test cycle required for the general march test (6144 test cycle).
Only increase by 1.3%. Therefore, it is effective in suppressing an increase in test time. (6) Citation of known document An example of a conventional scan path is disclosed in Japanese Patent Laid-Open No. 63-22239.
No. 9 and corresponding US Pat. No. 4,926,424
No.

FIG. 59 in which the entire cycle sequence is used for address setting
60 and the test circuit of FIG. Maeno et
al. , "TESTING OF EMBEDDED
RAM USING EXHAUSTIVE RAND
OM SEQUENCES ", 1987 Intern
national Test ConferencePa
per4.2, pp. 105-110.

[0073]

In the test auxiliary circuit (scan path) shown in FIG. 47, it is necessary to connect the DI scan register 20a and the DO scan register 30a to each data input terminal and each data output terminal of the RAM2. is there. Therefore, the scale of the test auxiliary circuit becomes large.

The two latch circuits forming each DI scan register 20a and each DO scan register 30a are used only during a test and only pass data during a normal operation. Therefore, there is a problem that the chip area of the semiconductor integrated circuit device increases due to an unnecessary test auxiliary circuit during normal operation and the manufacturing cost increases.

In the test circuit shown in FIGS. 59 and 60, the scan paths are separated into two systems, that is, an address scan path and a data scan path. Therefore, each test circuit requires two serial input / output terminals. As a result, the wiring of the serial shift path connected to these terminals becomes complicated.

An object of the present invention is to reduce the scale of the scanpath device (test auxiliary circuit).

Another object of the present invention is to reduce the chip area and manufacturing cost of a semiconductor integrated circuit device including a scan path device.

Still another object of the present invention is to simplify the wiring of the scan path device and to improve the efficiency of the test.

Still another object of the present invention is to enable mode setting in a scanpath device with a bypass function without complicating the circuit structure and to improve the efficiency of the test.

Still another object of the present invention is to shorten the test time without complicating the wiring in the semiconductor integrated circuit device including the storage means.

[0081]

A scanpath device according to a first invention includes a plurality of scan registers connected in series. Each of the plurality of scan registers includes a serial input terminal, a serial output terminal, first and second parallel input terminals, first and second parallel output terminals, and a first parallel output terminal.
And second holding means, first, second, third and fourth transmitting means, comparing means and activating means.

The first and second holding means hold and output the given data. The first transmission means transmits the data of the first parallel input terminal to the first holding means. The second transfer means transfers the data of the serial input terminal to one of the first and second holding means. The third transfer means transfers the data of the second parallel input terminal to the second holding means. The fourth transmission means transmits the data output from the one of the first and second holding means to the other of the first and second holding means.

The first parallel output terminal receives the data output from the first holding means. The second parallel output terminal receives the data output from the second holding unit. The serial output terminal receives the data output from the other of the first and second holding means.

The comparing means compares the data at the second parallel input terminal with the data output from the first holding means. The activation means activates or deactivates the third transmission means according to the comparison result of the comparison means. The serial input terminal of each scan register is connected to the serial output terminal of the previous scan register.

The scanpath device according to the second invention includes a plurality of scan registers connected in series. Each of the plurality of scan registers includes a serial input terminal, a serial output terminal, first and second parallel input terminals, and a first parallel input terminal.
And a second parallel output terminal, first and second holding means, first, second, third and fourth transmitting means, comparing means, first and second activating means, and forcing means. ..

The first and second holding means hold and output the given data. The first transmission means transmits the data of the first parallel input terminal to the first holding means. The second transfer means transfers the data of the serial input terminal to one of the first and second holding means. The third transfer means transfers the data of the second parallel input terminal to the second holding means. The fourth transmission means transmits the data output from the one of the first and second holding means to the other of the first and second holding means.

The first parallel output terminal receives the data output from the first holding means. The second parallel output terminal receives the data output from the second holding unit. The serial output terminal receives the data output from the other of the first and second holding means.

The comparing means compares the data at the second parallel input terminal with the data output from the first holding means. The first activation means activates or deactivates the first transmission means. The second activation means activates or deactivates the third transmission means according to the comparison result of the comparison means. The forcing means is responsive to the predetermined signal to activate or deactivate the third transmitting means in synchronization with the first activating means regardless of the comparison result of the comparing means. Force means. The serial input terminal of each scan register is connected to the serial output terminal of the previous scan register. A scan path device according to a third aspect of the present invention includes a first scan register group including a plurality of scan registers connected in series, and a plurality of scan registers connected in series to an output of the first scan register group. A second scan register group is provided. The scan path device further includes means for controlling the first and second scan register groups so that the second scan register group stops the shift operation and the first scan register group performs the shift operation.

A scanpath device according to a fourth aspect of the present invention includes an input terminal for receiving serial data, a first scan register group including a plurality of scan registers serially connected to the input terminal, and a first scan register group. It includes a second scan register group including a plurality of scan registers serially connected to the output, an output terminal, a selection unit, and a first control unit.

The selection means includes the data of the input terminal and the second
One of the data output from the scan register group is selected, and the selected data is given to the output terminal. The first control means sets the first and second scan register groups so that the second scan register group stops the shift operation and the first scan register group performs the shift operation when the data of the input terminal is selected by the selection means. The second shift register group is controlled.

The scanpath apparatus according to the fifth aspect of the present invention further comprises second control means. The second control means is the first
And receiving data from any one of the scan registers included in the second scan register group, and controlling the selecting means in response to the data.

A semiconductor integrated circuit device according to the sixth invention is
Storage means and scan path means are provided. The scan path means includes an input terminal for receiving serial data, a first scan register group, a second scan register group, a selecting means and a first control means.

The first scan register group includes a plurality of scan registers connected in series, and the data serially applied from the input terminal is applied in parallel to the storage means as an address signal. The second scan register group includes a plurality of scan registers connected in series, and the data serially given from the first scan register group is given to the storage means in parallel or the data output from the storage means is given in parallel. To receive.

The selection means includes the data of the input terminal and the second
One of the data output from the scan register group is selected, and the selected data is output. First
The control means of the first and second scan register groups stops the shift operation of the second scan register group and the first scan register group performs the shift operation when the data of the input terminal is selected by the selection means. Control the scan register group of.

A semiconductor integrated circuit device according to the seventh invention is
It further comprises a second control means. The second control means receives the data given from any one of the scan registers included in the first and second scan register groups, and controls the selection means in response to the data.

A semiconductor integrated circuit device according to the eighth invention is
Further provided is a holding means and a second control means. The holding unit is provided in series with the first and second scan register groups and holds the mode setting data. The second control means controls the selection means in response to the mode setting data held in the holding means.

[0097]

In the scan path device according to the first and second aspects of the present invention, the data of the serial input terminal is given to one of the first and second holding means by the second transmitting means during the test, The data output from one of the second holding means is given to the other of the first and second holding means and output from the serial output terminal. In this way, the shift operation is performed.

By this shift operation, the expected value data is set in the first and second holding means, and the read data is set to the second data.
It is given to the parallel input terminal of. The read data from the second parallel input terminal is compared with the expected value data held in the first holding means by the comparing means. The third transmission means is activated or deactivated according to the comparison result.
When the third transfer means is activated, the read data from the second parallel input terminal is given to the second holding means. If the third transmission means is not activated, the expected value data of the second holding means does not change.

In the scanpath device according to the first aspect of the present invention, during the normal operation, the data of the first parallel input terminal is given to the first holding means by the first transmission means, and the data is supplied from the first parallel output terminal. Is output. Further, the data of the second parallel input terminal is given to the second holding means by the third transmitting means, and is output from the second parallel output terminal.

In the scanpath device according to the second aspect of the present invention, during the normal operation, the first activating means activates or deactivates the first transmitting means, and the second activating means activates the third transmitting means. The transmission means is activated or deactivated. As a result, the first and second holding means operate as a latch circuit.

As described above, in the scanpath device according to the first and second inventions, one of the first and second holding means included in each scan register is used for inputting parallel data, The other of them is used for outputting parallel data. Therefore, it becomes possible to input and output data with one scan register, and the size of the scan path device is reduced.

In particular, in the scanpath device according to the second invention, the first and second holding means included in each scan register can be used as a latch circuit during normal operation. Therefore, it is no longer necessary to provide a latch circuit, which was conventionally required during normal operation.

In the scan path device included in the scan path device according to the third, fourth and fifth inventions and the semiconductor integrated circuit device according to the sixth, seventh and eighth inventions, the second scan register group is provided. It is possible to cause the first scan register group to perform the shift operation in a state where the shift operation is suppressed.

As a result, the data can be serially input to the first scan register group without changing the data of the second scan register group. Therefore, the efficiency of the test can be improved. Also, the first and second
Since the scan register group of 1 constitutes one path, the wiring of the serial shift path is simplified.

In the scanpath device according to the fourth and fifth inventions, the data in the input terminal is serially input to the first scan register group and the data is serially output from the output terminal. Can be set to a non-bypass state in which data is output to the first scan register group serially and data output from the second scan register group is output serially from the output terminal. When the scan path device is set to the bypass state, the data can be serially input to the first scan register group without changing the data of the second scan register group. Therefore, the efficiency of the test can be improved.

In the scanpath device according to the fifth aspect of the present invention, since the selecting means is controlled based on the data input to the first or second scan register group, the wiring for the control signal is simplified. It

In the semiconductor integrated circuit device according to the sixth, seventh and eighth inventions, the scan path means can be selectively set to the bypass state and the non-bypass state.
When the scan path means is set to the bypass state, the second
Address data can be serially input to the first scan register group without changing the data held in the first scan register group. As a result, the address signal can be easily updated, and the test time can be shortened.

In the semiconductor integrated circuit device according to the seventh invention, the selecting means is controlled based on the data input to the first and second scan register groups, so that the wiring for the control signal is simplified. To be done.

In the semiconductor integrated circuit device according to the eighth aspect of the present invention, since the selecting means is controlled based on the mode setting data held in the holding means, the wiring for the control signal can be simplified.

[0110]

【Example】

(1) Schematic Configuration and Operation FIG. 1 is a block diagram showing a schematic configuration of a test circuit included in the semiconductor integrated circuit device according to the first embodiment.
FIG. 2 is a block diagram showing the overall configuration of the semiconductor integrated circuit device.

First, reference will be made to FIG. A plurality of RAMs 2, a plurality of test circuits 3 and a logic circuit 4 corresponding to the plurality of RAMs 2 are provided on the semiconductor chip 1. Each R
AM2 is connected to the logic circuit 4 via the corresponding test circuit 3.
Connected to. The plurality of test circuits 3 are connected in series between the serial input terminal SIC and the serial output terminal SOC to form a scan path.

Each test circuit 3 has a reset signal RST, a mode setting signal MDSET, and a mode setting signal MDSET via a test bus TB.
Shift clock SCK, strobe signal STB, test mode signal TM, test chip enable signal TCE
And a test write enable signal TWE. In this embodiment, the shift clock SCK is the first phase shift clock SCK1 and the second phase shift clock SC.
It is a two-phase clock including K2. Shift clock SCK
May be a one-phase clock.

Next, referring to FIG. An AD scan register group 10, a DI scan register group 20, a DO scan register group 30, a mode setting scan register 40, and a selector 50 are connected in series between the serial input terminal SIB and the serial output terminal SOB of the test circuit 3. , Configure the scan path.

Test circuit 3 further includes a gate circuit 60 and a mode control latch 70. Shift clock SC
K is given to the AD scan register group 10 and to one input terminal of the gate circuit 60. The mode control signal MD output from the mode control latch 70 is applied to the other input terminal of the gate circuit 60. The output of the gate circuit 60 is given to the DI scan register group 20, the DO scan register group 30, and the mode setting scan register 40.

When the mode control signal MD is "1", the selector 50 is set to the bypass state. At this time, the shift clock SCK is not output from the gate circuit 60. As a result, the DI scan register group 20, the DO scan register group 30, and the mode setting register 40
Shift operation stops.

Therefore, when carrying out the random march test, the entire period series is shifted to the AD scan register group 10 while the DI scan register group 20 and the DO scan register group 30 hold write data and read expected value data. You can update the address by logging in.

On the other hand, when the mode control signal MD is "0", the selector 50 is set to the non-bypass state. At this time, the AD scan register group 10 is provided to the DI scan register group 20, the DO scan register group 30, and the mode setting register 40 via the gate circuit 60.
Similarly to the shift clock SCK is given. Therefore, the serial input terminal SIB and the serial output terminal SOB
The scan register between and operates as a normal scan path.

A mode setting signal MDST and a reset signal RST are applied to the mode control latch 70. Data is input to the mode control latch 70 from the mode setting scan register 40. Mode control latch 70
Outputs the mode control signal MD in response to the mode setting signal MDST, the reset signal RST, and the data from the mode setting scan register 40.

When the reset signal RST is applied, the mode control signal MD is set to "0". As a result, the selector 50 enters the non-bypass state. At this time, the scan register groups 10, 20, 30, and 40 are put into a shiftable state by the shift clock SCK. In this case, the scan registers 10, 20, 30, 40 of all the test circuits 3 on the semiconductor chip 1 shown in FIG. 2 are connected in series.

By the subsequent shift operation, data "1" or "0" is set in the mode setting scan register 40 in each test circuit 3. After that, when the mode setting signal MDST is applied, the data “1” or “0” held in the mode setting scan register 40 in each test circuit 3 is taken into the mode control latch 70, and the data is controlled by the mode control latch 70. It is output as the signal MD. As a result, the selector 50 in each test circuit 3 can be selectively set to the non-bypass state or the bypass state.

Although the compression method of read data is not shown in FIG. 1, a comparison circuit 80 may be provided as shown in FIGS. 59 and 60.

In the random march test, when shifting the entire period series into the test circuit 3 corresponding to the RAM 2 to be tested, the write data and the read expected value data must not change. Therefore, the test circuit 3 of the RAM 2 to be tested needs to be set to the bypass state. Further, in order to reduce the test time, it is necessary to set the test circuits 3 corresponding to other circuit blocks in the bypass state. As a result, all circuit blocks are set to the bypass state.

This state is equivalent to the case where the entire period series input from the serial input terminal SIC of the semiconductor chip 1 is commonly input to all the test circuits 3. Therefore, if the number of words is the same, it is possible to simultaneously set the entire cycle sequence as an address for a plurality of RAMs 2. This means that it is possible to simultaneously test a plurality of RAMs 2. (2) Random March Test Again, the processing procedure of the random march test using the entire periodic sequence for address setting is shown below.

(Procedure 1) Addresses are set while shifting in the entire period series, and "0" is written for all addresses.

(Procedure 2) Addresses are set while shifting in the entire period series, and "1" is written after reading "0" for each address.

(Procedure 3) Addresses are set while shifting in the entire period series, and "0" is written after reading "1" for each address.

(Procedure 4) Addresses are set while shifting in the entire period series, and "1" is written for all addresses.

(Procedure 5) Addresses are set while shifting in the entire period series, and "0" is written after reading "1" for each address.

(Procedure 6) Addresses are set while shifting in the entire period series, and "1" is written after reading "0" for each address.

Next, the estimation of the test cycle when performing the random march test using the test circuit 3 of FIG. 1 will be considered below.

Here, the RAM 2 has 1024 words × 8.
Consider the case of having a bit configuration. Number of words is 2 ¹⁰ = 1
Since it is 024, n = 10. Therefore, 10
The following full cycle sequence is used. In each procedure of the random march test, 9 extra shift operations are required before the address is determined. After that, the test can be performed by updating the address for each shift operation.

The shift operation can be performed in the same test cycle as the write operation or read / write operation of RAM 2. Therefore, it is assumed that in steps 1 and 4, the shift operation and the write operation are performed in the same test cycle, and in the other procedures, the shift operation and the read / write operation are performed in the same test cycle.

In steps 1 and 4, eight shift operations are required to set the write data in the DI scan register group 20, nine shift operations are required until the address is fixed, and further 1024 operations are required. Shift and write operations are required for each of the addresses. Therefore, in steps 1 and 4, 8 + 9 + 1024 = 10
Forty-one test cycles are required.

In steps 2, 3, 5 and 6, 8 is used to set the read expected value data in the DO scan register group 30.
The shift operation is required eight times, and the shift operation is required eight times in order to set the write data in the DI scan register group 20. Further, it is necessary to perform the shift operation 9 times until the address is determined, and further, the shift operation and the read / write operation are required for each of the 1024 addresses. Therefore, in the procedures 2, 3, 5 and 6, 16 + 9 + 1024 = 1049 test cycles are required.

As a result, the random march test
(1041 × 2 + 1049 × 4) = 6278 test cycles are required. (3) Unique effect The test cycle required for the random march test according to this example is 2.2% compared with the test cycle required for a general march test (6144 test cycle).
It only increases, and has a sufficient effect in suppressing the increase in test time.

In this embodiment, since the shift clock SCK is applied to the DI scan register group 20 and the DO scan register group 30 via the gate circuit 60, a special shift clock is provided for these scan register groups 20 and 30. No need to give. Therefore, the number of shift clock terminals does not increase and wiring congestion can be suppressed.

In this embodiment, it is not necessary to apply the independent mode control signal MD to each test circuit 3, and the common mode setting signal MDST and the common reset signal RST can be applied to all the test circuits 3. Therefore, wiring congestion can be further suppressed. (4) Detailed Configuration of Each Part (a) Test Circuit 3 The relationship between the test circuit 3 and the RAM 2 is shown in FIG. 3, and the detailed configuration of the test circuit 3 is shown in FIG.

As shown in FIG. 3, the test circuit 3 includes the address signal AX (n-) from the logic circuit 4 (see FIG. 2).
1) to AX (0), chip enable signal CEX, write enable signal WEX, and write data DIX (m
-1) to DIX (0) are given. Further, the test circuit 3 causes the logic circuit 4 to read the read data DOX (m-1).
Give ~ DOX (0). Furthermore, the test circuit 3 is
Address signals A (n-1) to A (0), chip enable signal CE, write enable signal WE, and write data DI (m-1) to DI (0) are applied to AM2. In the test circuit 3, the read data DO (m-
1) to DO (0) are given.

As shown in FIG. 4, the test circuit 3 has AD
Scan register group 100, chip enable scan register (hereinafter referred to as CE scan register) 20
0, write enable scan register (hereinafter referred to as WE scan register) 300, data input / output scan register group (hereinafter referred to as DIO scan register group)
400, dummy scan register (hereinafter referred to as DMY scan register) 500, latch circuit with reset 60
0 and multiplexer 700. Test circuit 3
Is an inverter circuit G1, G2, a two-input AND circuit G3
.About.G5 and a 3-input AND circuit G6 are further included.

The AD scan register group 100 is A in FIG.
The D scan register group 10 corresponds to the D scan register group 10, and the DIO scan register group 400 corresponds to the DI scan register group 20 and the DO scan register group 30 in FIG. The DMY scan register 500 corresponds to the mode setting scan register 40 of FIG. 1, the multiplexer 700 corresponds to the selector 50 of FIG. 1, and the reset latch circuit 600 corresponds to the mode control latch 70 of FIG.

FIG. 5 shows another example of the configuration of the test circuit 3. The test circuit 3 of FIG. 5 differs from the test circuit 3 of FIG. 4 in the following points. DMY500 is not provided,
The output of any one of the plurality of scan registers included in the AD scan register group 100 is given to the latch circuit with reset 600.

(B) AD Scan Register Group 100 FIG. 6 shows the configuration of the AD scan register group 100.
The AD scan register group 100 includes n address scan registers (hereinafter referred to as AD scan registers) 11
Including 0. These AD scan registers 110 are connected in series between the serial input terminal SIA and the serial output terminal SOA to form a short scan path (n-bit scan path). The serial output terminal SOR of each AD scan register 110 is connected to the serial input terminal SIR of the AD scan register 110 at the next stage.

During the test, AD scan register group 1
The test address of the RAM 2 is set to 00 by the shift operation.

(C) AD Scan Register 110 FIG. 7 shows the detailed structure of the AD scan register 110. The AD scan register 110 includes a latch circuit L1 and a 2-input latch circuit L2.

Latch circuit L1 operates as follows. Shift clock S given to enable terminal EN
When CK2 is enabled, it takes in data from the input terminal D, holds it, and outputs the data from the output terminal Q.

Two-input latch circuit L2 operates as follows. When the chip enable signal CEA applied to the first enable terminal EN1 is enabled, the data is taken in from the first input terminal D1, the data is held and the data is output from the output terminal Q. Also,
When the shift clock SCK1 applied to the second enable terminal EN2 is enabled, it takes in data from the second input terminal D2, holds it, and outputs the data from the output terminal Q. However, it is prohibited to simultaneously apply the signals in the enable state to the first enable terminal EN1 and the second enable terminal EN2.

Input terminal a of AD scan register 110
The address signal AX (i) is applied to xi from the logic circuit 4 (see FIG. 2). Chip enable signal CE
When A is enabled, this address signal AX
(I) is taken into the 2-input latch circuit L2, and
The address signal A (i) is output from the output terminal ai. That is, the address signal is transmitted from the input terminal axi to the output terminal ai while the chip enable signal CEA is in the enabled state. In this state, the address terminals of the logic circuit 4 and the RAM 2 are logically connected.

Conversely, when the enable signal CEA is in the disabled state, the logic circuit 4 and the RAM 2 are
The address terminals of are disconnected from each other. At this time,
If the two-phase shift clocks SCK1 and SCK2 that do not overlap are applied to the enable terminals EN2 and EN, the shift operation can be performed. First, when the first-phase shift clock SCK1 is applied to the enable terminal EN2 of the 2-input latch circuit L2, the data on the serial input terminal SIR is taken into the 2-input latch circuit L2. Since the output terminal Q of the 2-input latch circuit L2 is connected to the input terminal D of the latch circuit L1, when the second-phase shift clock SCK2 is applied to the enable EN, this data is transferred to the latch circuit L1. And is output to the serial output terminal SOR. In this way, the serial input terminal SIR
From 1 to serial output terminal SOR is performed.

(D) CE Scan Register 200 FIG. 8 shows a detailed configuration of the CE scan register 200. The CE scan register 200 includes a latch circuit L1 and a two-input latch circuit L2 similarly to the AD scan register 110, and further includes inverter circuits G11 and G12.
And a 2-input NAND circuit G13.

The shift operation of the CE scan register 200 is similar to the shift operation of the AD scan register 110. However, as the shift clock, shift clocks SCK1M and SCK2M different from the shift clock of the AD scan register 110 are used.

In the normal operation, the enable signal TCE is set to "L" and the enable signal STBM is set to "H". As a result, the enable signal CEX is output to the inverter circuit G12, the 2-input latch circuit L2 and the NAND
It is transmitted to the output terminal ce via the circuit G13. Since the enable signal CEX is inverted by the inverter circuit G12 and then inverted by the NAND circuit G13, as a result, the logic levels of the enable CE and the enable signal CEX become the same.

In the test, the enable signal STBM is set to "L" and the enable signal TCE becomes "L". Here, it is assumed that the enable signal STBM and the enable signal TCE are low active.

When the output signal of the output terminal Q of the 2-input latch circuit L2 is set to "H" by the shift operation, the enable signal CE becomes "L". Thereby,
RAM2 operates. When the output signal of the output terminal Q of the 2-input latch circuit L2 is set to "L", the enable signal TCE is not transmitted to the output terminal ce, and the enable signal CE holds "H". Therefore RAM
2 goes into a standby state.

As described above, the CE scan register 200
It is possible to control the operation of the RAM 2 by the data set in.

Therefore, as shown in FIG.
When M2 is integrated on the semiconductor chip 1,
The desired data is transferred to the CE of each test circuit 3 by the shift operation
If set in the scan register 200, the desired RAM 2
Can be selectively operated and tested.

In the CE scan register 200 of FIG.
The enable signal STBM is output from the output terminal cea as the enable signal CEA, and the AD scan register 1
Given to 10.

FIG. 9 shows another example of the configuration of the CE scan register 200. In this CE scan register 200, a 2-input AND circuit G14 is added. This allows the AD scan register 110 to be used as an address latch during normal operation.

The enable signal STBM is set to "H" in the normal operation and set to "L" in the test. Therefore, during normal operation, the enable signal CEA and the enable signal CE have the same logic level.

In normal operation, the enable signal CEX
(Low active) is transmitted to the output terminal ce and simultaneously to the output terminal cea. When the enable signal CEA becomes "L", the two-input latch circuit L2 of the AD scan register 110 shown in FIG. 7 enters the holding state (latches the address signal).

As described above, by using the CE scan register 200 shown in FIG. 9, the AD scan register 110 can be used as an address latch during normal operation.

The CE scan register 200 of FIG. 8 does not have such an address latch function. 8 and 9
The CE scan register 200 is used properly according to need.

(E) WE Scan Register 300 FIG. 10 shows a detailed structure of the WE scan register 300. The configuration of this WE scan register 300 is shown in FIG.
The configuration is similar to that of the CE scan register 200 shown in FIG.

The shift operation of the WE scan register 300 is similar to that of the AD scan register 110 (see FIG. 7). However, as the shift clock, the CE of FIG.
Like the scan register 200, the shift clock SC
K1M and SCK2M are used.

In the normal operation, the enable signal TWE is set to "L" and the enable signal STBM is set to "H". As a result, the enable signal WEX changes to the inverter circuit G12, the 2-input latch circuit L2 and the NAND circuit.
It is transmitted to the output terminal we via the circuit G13. Since the enable signal WEX is inverted by the inverter circuit G12 and then inverted by the NAND circuit G13, as a result, the enable signal WE and the enable signal WE are obtained.
The logic level of X will be the same.

In the test, the enable signal STBM is set to "L" and the enable signal TWE becomes "L". Here, it is assumed that the enable signal TWE is low active.

When the output signal of output terminal Q of 2-input latch circuit L2 is set to "H" by the shift operation, enable signal TWE is transmitted to output terminal we. Therefore, the enable signal CE of the RAM 2 (see FIG.
(See) is enabled, the write operation is performed. When the output signal of the output terminal Q of the 2-input latch circuit L2 is set to "L", the enable signal TW
E is not transmitted to the output terminal WE, and the enable signal WE holds "H". Therefore, the write operation of RAM 2 is not performed.

Thus, the WE scan register 300
It is possible to control the write operation of the RAM 2 with the data set to.

(F) DIO Scan Register Group 400 FIG. 11 shows the detailed structure of the DIO scan register group 400. The DIO scan register group 400 includes m DIO scan registers 410. These DIO
The write data DIX (m-
1) to DIX (0) and read data DO (m-1)
~ DO (0) is input. From these DIO scan registers 410, read data DOX (m-1) to DOX (m-1)
OX (0) and write data DI (m-1) to DI
(0) is output.

The DIO scan register 410 is connected in series between the serial input terminal SID and the serial output terminal SOD to form a short scan path (m-bit scan path). Each DIO scan register 41
The serial output terminal SOR of 0 is connected to the serial input terminal SIR of the DIO scan register 410 at the next stage.

(G) DIO Scan Register 410 FIG. 12 shows the detailed structure of the DIO scan register 410. The DIO scan register 410 includes two-input latch circuits L2a and L2b and inverter circuits G15 and G1.
It includes 6, 2-input NAND circuits G17 and G18 and an exclusive OR circuit G19. In the input terminal dix,
Write data DIX from the logic circuit 4 (see FIG. 2)
(I) is given. Data from the RAM 2 (see FIG. 2) or the scan register 41 is output to the output terminal dox.
The data held by 0 is output and given to the logic circuit 4.

The shift operation is performed by the 2-input latch circuit L2a,
This is performed by applying two-phase shift clocks SCK1M and SCK2M to the second enable terminal EN2 of L2b. During the shift operation, it is necessary to set the enable signal STBM and the comparison signal CMP to "L" and the test mode signal TM to "H". With this setting, the output of the NAND circuit G18 becomes "H", and the NAN
The output of the D circuit G17 becomes "L". Therefore, the first enable terminal E of the two-input latch circuits L2a and L2b is
The potentials of N1 are both "L".

When the shift clock SCK1M is applied, data is taken in from the serial input terminal SIR to the first-stage two-input latch circuit L2a. This data is inverted by the inverter circuit G15 and given to the second input terminal D2 of the second-stage two-input latch circuit L2b. Next, when the shift clock SCK2M is applied, the inverted data is taken into the second-stage two-input latch circuit L2b. This data is inverted again by the inverter circuit G16 and output to the serial output terminal SOR.

Thus, the two-phase shift clock SCK
A 1-bit shift operation is performed by 1M and SCK2M. The serial data is the inverter circuits G15, G
Since it is inverted twice by 16, the serial input terminal SI
The data of R and the data of the serial output terminal SOR have the same logic level.

In normal operation, the enable signal STBM
Is set to "H" and the test mode signal TM is set to "L". With this setting, the 2-input latch circuit L2
The potentials of the first enable terminals EN1 of a and L2b both become "H". At this time, the write data DIX (i) given to the input terminal dix is the 2-input latch circuit L2.
It is taken in by a and transmitted to the output terminal di.
In addition, the read data DO given to the input terminal do
(I) is taken into the 2-input latch circuit L2b and transmitted to the output terminal dox.

In this state, the data input / output terminals of RAM 2 and logic circuit 4 are logically connected to each other.

At the time of testing, test mode signal TM is set to "H". At the time of test, the write operation and the read expected value data provided to the RAM 2 are set in the DIO scan register 410 by the shift operation. The write data is set in the 2-input latch circuit L2a, and the data inverted by the inverter circuit G15 becomes the read expected value data. The data held in the two-input latch circuits L2a and L2b due to the shift operation have opposite logics. Therefore, the read expected value data is also set in the 2-input latch circuit L2b.

Read data DO provided from RAM2
(I) is given to the input terminal do. The read data DO (i) is compared with the read expected value data (output of the inverter circuit G15) by the exclusive OR circuit G19. When the RAM2 is normal, the output of the exclusive OR circuit G19 is "L". When the RAM2 has a failure (when data different from the read expected value data is read from the RAM2), the exclusive O
The output of the R circuit G19 becomes "H".

In this state, the comparison signal CMP becomes "H". When the RAM 2 is normal, the output of the NAND circuit G18 is held at "H". When the RAM 2 has a failure, a low active clock is generated at the output terminal of the NAND circuit G18. The output of the NAND circuit G18 is N
Two-input latch circuit L inverted by AND circuit G17
2b to the first enable terminal EN1. Therefore, when the RAM2 is normal, the potential of the first enable terminal EN1 is held at "L", and when the RAM2 has a failure, a high active clock is applied to the first enable terminal EN1.

As described above, when the data different from the read expected value data is read from the RAM 2, a high active clock is applied to the first enable terminal EN1 of the 2-input latch circuit L2b. As a result, RAM2
The read data (data having a logic opposite to the read expected value data) is taken into the 2-input latch circuit L2b. As a result, the data held by the 2-input latch circuit L2b is inverted. When the RAM 2 is normal, such inversion of the held data does not occur. Therefore, the 2-input latch circuit L2b holds the test result of the RAM2.

FIG. 13 shows the DIO scan register 410.
Another example of the configuration will be shown. In the DIO scan register 410 of FIG. 13, the DIO scan register 410 of FIG.
On the contrary, the 2-input latch circuit L2b serves as the first-stage latch circuit and the 2-input latch circuit L2a serves as the second-stage latch circuit. In this DIO scan register 410, 2
The 2-input latch circuit L2a in the first stage holds the write data and the expected read value data, and the 2-input latch circuit L2b in the first stage holds the test result.

The DIO scan register group 400 of FIG.
Is the DIO scan register 41 of FIGS.
It is configured by using one of 0.

Incidentally, these DIO scan registers 4
10 is one of the important components of the present invention. As described above, in the DIO scan register 410 shown in FIGS. 12 and 13, one 2-input latch circuit holds write data and read expected value data (inverted data of write data) and the other 2-input latch circuit It has the feature of retaining test results.

(H) DMY Scan Register 500 FIG. 14 shows the detailed structure of the DMY scan register 500. The DMY scan register 500 includes latch circuits L1a and L1b. The DMY scan register 500 is a simple shift register that operates with a two-phase shift clock.

First, the first-phase shift clock SCK1M
Is given, the data on the serial input terminal SIR is taken into the latch circuit L1a. Since the output terminal Q of the latch circuit L1a is connected to the input terminal D of the latch circuit L1b, when the second-phase shift clock SCK2M is applied next, this data is taken into the latch circuit L1b and the serial output terminal Output to SOR.

In this way, the serial input terminal SIR
From 1 to serial output terminal SOR is performed.

(I) Latch Circuit L1 FIG. 15 shows an example of the configuration of the latch circuit L1 (an example of a CMOS circuit). Latch circuit L1 includes N-channel transistors N1 to N3, P-channel transistors P1 to P3, and inverter circuits G20 to G22.

When the enable terminal EN is supplied with a signal of "H", the output of the inverter circuit G20 becomes "L". As a result, the transistors N3 and P3 are turned on and the transistors P1 and N1 are turned off. The data given to the input terminal D passes through the transistors N3 and P3, is inverted by the inverter circuit G21, and is again inverted by the inverter circuit G.
It is inverted by 22 and transmitted to the output terminal Q. Therefore, no inversion of data occurs between the input terminal D and the output terminal Q.

When a signal of "L" is applied to the enable terminal EN, the output of the inverter circuit G20 becomes "H". As a result, the transistors N3 and P3 are turned off and the transistors P1 and N1 are turned on. Therefore, the power supply potential VDD is applied to the source of the transistor P2, and the ground potential GND is applied to the source of the transistor N2. Since the gates of the transistors N2 and P2 are connected to each other and their drains are also connected to each other, the pair of transistors N2 and P2 functions as an inverter circuit.

The inverter circuit configured at this time constitutes a storage loop together with the inverter circuit G21. That is, one output is supplied to the other input to each other. The data held in this storage loop is output to the output terminal Q.

The data held in the storage loop is the data given to the input terminal D immediately before the signal at the enable terminal EN changes to "L".

(J) Latch Circuit with Reset 600 FIG. 16 shows a detailed configuration of the latch circuit with reset 600. The reset latch circuit 600 is different from the latch circuit L1 of FIG. 15 in that a two-input NAND circuit G23 is provided instead of the inverter circuit G21.

When a "H" signal is applied to the reset terminal R, the NAND circuit G23 functions as an inverter circuit. Therefore, in this state, reset-equipped latch circuit 600 operates in the same manner as latch circuit L1 in FIG. That is, when the enable terminal EN is given a signal of "H", the data given to the input terminal D is transmitted to the output terminal Q. When the signal of "L" is given to the enable terminal EN, the data given to the input terminal D immediately before the signal of the enable terminal EN changes to "L" is held.

When an "L" signal is applied to the reset terminal R, the output of the NAND circuit G23 becomes "H", and the output terminal Q outputs an "L" signal which is an inverted signal of the output. .. That is, the latch circuit with reset 600 is reset. In this way, the reset terminal R of the latch circuit with reset 600 is active low.

(K) Two-Input Latch Circuit L2 FIG. 17 shows an example of the configuration of the two-input latch circuit L2 (CMO
An example of the S circuit) is shown. This 2-input latch circuit L2 has N
Channel transistors N1 to N5, P channel transistors P1 to P5 and inverter circuits G20, G21,
Includes G22 and G24.

First and second enable terminals EN1,
EN2 is high active, and it is prohibited to set both potentials to "H" at the same time.

First and second enable terminals EN1,
When the "L" signal is applied to both EN2, the outputs of the inverter circuits G20 and G24 both become "H". As a result, the transistors N3, P3, N5 and P5 are turned off, and the transistors P1, N1, P4 and N4 are turned on.
Therefore, the source of the transistor P2 is connected to the power supply potential VD.
D is given, and the ground potential G is applied to the source of the transistor N2.
ND is given. Since the gates of the transistors N2 and P2 are connected to each other and their drains are also connected to each other, the pair of transistors N2 and P2 functions as an inverter circuit.

The inverter circuit configured at this time constitutes a storage loop together with the inverter circuit G21. That is, one output is supplied to the other input to each other.
The data held in this storage loop is output to the output terminal Q.

The data held in the storage loop is the first or second input terminal D1, D when either of the signals of the first and second enable terminals EN1, EN2 is "H".
This is the data given in 2.

When the signal of "H" is applied to the first enable terminal EN1, the output of the inverter circuit G24 becomes "L". As a result, the transistors N5 and P5 are turned on and the transistors P4 and N4 are turned off. The data given to the first input terminal D1 is the data of the transistors N5 and P5.
, Is inverted by the inverter circuit G21, is inverted by the inverter circuit G22, and is transmitted to the output terminal Q. Therefore, inversion of data does not occur between the first input terminal D1 and the output terminal Q.

When the signal of "H" is applied to the second enable terminal EN2, the output of the inverter circuit G20 becomes "L". As a result, the transistors N3 and P3 are turned on and the transistors P1 and N1 are turned off. The data given to the second input terminal D2 is the data of the transistors N3 and P3.
, Is inverted by the inverter circuit G21, is inverted by the inverter circuit G22, and is transmitted to the output terminal Q. Therefore, no inversion of data occurs between the second input terminal D2 and the output terminal Q. (5) Operation of Test Circuit 3 (FIG. 4) The operation of the test circuit 3 of FIG. 4 will be described. The mode control signal MD is output from the output terminal Q of the latch circuit with reset 600.
Is output. The case where the mode control signal MD is "0" is called a non-bypass state, and the case where the mode control signal MD is "1" is called a bypass state. The inverter circuit G2 outputs an inverted signal of the mode control signal MD.

(A) Operation in Bypass State The multiplexer 700 selects the data of the serial input terminal SIB and gives the data to the serial output terminal SOB. That is, the serial data bypasses the scan register groups 100, 200, 300, 400, 500. At this time, the output of the inverter circuit G2 becomes "0", and the outputs of the AND circuits G4, G5, G6 are fixed to "0". Therefore, the shift clocks SCK1, SC
Even if K2 is given, these are CE scan register 2
00, WE scan register 300, DIO scan register group 400, and DMY scan register 500. Therefore, the data held by these scan register groups 200, 300, 400, 500 does not change.

On the other hand, AD scan register group 1
The shift clocks SCK1 and SCK2 are directly applied to 00. Therefore, the AD scan register group 100 can perform the shift operation even in the bypass state.

In addition, the low active strobe signal S
When TB is applied, the high active comparison signal CMP
However, the enable signal STBM is fixed to "0". The comparison signal CMP is used when testing the RAM 2.

(B) Operation in Non-Bypass State The multiplexer 700 selects the data of the serial output terminal SOR (see FIG. 14) of the DMY 500 and supplies the data to the serial output terminal SOB. That is, the serial data includes scan register groups 100, 200, 30.
Pass 0,400,500.

The output of the inverter circuit G2 becomes "1". When the test mode signal TM is set to "1" and the shift clocks SCK1 and SCK2 are given, these shift clocks SCK1 and SCK2 are AND circuit G.
5 and G6 and shift clock signals SCK1M, S
Scan register groups 200, 300, 4 as CK2M
Given to 00,500. As a result, these scan register groups 200, 300, 400, 500 perform a shift operation.

At this time, the AD scan register group 100
Since the shift clocks SCK1 and SCK2 are directly supplied to the AD scan register group 100, the AD scan register group 100 performs the shift operation simultaneously with the other scan register groups 200, 300, 400 and 500. In the non-bypass state, the comparison signal CMP is fixed at "0".

(C) Summary of Operation In the bypass state, serial data is directly transmitted from the serial input terminal SIB to the serial output terminal SOB, and AD
Only the scan register group 100 performs the shift operation.
In the non-bypass state, the serial data at the serial input terminal SIB is shifted in all the scan registers in the test circuit 3 and transmitted to the serial output terminal SOB. R
At the time of testing AM2, multiplexer 700 is set to the bypass state and strobe signal STB which is low active is applied to generate a comparison signal CMP. (6) Operation during Random March Test Next, a random march test using the test circuit 3 of FIG. 4 will be described.

(A) Initialization operation (see FIG. 18) Reset cycle (step S1; see FIG. 19) First, the reset signal RST becomes "L". This causes the mode control signal M output from the latch circuit 600.
D becomes "0". As a result, the test circuit 3 is set to the non-bypass state. Therefore, all the scan registers are in a shiftable state.

Scan In Cycle (Step S
2, S3; see FIG. 20) A plurality of test circuits 3 as shown in FIG. 2 are connected in series to form a long scan path. All of the plurality of test circuits 3 are in the non-bypass state, and all the scan registers are in the shiftable state. Therefore, desired data can be set in the scan register at an arbitrary position in each test circuit 3 by the shift operation. This is called a scan-in operation. FIG. 20 shows a scan-in operation for 1 bit.

Before the RAM 2 is tested, an initial value is set in each scan register by the scan-in operation. DMY scan register 500 in all test circuits 3
Is set to "1". RAM2 to be tested
“1” is set in the CE scan register 200 and the WE scan register 300 in the test circuit 3 of
A desired initial value (for example, address 0) is set in the D scan register group 100, and the DIO scan register group 400
Write data is set to.

Mode Set Cycle (Step S
4; see FIG. 21) Next, the mode setting signal MDST having a pulse of “H”
Is given. As a result, the mode control signal MD output from the latch circuits with reset 600 in all the test circuits 3 becomes "1", and all the test circuits 3 are set to the bypass state. In this state, the same data (data of the serial input terminal SIC) is given to the serial input terminals SIB of all the test circuits 3.

Since the AD scan register group 100 can perform the shift operation even in the bypass state, the data of the serial input terminal SIC is transferred to each test circuit 3.
Can be scanned in to the AD scan register group 100.

In the random march test, the test address is updated by scanning the entire period series into the AD scan register group 100.

(B) Write-all operation (see FIG. 22) In the random march test, there is a procedure for performing writing on all addresses while updating the addresses by scan-in of the entire period series. This is called a write-all operation (steps S11 and S12; see FIG. 23).

The contents of the AD scan register group 100 are updated by applying the shift clocks SCK1 and SCK2. The address signal A (i) is determined at the timing of the shift clock SCK1. Therefore, when the low active enable signal TCE is applied, the RAM 2
Starts operation based on this address signal. Further, when the low-active enable signal TWE is applied while the enable signal TCE is active, the RAM
2 performs a write operation based on the address signal.

(C) Read / write all operation (see FIG. 2)
(See 4) In the random march test, there is a procedure of performing reading and writing for all addresses while updating the addresses by scan-in of the entire period series. This is called a read / write all operation.

Read / Write Cycle (Step S
21, S22; see FIG. 25) The contents of the AD scan register group 100 are updated by applying the shift clocks SCK1 and SCK2. Address signal A at the timing of shift clock SCK1
(I) is confirmed. Therefore, when the low active enable signal TCE is applied, the RAM 2 starts its operation based on this address signal. After a certain delay,
The read data DO (i) is output from the RAM 2.

After that, when the low active strobe signal STB is applied, the read data DO (i) and DI
The read expected value data (the reverse logic of the write data) held by the O scan register group 400 is compared, and the result is stored in the DIO scan register group 400.

Thereafter, when the low-active enable signal TWE is applied while the enable signal TCE is active, the RAM 2 performs the write operation based on this address signal.

Reset cycle (step S23;
The reset signal RST becomes "L", and all the test circuits 3 are set to the non-bypass state.

Adjust Cycle (Step S2
4; refer to FIG. 26) Since the test result is held in the 2-input latch circuit L2b of each DIO scan register 410, DI of FIG.
When using the O-scan register 410, an adjustment cycle is necessary after the reset cycle.

In the adjust cycle, only the shift clock SCK2 is applied without applying the shift clock SCK1. As a result, the test result is transferred to the 2-input latch circuit L2a and given to the serial output terminal SOR.

It should be noted that the DIO scan register 4 of FIG.
In 10, the test result is output to the serial output terminal SOR, so the adjust cycle is not necessary.

Scan Out Cycle (Step S
25, S26; see FIG. 27) The test result held in the DIO scan register group 400 is taken out by the shift operation. This is called a scan-out operation. The data of all the scan registers appear in order on the serial output terminal SOC in synchronization with the shift clock SCK2. An external LSI tester tests the data of the serial output terminal SOC at the tester strobe timing. (7) Overall operation of random march test In the random march test, the test operation is performed twice in the same procedure while changing the data "0" / "1". The test procedure when the data is "0" is shown in FIG. 28, and the test procedure when the data is "1" is shown in FIG. These test procedures differ only in the scan-in data of the initialization operation. That is, the DIO scan register group 400
The only difference is that "0" or "1" is set as the initial data. As a result, the write data to the RAM 2 and the read expected value data are changed.

The test procedure of FIG. 28 will be described.

Initialization operation (0) (step S31) Write data “0” to the DIO scan register group 400.
To set.

Write All Operation (Step S32) "0" is written for all addresses.

Initialization operation (1) (step S33) Write data “1” to the DIO scan register group 400.
To set. As a result, "0" is set as the read expected value data.

Read / write all operation (step S
34) Read "0" and "1" for all addresses
Write. At this time, the read data is compared with the read expected value data in the DIO scan register group 400.

Initialization operation (0) (step S35) Write data “0” to the DIO scan register group 400.
To set. As a result, "1" is set as the read expected value data.

Read / Write All Operation (Step S36) “1” read and “0” for all addresses
Write. At this time, the read data is compared with the read expected value data in the DIO scan register group 400.

In the test procedure of FIG. 29, step S41
~ S46 corresponds to steps S31 to S36 of FIG. 28,
Only "0" / "1" of the data is different. (8) Operation of Test Circuit 3 (FIG. 5) Next, the operation of the test circuit 3 of FIG. 5 will be described. Mode control signal MD for controlling bypass state and non-bypass state
The operation of the test circuit 3 of FIG. 5 is the same as that of FIG.
The operation is the same as that of the test circuit 3. Therefore, only the method of setting the mode control signal MD will be described.

In the test circuit 3 of FIG. 4, the data set in the DMY scan register 500 is taken into the latch circuit 600 by the scan-in operation. On the contrary,
In the test circuit 3 of FIG. 5, the AD scan register group 100
The data set in a predetermined AD scan register 110 therein is taken into the latch circuit 600. Therefore, if desired data is set in the AD scan register 110 during the initialization operation, this data is set in the latch circuit 600 when the mode setting signal MDST is applied. Thereby, the mode (bypass state / non-bypass state) of each test circuit 3 is determined.

In FIG. 5, the latch circuit 600 is AD
Although it is connected to the serial output terminal SOR of the AD scan register 110 at the final stage in the scan register group 100, it may be connected to the serial output terminal SOR of another AD scan register 110 in the AD scan register group 100.

Since the DMY scan register 500 is unnecessary in the test circuit 3 of FIG. 5, the scale of the test circuit can be made smaller than that of the test circuit 3 of FIG. However, in the test circuit 3 of FIG. 5, since one AD scan register 110 stores the mode setting data and the initial address, these cannot be set independently. Therefore, the test circuit 3 of FIG.
The test circuit 3 is used properly according to need. (9) Other application examples The test circuit 3 shown in FIGS. 4 and 5 is a single-port RAM.
Not only can it be applied to a multi-port RAM. FIG. 30 shows a case where these test circuits 3 are applied to the dual port RAM 2b. Dual port R
The test circuit 3 is assigned to each of the two ports (port A and port B) of the AM 2b.

Each test circuit 3 has a serial input terminal SI
B, serial output terminal SOB and various control signals RS
T, MDST, SCK1, SCK2, STB, TM, T
Control terminals for CE and TWE are provided independently and are connected in the semiconductor chip. At each port, a random march test can be performed as in the case of single port RAM.

(10) Another Example of Test Circuit 3 FIG. 31 shows still another example of the configuration of the test circuit 3.
The test circuit 3 of FIG. 31 differs from the test circuit 3 of FIG. 4 in the following points. An OR circuit G7 and an inverter G8 are further provided.

The enable signal CEA is applied to one input terminal of the OR circuit G7 via the inverter G8. O
The test mode signal TM is applied to the other input terminal of the R circuit G7.
Is given. The output of the OR circuit G7 is applied to the DIO scan register group 400 as the test mode enable signal TMCEA. DIO scan register group 400
Is not given the enable signal STBM, but is instead given the enable signal CEA.

FIG. 32 shows still another example of the configuration of the test circuit 3. The test circuit 3 of FIG. 32 is different from the test circuit 3 of FIG. 31 in that the enable signal CEA is applied to the OR circuit G7 via a passage wiring instead of the inverter G8. The configuration of the other parts is similar to that of the test circuit 3 of FIG.

(A) DIO scan register group 400
Another Example FIG. 33 shows the configuration of the DIO scan register group 400 used in the test circuit 3 of FIGS. 31 and 32.

The DIO scan register group 400 of FIG.
Is different from the DIO scan register group 400 of FIG. 11, the enable signal CEA is applied to each DIO scan register 410 instead of the enable signal STBM,
The point is that the test mode enable signal TMCEA is applied instead of the test mode signal TM. The configuration of the other part is the same as that of the DIO scan register group 40 shown in FIG.
It is similar to the configuration of 0.

(B) Another Example of DIO Scan Register 410 FIG. 34 shows a detailed configuration of the DIO scan register 410 included in the DIO scan register group 400 of FIG.

The DIO scan register 410 of FIG. 34 is different from the DIO scan register 410 of FIG.
First enable terminal EN1 of the 2-input latch circuit L2a
Enable signal C instead of enable signal STBM
EA is applied to the NAND circuit G17, instead of the test mode signal TM, the test mode enable signal TMCE is supplied.
This is the point where A is given. The configuration of the other parts is similar to the configuration of the DIO scan register 410 of FIG.

As described above, if the CE scan register 200 of FIG. 9 is used, the AD scan register 11 of FIG.
When 0 is in normal operation, it operates as an address latch circuit. Since the enable signal CEA is applied to the 2-input latch circuit of the DIO scan register 400 of FIG. 34 similarly to the AD scan register 110 of FIG. 7, the 2-input latch circuit L2a operates as a data input latch during normal operation.

On the other hand, test mode enable signal TMCEA applied to 2-input latch circuit L2b is generated by a gate circuit formed of an inverter G8 and an OR circuit G7 as shown in FIG.

Since the test mode signal TM is "L" in the normal operation, the test mode enable signal TMC is used.
EA becomes an inverted signal of the enable signal CEA. Also,
Since the comparison signal CMP is set to "L" during normal operation, the output of the 2-input NAND circuit G18 becomes "H". As a result, the test mode enable signal TMCE
A is inverted by the 2-input NAND circuit G17 and transmitted to the first enable terminal EN1 of the 2-input latch circuit L2b.

The enable signal CEA is inverted by the inverter G8 shown in FIG.
Since it is inverted by the circuit G17, as a result, the enable signal CEA is transmitted to the first enable terminal EN1 of the 2-input latch circuit L2b as a non-inverted signal. Therefore, in the normal operation, the 2-input latch circuit L2b operates as a data output latch.

This latch operation is performed by the enable signal CEA.
This is performed in response to the fall of (enable signal CEX).

Since the test mode signal TM is "H" during the test, the test mode enable signal TMC is used.
EA becomes "H" regardless of the enable signal CEA. Therefore, 2-input NAND circuit G17 is activated and a test operation is performed in response to comparison signal CMP.

When the test circuit 3 of FIG. 32 is used, the inverted signal of the enable signal CEA is 2 in FIG.
It is transmitted to the first enable terminal EN1 of the input latch circuit L2b. Therefore, the 2-input latch circuit L2b latches the data at the input terminal do in response to the rising of the enable signal CEA (enable signal CEX). Figure 3
The test circuit 3 of No. 1 and the test circuit 3 of FIG. 32 are selectively used as needed. (11) Other Embodiments FIG. 35 shows the configuration of the main part of the second embodiment of the present invention. This embodiment differs from the embodiment of FIG. 1 in that the mode control latch 70 is not provided and the mode control signal MD is directly applied from the outside.

FIG. 36 shows the structure of the main part of the third embodiment of the present invention. In this embodiment, the shift clock SCKA is applied to the AD scan register group 10, and the DI scan register group 20 and the DO scan register group 3 are supplied.
The shift clock SCKD is applied to 0. Since the shift clock SCKA and the shift clock SCKD are separated, the AD scan register group 10 can perform the shift operation while the operations of the DI scan register group 20 and the DO scan register group 30 are stopped.

Test circuit 3 of FIGS. 1, 35 and 36
Can also be applied to the semiconductor integrated circuit of FIG.

(12) Fourth Embodiment (a) Overall Structure FIG. 37 is a block diagram showing the structure of the scanpath device (test auxiliary circuit) of the semiconductor integrated circuit device according to the fourth embodiment.

Around the RAM 2, a plurality of AD scan registers 10a and a plurality of data input / output scan registers (hereinafter referred to as DIO scan registers) 25a.
Are arranged. The configuration of each AD scan register 10a is similar to the configuration of the AD scan register 10a shown in FIG.

These scan registers 10a and 25a
Is connected to another logic circuit (not shown) on the semiconductor chip and RAM2 during normal operation of RAM2,
At the time of testing M2, the other logic circuits and RAM2 are separated from each other.

These scan registers 10a and 25a
Are serially connected between the serial input terminal SIC and the serial output terminal SOC to form a scan path. Test data such as address signals and data are provided to RAM 2 by the scan path shift function. R
The test result of AM2 is taken into the DIO scan register 25a in the scan path.

(B) First Example of DIO Scan Register FIG. 38 shows a first example of the DIO scan register 25a. The scan register 25a has the same structure as the scan register 410 shown in FIG.

The serial input terminal SI is connected to the input terminal D2 of the first latch circuit L2a, the first parallel input terminal PI1 is connected to the input terminal D1 of the first latch circuit L2a, and the first parallel output terminal. PO1 is connected to the output terminal Q of the first latch circuit L2a. The second parallel input terminal PI2 is connected to the input terminal D1 of the second latch circuit L2b, and the second parallel output terminal PO2 is the second
Is connected to the output terminal Q of the latch circuit L2b, and the serial output terminal SO is connected to the output terminal of the inverter G16.

First phase serial shift clock SCK1
The serial clock terminal sck1 receiving the second latch circuit L2b is connected to the enable terminal EN2 of the first latch circuit L2a, and the serial clock terminal sck2 receiving the second phase serial shift clock SCK2 is connected to the enable terminal EN2 of the second latch circuit L2b. .. Parallel clock PCK
The parallel clock terminal pck1 receiving 1 is connected to the enable terminal EN1 of the first latch circuit L2a. Test clock terminal tck for receiving the test clock TCK
Is connected to one input terminal of the NAND circuit G18, and the test mode terminal tm for receiving the test mode signal TM is N
It is connected to one input terminal of the AND circuit G17.

The data of the serial input terminal SI and the first parallel input terminal PI are provided in the first latch circuit L2a.
The data of 1 is input, and the data obtained by inverting the output of the first latch circuit L2a and the data of the second parallel input terminal PI2 are input to the second latch circuit L2b.

The data of the second parallel input terminal PI2 is compared with the inverted data of the data held in the first latch circuit L2a by the exclusive OR circuit G19. The comparison result is given to the other input terminal of the NAND circuit G18. The output of the NAND circuit G18 is NA
It is given to the other input terminal of the ND circuit G17. NAN
Output PCK2 of D circuit G17 (second test clock)
Is a second latch circuit L2 as a latch enable signal.
It is given to the enable terminal EN1 of b.

A set of data input terminal and data output terminal of RAM 2 is assigned to one DIO scan register 25a. The second of each DIO scan register 25a
The parallel input terminal PI2 of is connected to the data output terminal DOi (i = 1, ..., N) of the RAM2. Here, n is a natural number. First of each DIO scan register 25a
The parallel output terminal PO1 of is connected to the data input terminal DIi of the RAM2. That is, in the DIO scan register 25a of FIG. 38, the input data to the RAM2 is assigned to the master latch and the output data from the RAM2 is assigned to the slave latch.

FIG. 39 shows an example in which the DIO scan register 25a having the same function as the DIO scan register 25a of FIG. 38 is constituted by a MOS circuit. DI of FIG. 39
The O scan register 25a includes N channel MOS transistors N31 to N34 and inverters G31 to G34.
including. The inverters G31 and G32 form a ratio type latch circuit L31, and the inverters G33 and G34 also form a ratio type latch circuit L32. Inverter G32, G
34 has a driving capability smaller than that of the inverters G31 and G33, respectively. 38 and 39, the parts to which the same reference numerals are assigned indicate the same or corresponding parts.

Note that instead of using the N-channel MOS transistor as shown in FIG. 39, a P-channel MO transistor is used.
An S transistor may be used.

Even if a CMOS 2-input latch circuit is used as shown in FIGS. 40 and 41 in place of the ratio type latch circuit of FIG. 39, the DIO scan register 25a having the same function as the DIO scan register 25a of FIG. 38 is obtained. Can be configured.

In the DIO scan register 25a of FIG. 40, the node B is directly connected to the second parallel output terminal PO2. On the other hand, the DIO scan register 25 of FIG.
At a, node B is connected to the second parallel output terminal PO2 via two inverters. 40 and 4
In FIG. 1, the parts denoted by the same reference numerals as those in FIGS. 38 and 39 indicate the same or corresponding parts.

(C) Operation of DIO Scan Register The operation of the DIO scan register 25a will be described with reference to FIG.

During normal operation of the RAM2, the serial clock terminals sck1 and sck2 and the test mode terminal t
The potential of m is set to "L", and the parallel clock terminal p
The potential of ck1 is set to "H". Thereby, the first
The data to be input to the RAM2 is transmitted from the parallel input terminal PI1 to the first parallel output terminal PO1.

Further, the second test clock PCK becomes "H". Thereby, the second parallel input terminal P
The data output from the RAM2 is transmitted from I2 to the second parallel output terminal PO2. At this time, the potential of the test clock terminal tck may be set to either "H" or "L".

At the time of testing the RAM2, the potential of the parallel clock terminal pck1 is set to "L", the potential of the test clock terminal tck is set to "L", and the potential of the test mode terminal tm is set to "H". .. Thereby,
RAM2 is separated from other logic circuits. The shift operation is performed by the first-phase and second-phase clocks SCK1 and SCK2 applied to the serial clock terminals sck1 and sck2, and the test result is read.

(D) Operation of the Fourth Embodiment FIG. 42 is a timing chart showing the shift operation of the scanpath device of FIG. Each AD scan register 10a
To the serial clock terminal sck1a of each DIO scan register 25a and the serial clock terminal sck1a of each AD scan register 10a.
Serial clock terminal s of IO scan register 25a
The second phase clock is applied to ck2.

Serial input terminal S of each scan register
Data for I is taken into node A in its scan register by the first phase clock. The data of the node A is inverted and transferred to the node B by the second phase clock. The data of the node B is inverted and given to the serial output terminal SO.

As a result, a 1-bit shift operation is performed from serial input terminal SI to serial output terminal SO. In this way, the shift operation is performed by the clocks of the first phase and the second phase, and the test data is set and the test result is read.

FIG. 43 is a timing chart showing an operation at the time of testing the scan path device of FIG. At the time of testing the RAM, the potential of the test mode terminal tm is set to "H". The serial clock terminals sck1 and sck2 of the DIO scan register 25a are supplied with the first-phase and second-phase shift clocks SCK1 and SCK2. AD
Serial clock terminal sck of the scan register 10a
1a and sck2a have shift clocks SCK1 and SCK
First-phase and second-phase shift clocks SC different from 2
K1a and SCK2a are given. As a result, the test address is updated.

Further, the inverted data of the read expected value is set to the first parallel output terminal PO1. The inverted data is further inverted by the inverter G15 (inverter G31 in FIG. 39). As a result, the read expected value is compared with the data read from the RAM 2 to the second parallel input terminal PI2 by the exclusive OR circuit G19.

Each time data is read from RAM 2, test clock TCK is applied to test clock terminal tck. Therefore, when fail data (wrong data) is read from the RAM 2, the test clock terminal tck
The second test clock PCK2 having the same phase as the test clock TCK of is generated. As a result, the data of the second parallel input terminal PI2 is transmitted to the second parallel output terminal PO2 via the node B.

A read expectation value (data opposite to the inverted data of the first parallel output terminal PO1) is set in advance in the node B by the shift operation. Therefore, RA
When the fail data is read from M2, the data at the second parallel output terminal PO2 is inverted.

After the above operation is performed for a plurality of addresses, the shift operation shown in FIG. 42 is performed again to read the test result. This allows DIO
Based on whether or not the data held by the latch circuit in the scan register 25a is inverted, it is possible to know whether or not the data different from the expected read value is given to the second parallel input terminal PI2.

(E) Second Example of DIO Scan Register FIG. 44 is a circuit diagram showing another example of the DIO scan register 25a. The DIO scan register 25 of FIG.
The a has the same configuration as the DIO scan register 410 of FIG. In FIG. 44, the same reference numerals as those in FIG. 38 denote the same or corresponding parts.

The second latch circuit L2b has the data of the serial input terminal SI and the second parallel input terminal PI.
The data of 2 is input. The inverted data of the output of the second latch circuit L2b and the data of the first parallel input terminal PI1 are input to the first latch circuit L2a.

The data of the second parallel input terminal PI2 is compared with the inverted data of the data held in the first latch circuit L2a by the exclusive OR circuit G19. The comparison result is given to the NAND circuit G18. The output of the NAND circuit G18 is the NAND circuit G17.
Given to. The output PCK2 (second test clock) of the NAND circuit G17 is given to the enable terminal EN1 of the second latch circuit L2b as a latch enable signal.

The second parallel input terminal PI2 is the RAM2
Data output terminal, and the first parallel output terminal PO1 is connected to the data input terminal of RAM2.

In the DIO scan register 25a of FIG. 38, the data input to the RAM2 is assigned to the master latch and the data output from the RAM2 is assigned to the slave latch, whereas in the DIO scan register 25a of FIG. The data output from RAM2 is assigned to the master latch and the data input to RAM2 is assigned to the slave latch.

FIG. 45 shows an example in which a DIO scan register having a function similar to that of the DIO scan register 25a shown in FIG. 44 is constructed using a ratio type latch. In FIG. 45, the same reference numerals as those in FIG. 38 denote the same or corresponding parts.

The operation of the DIO scan register 25a shown in FIG. 45 is the same as that of the DIO scan register 25 shown in FIGS.
It is almost the same as the operation a. However, in the scan register 25a shown in FIGS. 44 and 45, the test result is held in the master latch, so that care must be taken when reading the test result by the shift operation. That is,
In order to read the test result nondestructively, first, the shift clock is applied to the serial clock terminal sck2 to transfer the test result to the slave latch, and then the test result shown in FIG.
It is necessary to perform the shift operation as shown in.

(F) Other Examples of Comparison Circuit and Latch Enable Circuit In the examples of FIGS. 38 to 45, the second parallel input terminal PI is used.
The exclusive OR circuit G19 is used as a comparison circuit for comparing the data stored in the first latch circuit L2a with the data stored in the second latch circuit L2a.
NA as a latch enable circuit for making the latch circuit L2b of the above latch the data of the second parallel input terminal PI2.
Only the ND circuits G17 and G18 are used. However, the comparison circuit and the latch enable circuit are not limited to such a combination of logic circuits.

For example, as shown in FIG. 46, an exclusive NOR circuit G41 is used as a comparison circuit, and NOR circuits G42 and O are used as a latch enable circuit.
The R circuit G43 may be used. One input terminal of the NOR circuit G42 is connected to the output terminal of the exclusive NOR circuit G41, and the other input terminal is connected to the inverted test clock terminal / tck that receives the inverted test clock / TCK. One input terminal of the OR circuit G43 is NOR
It is connected to the output terminal of the circuit G42 and is connected to the inversion test mode terminal / tm which receives the other neuron unit mode signal / TM.

(G) Advantages of the Fourth Embodiment According to the fourth embodiment, one of the two latch circuits forming each scan register is assigned to the data input and the other of them is assigned to the data output. .. Therefore, 1
Data can be input and output with one scan register. Therefore, the scale of the scan path device of the semiconductor integrated circuit device can be reduced.

In particular, if each scan register is formed of two ratio type latch circuits as shown in FIGS. 38 and 44, the number of elements used is extremely small. Therefore, it is very effective in reducing the circuit scale.

(H) Other Application Examples In the fourth embodiment, the circuit to be tested is RAM2.
In particular, the data output terminal of the RAM 2 is connected to the scan path device. However, the scanpath device according to the present invention may be connected to a data bus connected to a plurality of RAMs.

The circuit to be tested is not limited to RAM. The scanpath device according to the present invention can be applied to any circuit that continuously outputs data "0" or "1", and similar effects can be obtained.

[0292]

According to the first and second aspects of the present invention, it is possible to input and output data with one scan register, and the scale of the scan path device is reduced.

In particular, according to the second invention, most of the scan path device can be used during normal operation. Therefore, it is possible to suppress an increase in chip area and manufacturing cost of the semiconductor integrated circuit device due to the addition of the scan path device.

According to the third to ninth inventions, the test time can be shortened without complicating the wiring.

Particularly, according to the fourth and sixth inventions, the efficiency of the test is further improved. Further, according to the fifth, seventh and eighth inventions, the wiring is further simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a first embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration of the first embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between a test circuit and a RAM.

FIG. 4 is a block diagram showing an example of a configuration of a test circuit.

FIG. 5 is a block diagram showing another example of the configuration of the test circuit.

FIG. 6 is a block diagram showing a configuration of an AD scan register group.

FIG. 7 is a block diagram showing a configuration of an AD scan register.

FIG. 8 is a block diagram showing an example of a configuration of a CE scan register.

FIG. 9 is a block diagram showing another example of the configuration of the CE scan register.

FIG. 10 is a block diagram showing a configuration of a WE scan register.

FIG. 11 is a block diagram showing a configuration of a DIO scan register group.

FIG. 12 is a block diagram showing an example of a configuration of a DIO scan register.

FIG. 13 is a block diagram showing another example of the configuration of a DIO scan register.

FIG. 14 is a block diagram showing a configuration of a DMY scan register.

FIG. 15 is a circuit diagram showing a configuration of a latch circuit.

FIG. 16 is a circuit diagram showing a configuration of a latch circuit with reset.

FIG. 17 is a circuit diagram showing a configuration of a 2-input latch circuit.

FIG. 18 is a flowchart for explaining an initialization operation.

FIG. 19 is a waveform diagram showing a reset cycle.

FIG. 20 is a waveform diagram showing a scan-in cycle.

FIG. 21 is a waveform diagram showing a mode set cycle.

FIG. 22 is a flowchart for explaining a write all operation.

FIG. 23 is a waveform diagram showing a write cycle.

FIG. 24 is a flowchart for explaining a read / write all operation.

FIG. 25 is a waveform chart showing a read / write cycle.

FIG. 26 is a waveform diagram showing an adjust cycle.

FIG. 27 is a waveform chart showing a scan-out cycle.

FIG. 28 is a flowchart for explaining a random march test.

FIG. 29 is a flowchart for explaining a random march test.

FIG. 30 is a block diagram showing another application example of the present invention.

FIG. 31 is a block diagram showing still another example of the configuration of the test circuit.

FIG. 32 is a block diagram showing still another example of the configuration of the test circuit.

FIG. 33 is a block diagram showing a configuration of a DIO scan register group used in the test circuits of FIGS. 31 and 32.

34 is a block diagram showing a configuration of a DIO scan register included in the DIO scan register group of FIG. 33.

FIG. 35 is a block diagram showing a configuration of a main part of a second embodiment of the present invention.

FIG. 36 is a block diagram showing a configuration of a main part of a third embodiment of the present invention.

FIG. 37 is a block diagram showing a fourth embodiment of the present invention.

FIG. 38 is a circuit diagram showing an example of a configuration of a DIO scan register.

FIG. 39 is a circuit diagram showing another example of the configuration of the DIO scan register.

FIG. 40 is a circuit diagram showing another example of the configuration of the DIO scan register.

FIG. 41 is a circuit diagram showing another example of the configuration of the DIO scan register.

FIG. 42 is a timing chart showing the shift operation of the scan path device.

FIG. 43 is a timing chart showing an operation during a test of the scan path device.

FIG. 44 is a circuit diagram showing another example of the configuration of the DIO scan register.

FIG. 45 is a circuit diagram showing another example of the configuration of the DIO scan register.

FIG. 46 is a diagram showing another example of configurations of a comparison circuit and a latch enable circuit.

FIG. 47 is a block diagram showing a first conventional technique.

FIG. 48 is a circuit diagram showing a configuration of an AD scan register.

FIG. 49 is a circuit diagram showing a configuration of a DI scan register.

FIG. 50 is a circuit diagram showing a configuration of a DO scan register.

FIG. 51 is a timing diagram showing a shift operation in the first conventional technique.

FIG. 52 is a timing diagram showing an operation during a test in the first conventional technique.

FIG. 53 is a block diagram showing a second conventional technique.

FIG. 54 is a block diagram showing a configuration of a test circuit according to a second conventional technique.

FIG. 55 is a diagram showing an example of a RAM.

FIG. 56 is a waveform chart showing a write operation.

FIG. 57 is a waveform chart showing a read / write operation.

FIG. 58 is a diagram for explaining a full cycle sequence.

FIG. 59 is a block diagram showing an example of a configuration of a third conventional technique.

FIG. 60 is a block diagram showing another example of the configuration of the third conventional technique.

[Explanation of symbols]

 1 semiconductor chip 2 RAM 3 test circuit 10 AD scan register group 20 DI scan register group 30 DO scan register group 40 mode setting scan register 50 selector 60 gate circuit 70 mode control latch 100 AD scan register group 400 DIO scan register group 410 DIO Scan register 500 DMY Scan register 600 Latch circuit with reset 700 Multiplexer L2a, L2b Two-input latch circuit G17, G18 NAND circuit G19 Exclusive OR circuit dix, do input terminal di, dox output terminal SIR serial input terminal SOR serial output terminal SCK , SCK1M, SCK2M Shift clocks In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (8)

[Claims] 1. A plurality of scan registers connected in series, each of the plurality of scan registers including: a serial input terminal, a first parallel input terminal, a second parallel input terminal, and holding applied data. Holding means for outputting given data, second holding means for holding and outputting given data, first transmitting means for transmitting data of the first parallel input terminal to the first holding means, the serial Second transmitting means for transmitting the data of the input terminal to one of the first and second holding means, a third transmitting means for transmitting the data of the second parallel input terminal to the second holding means, Fourth transmitting means for transmitting data output from the one of the first and second holding means to the other of the first and second holding means, and output from the first holding means First receive the data 1
Second parallel output terminal for receiving data output from the second holding means
A parallel output terminal, a serial output terminal for receiving data output from the other of the first and second holding means, and a data output from the first holding means for data of the second parallel input terminal Comparing comparing means and activating means for activating or deactivating the third transmitting means according to the comparison result of the comparing means, wherein the serial input terminal of each scan register is the serial output of the preceding scan register. Connected to the terminal,
Scan campus equipment. 2. A plurality of scan registers connected in series, wherein each of the plurality of scan registers holds a serial input terminal, a first parallel input terminal, and a second parallel input terminal. First holding means for outputting, second holding means for holding and outputting given data, first transmitting means for transmitting data of the first parallel input terminal to the first holding means, the serial Second transmitting means for transmitting the data of the input terminal to one of the first and second holding means, a third transmitting means for transmitting the data of the second parallel input terminal to the second holding means, Fourth transmitting means for transmitting data output from the one of the first and second holding means to the other of the first and second holding means, and output from the first holding means First receive the data 1
Second parallel output terminal for receiving data output from the second holding means
A parallel output terminal, a serial output terminal for receiving data output from the other of the first and second holding means, and a data output from the first holding means for data of the second parallel input terminal Comparing means for comparing, first activating means for activating or deactivating the first transmitting means, second for activating or deactivating the third transmitting means according to the comparison result of the comparing means Activating means and responsive to a predetermined signal to activate or deactivate the third transmitting means in synchronization with the first activating means irrespective of the comparison result of the comparing means. Including a forcing means for forcing a second activating means, wherein the serial input terminal of each scan register is connected to the serial output terminal of the previous scan register,
Scan campus equipment. 3. A first scan register group including a plurality of scan registers connected in series, and a second scan register group including a plurality of scan registers connected in series to an output of the first scan register group. , And a means for controlling the first and second scan register groups such that the second scan register group stops the shift operation and the first scan register group performs the shift operation. apparatus. 4. An input terminal for receiving serial data, a first scan register group including a plurality of scan registers serially connected to the input terminal, and a plurality of scans serially connected to an output of the scan register group. A second scan register group including a register, an output terminal, data of the input terminal and data output from the second scan register group are selected, and the selected data is given to the output terminal. Selection means,
And when the data of the input terminal is selected by the selecting means, the second scan register group stops the shift operation and the first scan register group performs the shift operation. A scanpath device comprising first control means for controlling the second shift register group. 5. A second control means for receiving data from one of the scan registers included in the first and second scan register groups and controlling the selecting means in response to the data. Item 4. The scan path device according to Item 4. 6. A storage means for storing data and a scan path means, wherein the scan path means includes an input terminal for receiving serial data, a plurality of scan registers connected in series, and serially from the input terminal. A first scan register group for giving the given data as an address signal to the storage means in parallel; and a plurality of scan registers connected in series, wherein the data serially given from the first scan register group is A second scan register group which is given to the storage means in parallel or receives data output from the storage means in parallel, one of data of the input terminal and data output from the second scan register group is selected. Selecting means for outputting the selected data, and the input by the selecting means. Control the first and second scan register groups so that the second scan register group stops the shift operation and the first scan register group performs the shift operation when the child data is selected. A semiconductor integrated circuit device including first control means for controlling the semiconductor integrated circuit device. 7. The second scan path means receives data provided from one of the scan registers included in the first and second scan register groups, and controls the selection means in response to the data.
The semiconductor integrated circuit device according to claim 6, further comprising: 8. The scan path means is provided in series with the first and second scan register groups and holds a mode setting data, and a mode setting data held in the holding means. 7. The semiconductor integrated circuit device according to claim 6, further comprising second control means that responds to control the selection means.