JPS58145233A - Logical circuit provided with diagnosing circuit - Google Patents

Abstract

PURPOSE:To reduce the test time, by performing set/reset operation with a signal by-passing the prestage logic at the through-mode and performing the operation with a signal from the prestage logic at the normal mode, by using control pins, a decoder and gates. CONSTITUTION:A pattern ''00'' is set to a register 6 from control pins 6. A control line 8 is set to ''1'' and lines 9, 10 are set to ''0'' by a decoder 7, only an LSI2 is the normal mode and LSIs 3, 4 are the through-mode, allowing to check failures at the inside of the LSIs. In the production of the test pattern for the purpose, when the by-pass signal for the LSIs 3, 4 and the logical block of the LSI2, and a switch is used for a switch gate, the LSI3 or 4 are used, the test pattern of the LSI2 is used and the rate of detection almost equal to the single LSI2 is obtained. Similarly, a check is performed for the LSIs 3, 4 by resetting addresses with the control pins 5.

Description

[Detailed description of the invention] The present invention relates to a logic circuit incorporating a diagnostic circuit.

In order to improve the diagnosability of large-scale logic circuits, conventional methods have been used to add scan paths to existing circuits and divide complex, large-scale circuits into simple, small-scale circuits. An example of this is LS8D (1 level 5ens
tive 5can design) method and random scan method are available. In these scan methods, input signals can be easily set (scan-
(scan and
However, it has some problems.

(1) The amount of hardware increases due to the scan path.

(In order to ensure that the 2-in scan fist in/out function is executed correctly, the clock control between the latches must be devised.

(3) It takes time to scan in/out when running a test.

In particular, regarding (2), the designer must either take more complex circuit measures using multiple clocks, or design the circuit so that in-phase transfer does not occur, and a scan-type structure must be used. This is a serious drawback.

The purpose of the invention is to solve the aforementioned problems (2) and (3) by facilitating the control and observation of the partial four-way system and improving diagnostic performance without using the above-mentioned scanning method. Its purpose is to provide logic circuits.

That is, the logic circuit is divided based on a certain standard, and addresses are assigned to the partial circuit locations. A switch function and a bypass are built into each partial circuit, and depending on the control signal, it is possible to select between a mode in which one circuit operates as it should (normal mode) and a mode in which the intermediate circuit is bypassed (through mode). Only the subcircuit to be diagnosed is in normal mode, other subcircuits are in through mode.
Control of the subcircuit to be diagnosed by operating in mode.

This makes observation easy.

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 shows the overall configuration of the circuit. As an example, consider a package made up of LSIs. That is, 1 represents the package and 2 to 4 represent LSIt-. 6riLS This is a register for storing the rounding address of I selection, and the I selection can be set from control pin 5. 7 is a decoder, and LSIs 2 to 4 are selected via signal lines 8 to 10 according to a designated address.

11-20 are input edge bins of the package, 31-4
0 is the output edge bin. Numbers 5 to 10 are added to improve diagnostic performance, resulting in nine logics.

FIG. 2 is an example of the configuration of an LSI, and L in FIG.
Shown in SI3. The input edge bins 53 and 54, the output edge bins 71 and 72, and the logic block 3' are conventional LSI components, and other parts are added to improve diagnosability. The signal line 9 is connected to the control bin 52 .

Either the output signal 60 of the 5WG83i logic block 3' immediately before the Itl edge bin 71 or the input edge bin 5
This is a switch gate having a function of selecting one of the signals 81 that has bypassed the logic block 3' from the logic block 3' in accordance with the control signal 9. Similarly, it has a function to select, depending on the control signal 9, either the output signal 61 of the 5WG84tl logic block 3' immediately before the output edge 72, or the good signal 82 that bypasses the logic block 3' from the input edge bin 54. It is a switch gate.

Figure 3 shows the details of the switch game (SWG).

Depending on whether the signal on the control line 9 is 1 or 0, either the output 4I60 or the bypass f181 signal is selected, and the II
! 71.

In an LSI with such additional logic, when the control signal is 1, '@ operates exactly the same as conventional logic (this is called normal mode), and when the control signal is 0, the logic inside the LSI operates. It is possible to easily transmit a signal on the input side to the output side without any interference (this is called the through mode).

In the example shown in FIG. 2, the number of input edge bins and the number of output edge bins are equal. When the number of input edge pins is large, a plurality of bypass signals are logically summed just before the switch gate 94 as shown in FIG. Conversely, when there are many output edge bins, the bypass signal is branched just before the switch gate 94 and connected to multiple switch gates 94 as shown in FIG. Although only the additional logic is shown and overwhelm is demonstrated using a switch gate (switch gate), this method cannot be used in cases where the delay of the switch gate adversely affects the circuit operation.

A method using a switch/latch to solve this problem will be explained below. FIG. 6 shows an example in which switch latches 85 and 86 are used instead of switch gates for LSI 3. Conventional LSI logic beam, 'trail, //2
divided into two parts. This division is done as follows. From the output edge bins 71 and 72, the input edge 911 or input edge! ! Reverse trace on the corresponding cabinet. In the partial circuit cut out in this way, the remaining logic block (combinational circuit) with the latch replaced with a switch latch (8WL) is
It is. In other words, in this example, 1. , // are subcircuits surrounded by two switch latches 85, 86 and output edges 71, 72. Switch-Latch 8.5H Logic Block Lt'? Depending on the control signal 9, it is selected whether to perform a normal latch operation based on the signals 62 to 65 that have passed through, or to perform only a set/reset operation based on the ratio signal 81 that bypasses the logic blocks L and ' from the input edge own bin 53. It has a function. Switch latch 86 operates in a similar manner.

FIG. 7 shows details of the switch/latch 85.

114 is a D type 7-lip type with set/reset priority.
It's a flop. Input status 62fl) Riga signal Ti, 6
3 gives theta signal. Switch gates 112 and 113 are connected to input line 6 depending on whether the signal on control line 9 is 1 or 0.
A combination of reset signal R on 4 and set signal 8 on 65, fi! 81 and its inverted signal by the inverter 125.
3 and 124. In other words, normal mode (control line 9
In 1), the switch/latch 85Lri latch 114 operates as the through mode (control f19 is set to O).
), only the set/reset operation is performed, and the bypass line 81
and its inverted signal are output on lines 121 and 122. The circuits added in addition to the conventional latch to improve diagnostic performance are switch gates 112 and 113, an inverter 125, and signal lines 9 and 81.

In an LSI with such additional logic, when the control signal is 1 (normal mode), it operates exactly the same as conventional logic.
When the control signal is 0 (through mode), without operating most of the logic (blocks L,') in the HLSI,
A signal on the input side can be easily transmitted to the output side.

Next, an outline of the operation of an embodiment of the present invention will be explained using FIG. Here, LSI2 to 4 included in the package
, addresses 1 to 3 are assigned to each of them. First, do not select any LSI from control bin 5.
Set the button number 001 in register 6. At this time, all the controls 418 to 10 become @0# via the decoder 7, that is, all the LS Ii miss-through states occur. Under such conditions, it is possible to inspect the package substrate, the input/output edge/bi/junction of the LSI, the bypass line within the LSI, and the faults related to the switch logic. In the test button generation for this purpose, it is not necessary to target LSI logic blocks, but bypass lines and switches.
It is easy to create as only gates, switches/latches, and combinational circuits need to be considered.

If it can be guaranteed in advance that there is no failure inside the LSI, then the inspection of this package can be completed, but if not, the pot LSI will be diagnosed one after another. First, L.S.
In order to diagnose I2, a button of "01" is set in the register 6 from the control bin 5. At this time, the decoder 7
Therefore, the control line 8 becomes "1", and 9 and 10 become "10". In other words.

Only LSI 2 is in normal mode, and LSI 3.4 is in through mode, so that internal failures in LSI 2 can be inspected. Tess for this) - i'X, LS in batan generation
The logic block of I2 and the bypass signals and switch gates of LSIs 3 and 4, or if a switch latch is used for LSI 3 or 4, that latch and its LS
Assuming that the combinational circuit between the output edge of I and the switch/latch is connected to the subsequent stage of LSI2, LS
It is only necessary to determine a test pattern for I2, and it becomes possible to easily generate a button having almost the same detection rate in a processing time that is not much different from that for generating a button for LSI 2 alone.

Similarly, by resetting the address using the control circuit 15, it is possible to test LSI 3.4 as well.

In this case as well, test button generation is easy to control and measure IN through other LSIs that are in through mode.
It is possible to achieve the same processing time and detection rate as for bang generation using I alone.

As explained above, in the bypass method of the present invention, the button is set (scanned in) on the partial Iol path for each test, which is necessary in the conventional scan method, and then
There is no need to advance the clock, latch the output of the partial circuit, and retrieve the value (scan out). Therefore, there is no need to consider clock control between latches to ensure that the scan-in/out function is executed normally. Furthermore, since there is no need to scan in and out for each test, test time can be shortened.

Although the present invention has been specifically explained above using one embodiment thereof, the present invention is not limited to this embodiment and can be applied to, for example, the following cases. (1) The hierarchy of the target circuit is not limited to packages and LSIs, and can be expanded vertically. For example, L
It is also possible to further divide the SI into blocks and select each block.

This LSIP 3 requires registers and decoders. (2) The selection of the normal mode does not have to be limited to one partial circuit, but can be performed for a plurality of circuits at the same time. At this time, it is necessary to change the configuration of the register and decoder as necessary.

The configuration and operation of the present invention have been explained above, and the effect of the present invention is that diagnostic performance can be improved by using the bypass function sound without using scan/in/at.
This has the effect of avoiding the complexity of clock control associated with the scan method and reducing test time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an easy-to-diagnose logic circuit according to the present invention, FIGS. 2 and 6 show the structure of a partial circuit included in the wjJ1 diagram, and FIG. The configurations of the switches and gates used in each are shown. FIG. 7 shows the configuration of the switch/latch used in FIG. 6. FIGS. 4 and 5 show how to connect the bypass line between the input edge and the output edge. 1...Package, 2-4...LSI, 6...Register, 7...F coder, 81-82...Bypass, 83゜84.112,113...Switch gate , 83°86...Switch latch, 5.52...
Control bins, 11-20...Input edge pins, 31-
4o...Exit 1 Figure 6 (2) 7th exit

Claims (1)

[Claims] 1. A control pin and a decoder for addressing the partial circuit and selecting normal mode and through mode; A gate with a switch that can select a signal, and a latch that is operated by the signal from the previous stage logic in normal mode and performs set and reset operations only by the signal bypassed from the previous stage logic in through mode. Logic circuit with circuit.