JP2002082146A - Scan test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scan test circuit, in which the controllability of the input terminal of a combination circuit is ensured, while the increase in a circuit scale is suppressed to a minimum and which can enhance failure detection rate. SOLUTION: The scan test circuit is provided with a plurality of data selectors 34, 35, a register group which is constituted of a plurality of latches 23, 24 connected to the respective data selectors, the combination circuit 18 which is connected to the data selectors, a scan chain 10 which is composed of a scan flip-flop circuit constituting a flip-flop circuit as a circuit to be tested and which is connected to the combination circuit, a test enable terminal 27 which changes over a scan test and a normal operation and logic circuits 28, 30 in which enable terminals Es of the latches constituting the register group are always enabled during a scan test period by setting the test enable terminal. The scan test circuit is constituted, in such a way that at least one tatch from among the plurality of latches constituting the register group is replaced by scan flip-flop circuits 13, 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a scan test circuit for improving a fault detection rate in an LSI scan test.

[0002]

2. Description of the Related Art As LSIs become larger and more sophisticated, AS
IC (application Specified IC)
The task of creating test patterns to sort out good and defective products after manufacturing is becoming more complex and difficult, and a high failure detection rate can be achieved by simply diverting the test patterns created by the designer at the time of design for function verification. Is difficult to secure.

Therefore, conventionally, a scan path method has been used as a technique for securing a high failure detection rate. In this scan path method, flip-flops (hereinafter, referred to as “FFs”) inside an LSI are replaced with scan flip-flops (hereinafter, referred to as “scan FFs”), and these scan FFs are serially connected at the time of inspection to form a shift register (scan). In this case, data is written from an input of the scan chain (scan-in), and an input signal is set to a combinational circuit inside the test object. Then, the response of the circuit to the input signal is read in parallel by each FF (parallel capture), the scan chain is shifted, and the response of the circuit is observed from the output of the scan chain (scan out). Since such a test can be performed by a standard procedure, a so-called automatic test pattern generation (ATP)
G: Automatic Test Pattern Generator) to obtain a high failure detection rate.

FIG. 2 is a diagram showing a configuration of a conventional scan test circuit. In FIG. 2, the scan chain 100
Is arranged between the combinational circuits 105 and 106 and is composed of scan FFs 101 and 102. Scan data input terminal SD of first stage scan FF 101
Are connected to the scan-in terminal 103, and the data output terminal Q is connected to the scan data input terminal SD of the second-stage scan FF 102 and the input terminal A of the combination circuit 106. The output terminal Q of the second-stage scan FF 102 is connected to the scan-out terminal 104 and the input terminal B of the combination circuit 106.

The scan enable signal terminal 107 is connected to the scan enable terminals S of the scan FFs 101 and 102.
E is connected. This signal is a signal for switching between the scan shift mode and the parallel capture mode. Here, when the scan enable terminal SE is “0”, the scan FFs 101 and 102 enter the parallel capture mode, in which the data of the data input terminal D is stored and output to the output terminal Q. When the scan enable terminal SE is "1", the scan shift mode is set, and the data at the scan data input terminal SD is stored and output to the output terminal Q.

The external input terminals 108a to 108c are connected to input terminals A to C of the combinational circuit 105, respectively.
The output terminal Y1 is connected to the data input terminal D of the scan FF 101, and the output terminal Y2 is connected to the data input terminal D of the scan FF 102. External output terminal 109
Are connected to the output terminal Y of the combinational circuit 106.
The clock input terminal 110 is connected to the scan FF 10
1 and 102 are connected to the clock terminals.

The latches 111 to 114 used as data registers each have a data input terminal D connected to a register data input terminal 115, and store data input from the register data input terminal 115. The enable terminal E has a decode circuit 11
6 output terminals E0 to E3 and test enable signal terminal 1
17 are connected and controlled via OR gates 118 to 121 as logic circuits, respectively. The test enable signal terminal 117 is a terminal which becomes "0" during normal operation and "1" during test operation. Then, the decode circuit 116 connects the address input terminal AD [1: 0] for selecting the latches 111 to 114 to the address terminal 112,
The write enable input terminal WE is connected to the write enable terminal 123.

Further, two input terminals 0 and 1 of a data selector (hereinafter simply referred to as “selector”) 124 are connected to output terminals Q of latches 111 and 112, respectively. Also, two input terminals 0 and 1 of the selector 125
Are connected to the output terminals Q of the latches 113 and 114. Here, the select signals S of the selectors 124 and 125 are input from another circuit block. When the select signal S is “0”, the selector 124
1 is selected, and when it is '1', the output of the latch 112 is selected. Similarly, the selector 125 selects the output of the latch 113 when the select signal S is “0”,
When 1 ', the output of the latch 114 is selected. And
The output terminals y of the selectors 124 and 125 are connected to the combinational circuit 1
06 are connected to input terminals D and C, respectively.

Next, the operation of the conventional example shown in FIG. 2 during normal operation will be described. First, the operation of the decode circuit 116 will be described with reference to the timing chart of FIG. FIG.
Is a decode circuit 11 of the scan test circuit shown in FIG.
6 is a timing chart for explaining the operation of FIG. 3, the waveforms of AD [1: 0], WE, E0, E1, E2, and E3 indicate the waveforms of the respective terminals of the decoding circuit 116 shown in FIG. 2, and the input signal AD [1: 0] , WE are input in synchronization with the clock signal 110 of FIG. When WE = “1”, the output terminal E0 becomes “1” when AD [1: 0] = “b00”. Similarly, AD [1:
0] = 'b01, the output terminal E1 becomes'1'
When [1: 0] = 'b10, the output terminal E2 becomes'1',
When AD [1: 0] = 'b11 The output terminal E3 is'1'
become. At this time, the test enable signal of the test enable signal terminal 117 shown in FIG. 2 is set to "0", and the values of the outputs E0 to E3 of the decode circuit 116 are directly latched via the OR gates 118 to 121, respectively. ~
Propagate to 114. Thus, the latches 111 to 1
When the 14 enable terminal E is “1”, the data at the register data input terminal 115 is stored in a desired latch.

[0010] Then, the latch 124 is selected by the selector 124.
Either of the outputs 11 or 112 is selected and input to the input terminal D of the combinational circuit 106. Similarly, either one of the outputs of the latches 113 and 114 is selected by the selector 125 and the input terminal C of the combinational circuit 106 is selected.
Is input to Also, during normal operation, the scan enable signal 107 is set to '0',
In F101, the data logically operated by the combination circuit 105 is stored in synchronization with the rise of the clock signal from the clock input terminal 110, and the output is stored in the combination circuit 106.
Is input to the input terminal A. Similarly, the scan FF 102
However, the data logically operated by the combination circuit 105 is stored in synchronization with the rise of the clock signal, and the output is input to the input terminal B of the combination circuit 106. Then, a calculation result corresponding to the input signals A to D of the combination circuit 106 is output to the external output terminal 109.

Next, the test operation of the conventional example shown in FIG. 2 will be described.

First, (1) scan enable terminal 107
Set the scan enable signal to '1'
F101, 102 input to scan data input terminal SD
Set to the side. (2) The shift operation of the scan chain 100 is performed by inputting the system clock from the clock terminal 110, and the scan data as the test vector is transmitted from the scan-in terminal 103 to the all-scan FF 101,
Set to 102. Next, (3) the scan enable terminal SE is set to "0", and the inputs of the scan FFs 101 and 102 are set to the data input terminal D side. (4) Input terminals (115, 117, 122, 123, 108a, 108
b, 108c), a test pattern is input, and the response of the combinational circuit 105 is taken into the scan FFs 101 and 102. At the same time, the output of the combinational circuit 106 is connected to the external output terminal 10.
Observe at 9 and compare with the expected value of the test pattern.

Next, (5) the scan enable signal of the scan enable signal terminal 107 is set to "1", and the inputs of the scan FFs 101 and 102 are set to the scan data input terminal SD side. And (6) clock terminal 110
Scan chain 1 by inputting the system clock from
00, the internal state of the scan chain 100 is observed from the scan-out terminal 104 and compared with the expected value of the test vector. At the same time, scan data as a test vector is set in all scan FFs from the scan-in terminal 103. A test operation is performed by repeating the above operations (1) to (6).

However, at this time, the test enable signal terminal 117 of FIG. 2 is set to "1", and the enable terminals E of the latches 111 to 114 are always set to "1" through the OR gates 118 to 121. The data at the register data input terminal 115 propagates to the outputs of the latches 111 to 114 as the same data. Here, the latches 111 to 111
The purpose of keeping 114 in a state of always propagating data is
Latches 111-114 during test operation due to PG restrictions
As a combinational circuit (buffer).

Then, the latch 124 is selected by the selector 124.
Either of the outputs 11 or 112 is selected and input to the input terminal D of the combinational circuit 106. Here, since the data of the register data input terminal 115 is directly propagated to the outputs of the latches 111 and 112, the selector 1
The output Y at 24 is independent of signals from other blocks entering the select terminal S. That is, the output of the selector 124 is equivalent to the data of the register data input terminal 115. Similarly, the output of the selector 125 becomes equivalent to the data of the register data input terminal 115. As a result, the same value (the value of the data at the register data input terminal 115) is input to the input terminals C and D of the combinational circuit 106.

[0016]

As described above, in the conventional example shown in FIG.
The same value is input to the input terminals C and D, which significantly limits the number of combinations of input values of the input terminals A to D, making it difficult to secure a high failure detection rate. . For example, FIG.
Shows a simple combinational circuit. FIG. 4 is a diagram showing a configuration example of the combinational circuit shown in FIG.

The terminals A to D and the terminal Y in FIG. 4 correspond to the input terminals A to D and the output terminal Y of the combination circuit 106 in FIG. In the AND gate 150, the input terminal a is connected to the terminal A, the input terminal b is connected to the terminal B, and the output terminal Y is connected to the input terminal a of the AND gate 151. Also,
The EXOR gate 152 has an input terminal a connected to the terminal C, an input terminal b connected to the terminal D, and an output terminal y connected to the input terminal b of the AND gate 151. The output y of the AND gate 151 is connected to the terminal Y.

In this circuit, the terminals C,
D is given the same value during the test operation.
The stuck-at fault of the input terminal a of the OR gate 152 is “0”, the terminal C is “1”, the terminal D is “0”, and both the terminals A and B are
It cannot be set to '1' and propagated to the output terminal Y for detection. Similarly, the input terminal b of the EXOR gate 152
Terminal C to '0' and terminal D to '0'
1 'and terminals A and B are both set to' 1 'and output terminal Y
And cannot be detected.

Further, the output terminal y of the EXOR gate 152
And the input terminal b of the AND gate 151 is always set to "0", so that both terminals A and B are set to "1" and the
Even if the input terminal a of the D gate 151 is set to '1',
The "0" stuck-at fault at the output terminal y of the XOR gate 152 and the "0" stuck-at fault at the input terminal b of the AND gate 151 cannot be detected, and the output terminal y of the AND gate 151 is always "0". Therefore, the stuck-at '0' cannot be detected.

Further, in order to detect a stuck-at fault in the input / output terminal of the AND gate 150 and the input terminal a of the AND gate 151, the input terminal b of the AND gate 151 must be connected to the input terminal b.
Although it is necessary to set it to 1 ', these failures cannot be detected because of the above-mentioned reason. As a method of detecting these undetectable faults, a method is considered in which all of the latches 111 to 114 in FIG. 2 are replaced with scan FFs to improve controllability in addition to the scan chain. Since the circuit scale is usually about twice as large, an increase in circuit scale cannot be avoided.

FIG. 5 is a diagram showing the configuration of a conventional scan test circuit when the register group is composed of 50 latches.

As shown in FIG. 5, the scan test circuit comprises:
The selectors SL1 and SL2 are connected to 50 latches L1-0 to L1-49 and L2-0 to L2-49, respectively, forming a shift register group. As described above, as the number of latches constituting the register group increases, replacing all the latches with the scan FFs increases the circuit scale and is not practical. In particular, in the case of a digital signal processing LSI, since the ratio of the data register to the entire circuit is large, the increase in the circuit scale when switching to the latch scan FF is more remarkable.

The present invention has been made in view of the above points, and it is possible to secure the controllability of the input terminals of a combinational circuit while minimizing the increase in circuit scale, and to improve the fault detection rate. It is an object to provide a simple scan test circuit.

[0024]

To achieve the above object, a scan test circuit according to claim 1 of the present invention comprises:
A plurality of data sectors, a register group including a plurality of latches connected to the respective data selectors, a combinational circuit connected to the data selectors, and a scan flip-flop circuit forming a flip-flop circuit of the circuit under test. A scan chain connected to the combinational circuit, a test enable terminal for switching between a scan test and a normal operation, and an enable terminal of a latch constituting the register group, which are always enabled during a scan test period by setting the test enable terminal. In a scan test circuit including a logic circuit, at least one of a plurality of latches constituting the register group is replaced with a scan flip-flop circuit.

The scan test circuit according to claim 2 is
2. The scan test circuit according to claim 1, wherein the logic circuit connected to a scan flip-flop circuit forming the register group among the logic circuits is a composite gate.

The scan test circuit according to claim 3 is:
3. The scan test circuit according to claim 2, wherein the composite gate is an AND-OR composite gate.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a scan test circuit according to the present invention. In the figure, a scan chain 10 is arranged between a combinational circuit 17 and a combinational circuit 18 and includes scan FFs 11, 12, 13, and 14. The scan data input terminal SD of the first-stage scan FF 11 is connected to the scan-in terminal 15, and the data output terminal Q is connected to the second-stage scan FF 1
2 and the input terminal A of the combinational circuit 18. The data output terminal Q of the second-stage scan FF 12 is connected to the third-stage scan FF.
13 scan data input terminal SD and combination circuit 18
The data output terminal Q of the third-stage scan FF 13 is connected to the scan data input terminal SD of the fourth-stage scan FF 14, the selector 35 and the AND-O.
The scan FF 1 of the fourth stage connected to the R composite gate 31
4 is a data output terminal Q,
It is connected to a selector 34 and an AND-OR composite gate 29 as a logic circuit.

The scan enable signal terminal 19 is connected to each of the scan enable terminals SE of the scan FFs 11, 12, 13, and 14, respectively. The scan enable signal is a signal for switching between the scan shift mode and the parallel capture mode. Here, scan FF
11, 12, 13, and 14 are scan enable terminals S
When E is '0', the mode is the parallel capture mode, the data at the data input terminal D is stored and output to the output terminal Q, and when '1', the mode is the scan shift mode and the data at the scan data input terminal SD is It is stored and output to the output terminal Q.

The input terminals A to C of the combination circuit 17 are connected to external input terminals 20a to 20c, respectively, the output terminal Y1 is connected to the data input terminal D of the scan FF 11, and the output terminal Y2 is connected to the scan FF 12 Is connected to the data input terminal D of The external connection terminal 21 is connected to the output terminal Y of the combination circuit 18. The clock input terminal 22 is connected to the scan FFs 11, 12, 13, 1
4 is connected to each clock terminal.

Latch 2 used as data register
Each of the data input terminals 3 and 24 has the data input terminal D connected to the register data input terminal 25, and stores data input from the terminal 25. Output terminals E0, E of the decode circuit 26 are connected to enable terminals E of the latches 23, 24, respectively.
2 and a test enable signal terminal 27 are OR gates 28,
30 are connected and controlled respectively. The enable signal of the test enable signal terminal 27 is a terminal which becomes "0" during normal operation and "1" during test operation.

The scan FFs 13 and 14 are also used as data registers, and each data input terminal D is connected to A
It is connected to the register data input terminal 25 via the ND-OR composite gates 29 and 30. These AND-O
The R composite gates 29 and 30 are connected to output terminals E1 and E3 of the decode circuit 26, respectively, and are controlled. The decode circuit 26 includes latches 23 and 24 and a scan FF
Address input terminal A [1:
0] is connected to the address terminal 32, and the write enable input terminal WE is connected to the write enable terminal 33.

The two inputs of the selector 34 are connected to the latch 23
And two inputs of the selector 35 are connected to the latch 24 and the scan FF 14, respectively.
It is connected to the output terminal Q of F13. Here, the select signals S of the selectors 34 and 35 are input from another circuit block, and the selector 34
Is '0', the output of the latch 23 is selected, and when '1', the output of the scan FF 14 is selected. Similarly, when the select signal S is “0”, the selector 35
Is selected, and when it is “1”, the output of the scan FF 13 is selected. The output terminals Y of the selectors 34 and 35 are connected to the input terminals D and C of the combinational circuit 18, respectively.

The operation of the scan test circuit during normal operation will be described below.

First, the operation of the decoding circuit 26 and the input timing of the input signals AD [1: 0] and WE are the same as those of the decoding circuit 116 in FIG. 2, and AD [1: 0] = 'b00
In this case, the output terminal E0 becomes '1'. Similarly, AD [1: 0]
= 'B01', the output terminal E1 goes to '1' and AD [1: 0] =
In the case of 'b10, the output terminal E2 becomes' 1 'and AD [1: 0] =' b
In the case of 11, the output terminal E3 becomes '1'. At this time, the enable signal of the test enable signal terminal 27 in FIG. 1 is set to “0”, and the outputs E0 and E2 of the decode circuit 26 are directly sent to the latches 23 and 24 via OR gates 28 and 30, respectively. Propagate. And latches 23, 2
When the enable terminal E of No. 4 is "1", data of the register input terminal 25 is stored in a desired latch.

The output E1 of the decoding circuit 26 is
When the value is 1 ', the AND-OR composite gate 29 is set to a mode in which the data at the register data input terminal 25 is propagated to the scan FF 14, and the scan FF 14 at the rising edge of the next clock signal input from the clock input terminal 22. The data is stored in At the same time, when the output E3 of the decode circuit 26 is “1”, the AND-OR composite gate 31 enters a mode in which the data of the register input terminal 25 is propagated to the scan FF 13 and scans at the next rising edge of the clock signal. Data is stored in the FF 13.

The selector 34 controls the latch 23
Alternatively, one of the outputs of the scan FF 14 is selected and input to the input terminal D of the combinational circuit 18. At the same time, either the output of the latch 24 or the output of the scan FF 13 is selected by the selector 35 and input to the input terminal C of the combination circuit 18.

In the normal operation, the scan enable signal of the scan enable signal terminal 19 is set to "0". Therefore, in the scan FF 11, the data logically operated by the combination circuit 17 is synchronized with the rising of the clock signal. The output is input to the input terminal A of the combinational circuit 18. Similarly, in the scan FF 12, the data logically operated by the combination circuit 17 is stored in synchronization with the rise of the clock signal, and the output is input to the input terminal B of the combination circuit 18. Then, a calculation result corresponding to the input signals A to D of the combination circuit 18 is output to the external output terminal 21.

Next, the operation during the test operation will be described.

First, (1) scan enable signal terminal 1
9 is set to "1", and the inputs of the scan FFs 11, 12, 13, and 14 are set to the scan data input terminal SD side. (2) The shift operation of the scan chain 10 is performed by inputting the system clock from the clock terminal 22, and the scan data as the test vector is transferred from the scan-in terminal 15 to the full scan F
Set to F. Next, (3) scan enable terminal 19
Is set to “0”, and the inputs of the scan FFs 11, 12, 13, and 14 are set to the data input terminal D side. (4) Input terminals (25, 2
7, 33, 20a, 20b, 20c), and inputs the test patterns from the circuits in all stages of each scan FF, such as the combinational circuit 17, to the scan FFs 11, 12, 13, 1
Take in 4. At the same time, the output of the combinational circuit 18 is observed at the external output terminal 21 and compared with the expected value of the test pattern. Next, (5) the scan enable signal is set to "1", and the inputs of the scan FFs 11, 12, 13, and 14 are set to the scan data input terminal SD side. (6) The shift operation of the scan chain 10 is performed by inputting the system clock from the clock terminal 22, the internal state of the scan chain 10 is observed from the scan out terminal 16, and compared with the expected value of the test vector. At the same time, scan data, which is a test vector, is set from the scan-in terminal 15 to all the scan FFs 11 to 14. (1) to (6) above
The test is performed by repeating the above operation.

However, at this time, the enable signal input from the test enable signal terminal 27 in FIG. 1 is set to "1", and the enable terminals E of the latches 23 and 24 are always set to "1" through the OR gates 28 and 30. 1 'and the data at the register data input terminal 25
Propagated as the same data to the outputs of 3, 24. here,
The purpose of keeping the latches 23 and 24 in a state where data is always propagated is to prevent the latches 2 and 24 from operating during the test operation due to ATPG restrictions.
This is because 3 and 24 are handled as a combinational circuit (buffer).

The selector 34 operates the latch 23.
Alternatively, one of the outputs of the scan FF 14 is selected and input to the input terminal D of the combinational circuit 18. Either the latch 24 or the output of the scan FF 13 is selected by the selector 35 and input to the input terminal C of the combinational circuit 18.

At this time, the select signal S of the selector 34
Is' 0 'and the select signal S of the selector 35 is'
When the value is 0 ', the output of the latch 23 and the output of the latch 24, which are the same as the data of the register data input terminal 25, are input to the input terminals D and C of the combinational circuit 18, respectively. Will be severely restricted. However, the select signal S of the selector 34
Is “1” and the select signal S of the selector 35 is “
1 ′, the output of the scan FF 14 and the scan F
The output of F13 is input to the input terminals D and C of the combinational circuit 18 respectively, and the scan FF 14 and the scan FF 13
Is set to a desired value using the scan chain 10, it is possible to secure a high failure detection rate without limiting the number of combinations of the input values of the input terminals A to D of the combinational circuit 18. Become.

This effect will be described with reference to the combination circuit of FIG.

The input terminals A to D and the output terminal Y in FIG. 4 correspond to the input terminals A to D and the output terminal Y of the combinational circuit 18 in FIG. Other components and connections are the same as those described above. It is also assumed that a signal is given from another block so that the select signal S of the selector 34 is “1” and the select signal S of the selector 35 is “1”.

In this combinational circuit, a stuck-at-fault at the input terminal a of the EXOR gate 152 is "0",
1 ', terminal D to' 0 ', terminals A and B both to' 1 '
The value can be propagated to the terminal Y and detected. At the same time, when the stuck-at fault of the input terminal b of the EXOR gate 152 is “0”, the terminal C is set to “0” and the terminal D
Is set to '1' and both terminals A and B are set to '1', whereby the value can be propagated to terminal Y and detected.

The output terminal y of the EXOR gate 152
And the value of the input terminal b of the AND gate 151 is the terminal C,
D is set to “1” by setting only one of D to “1”, so that both the terminals A and B of the AND gate 150 are set to “1” and the input terminal a of the AND gate 151 is set to “1”. If set to '1', EXOR gate 152
'0' stuck-at fault at output terminal y of AND gate 15
"0" stuck-at fault of the input terminal b of 1 can be detected. Furthermore,
'0' stuck-at fault at the output terminal y of the AND gate 151 can be detected at the same time.

As described above, the AND gate 15
Since the input terminal b of No. 1 can be set to “1”, if the terminals A and B are set to desired values, it is possible to detect the stuck-at fault of the input terminal a of the AND gate 150. . Other stuck-at faults can also be detected by setting the terminals A to D to desired values.

[0049]

As described above, according to the first aspect of the present invention, a combination circuit in which a plurality of data sectors, a register group including a plurality of latches connected to each data selector, and the data selector are connected. A scan chain composed of a scan flip-flop circuit constituting a flip-flop circuit of the circuit under test and connected to the combinational circuit; a test enable terminal for switching between a scan test and a normal operation; and an enable of a latch constituting the register group A logic circuit for enabling a terminal to be always enabled during a scan test period by setting the test enable terminal, wherein at least one of a plurality of latches constituting the register group is a scan flip-flop. Scan chains using circuits By doing so, it is possible to secure the controllability of the input terminals of the combinational circuit and improve the fault detection rate while minimizing the increase in the circuit scale, and the number of latches constituting the register group is large. It is more effective than the case, especially in the case of LSI for digital signal processing.
Since the ratio of the data register to the entire circuit is large, the effect is extremely large.

According to the second and third aspects of the present invention, the logic circuit connected to the scan flip-flop circuit forming the register group is constituted by an AND-OR composite gate, thereby simplifying the circuit structure.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a scan test circuit according to the present invention.

FIG. 2 is a diagram showing a configuration of a conventional scan test circuit.

FIG. 3 is a timing chart for explaining the operation of the decoder circuit of the scan test circuit shown in FIG.

FIG. 4 is a diagram illustrating a configuration example of the combinational circuit illustrated in FIG. 2;

FIG. 5 is a diagram showing a configuration of a conventional scan test circuit when a register group is composed of 50 latches.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Scan chain 11-14 Scan flip-flop circuit 16 Scan-out terminal 17, 18 Combination circuit 19 Scan enable signal terminal 20a-20c External input terminal 21 External output terminal 22 Clock input terminal 23, 24 Latch 25 Register data input terminal 28, 30 OR gate (logic circuit) 29, 31 AND-OR composite gate (logic circuit) 26 decode circuit 27 test enable terminal 32 address terminal 33 write enable terminal 34, 35 selector

Claims (3)

[Claims] A plurality of data sectors; a register group including a plurality of latches connected to the data selectors; a combinational circuit connected to the data selectors; and a scan flip-flop constituting a flip-flop circuit of a circuit under test. A scan chain composed of a latch circuit and connected to the combinational circuit, a test enable terminal for switching between a scan test and a normal operation, and an enable terminal of a latch constituting the register group are always set during the scan test period by setting the test enable terminal. A scan test circuit comprising a logic circuit for enabling, wherein at least one of a plurality of latches constituting the register group is replaced with a scan flip-flop circuit. 2. The scan test circuit according to claim 1, wherein, among the logic circuits, the logic circuit connected to a scan flip-flop circuit forming the register group is a composite gate. 3. The scan test circuit according to claim 2, wherein the composite gate is an AND-OR composite gate.