JPS61180156A - Inspection system for logical circuit - Google Patents

Abstract

PURPOSE:To evade in-phase transfer without increasing any system delay by adding a selecting mechanism which inputs system data or scan data during the transmission of a scan clock according to the mode to an output-side FF which is put in an in-phase state. CONSTITUTION:The system clock 2 and system data 3 are signals for normal operation control and scan data 4, the scan clock 5, and a scan address 6 are used only during inspection. A combinational circuit 10 consists of input FF groups 11-14 and output FF groups 15 and 16. When the system clock of an aimed FF is in phase with the system clock of the FF as its front stage, the selecting mechanism for the system data and scan data is provided so as to stored the system data without sending out the system clock to the aimed FF, thereby storing the system data by sending out the scan clock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a testing method for digital logic circuits, and particularly to a testing method using a scan bus.

[Background of the invention]

In order to improve the testability of large-scale logic circuits, a method is used that adds a scan bus to an existing circuit and divides a complex, large-scale sequential circuit into simple, small-scale combinational circuits. An example is shown below.

By assigning a unique scan address to every flip-flop in a logic circuit and selecting the address, scan-in/scan-out can be easily performed for any flip-flop. In such logic circuits, by repeating the following procedure for all test patterns for each combinational circuit surrounded by flip-flops,
Can be inspected.

(1) Scan in the test pattern to the input side blip prop of the combinational circuit.

(2) Send the system clock to the output side flip-flop and take in the system data that is the output of the combinational circuit.

(3) The data taken in from the output side flip-flop is scanned out and compared with the previously determined expected value.

Several logic design constraints are typically imposed to ensure that such testing schemes operate reliably.

One of them is, for example, 1977 DAC, 462-46
8“A Logic Design 5tructar
In other words, the system clocks of the input side flip-flop and the output side flip-flop are prohibited from being in the same phase.The reason for this is shown below.

The flip-flop used here is data through when the pulse is on. If the value of the system data of the input flip-flop is different from the value scanned in in step (1) above, the value scanned in is destroyed when the system clock is sent in step (2). This effect may propagate to the output flip-flop, and in this case, the system clock of the output flip-flop is
This is because if it is in the N state, the value of the output side flip-flop will also change, and there is a risk that it will not match the expected value.

This is because the pulse width of the system clock used during inspection is longer than the pulse width of the system clock during actual operation.

Normally, the pulse width of the system clock is short, so there is no problem because the pulse ends before the influence propagates from the input side to the output side.

In a circuit that involves in-phase transfer, stable operation cannot be guaranteed during testing as described above, resulting in a decrease in the detection rate of test data. In order to avoid this, it is necessary to change the logic to prevent in-phase transfer, and change the conventional flip-flop to a master-slave configuration.
Various techniques have been used, such as (2) using a delay latch, and (2) fixing the system clock of the input flip-flop in the OFF state when transmitting the system clock. However, all of these methods have the drawback of increasing system delay and reducing the operating speed of the logic circuit.

[Purpose of the invention]

The present invention aims to eliminate this drawback and provides a test scheme that makes it possible to avoid in-phase transfer without increasing system delay.

[Summary of the invention]

In other words, depending on the mode when the scan clock is sent to the output side flip-flops that are in the same phase,
Add a selection mechanism to capture either system data or scan data. It is assumed that scan data is captured in the first mode and system data is captured in the second mode. As a result, in the second mode, by selecting the address of the output side flip-flop and sending out the scan clock, it is possible to take system data into the output side flip-flop without sending out the system clock. Become. On the other hand, the system clock for the input side flip-flop group remains unchanged,
Also, although the scan clock changes, since its own address is not selected, its influence is not transmitted, and the previously scanned-in value can be retained. In other words, the change in the value of the input flip-flop, which was a problem with conventional in-phase transfer, does not occur, and therefore the risk of the value of the output flip-flop changing can be avoided, and stable operation can be guaranteed.

The system data and scan data selection mechanism described above can be implemented without introducing any new elements on the system clock and system data signal paths during normal operation.

As described above, in-phase transfer can be handled without increasing system delay, and stable operation can be guaranteed during testing.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the entire circuit targeted by the inspection method using such a scan path.

1 is the entire circuit such as LSI and package. 2 is a system clock signal, and 3 is a system data signal, which are originally signals for normal operation control. 4 is a scan data signal that sets data for scan-in, 5 is a scan clock signal that activates scan-in, and 6 is a scan address signal that selects a flip-flop, and these are used only during inspection. used. 7 is an output data signal during normal operation, and 8 is an output signal during scan out. 10 is an example of a combinational circuit surrounded by flip-flops. 11 to 14 indicate input flip-flop groups, and 15 to 16 indicate output flip-flop groups. 17 is a scan address decoder, and 18 is a decoded signal, which corresponds one-to-one to each flip-flop in the circuit. This decode signal and the scan clock are ANDed at gate G1,
It is supplied to the SC terminal of the flip-flop.

Further, the output of the flip-flop and the decoded signal are ANDed at gate G2, further ORed at gate G5, and outputted from the scan out bin. The symbols T0 to T shown for each flip-flop indicate the type of system clock. That is, in this example, the system clocks of the input flip-flop 12 and the output flip-flop 16 are both T□ and in phase.

Figures 2 and 3 show an example of a flip-flop with 6 input terminals, C, and SD.
are system data 21° and system clock 22. Connected to scan data 4. Scan clock 5 and address decode signal 18 are ANDed at gate 23 and connected to input terminal SC. Q and Q are output terminals. The operation specification 31 indicates that if the clock terminals C and SC are both 0, the flip-flop does not operate and the previous value is held. Operation specification 32 corresponds to normal logical operation and indicates that system data is captured when the system clock is asserted. Operation specification 33 corresponds to scan-in operation, and the address of the flip-flop is selected and the scan/in operation is performed.
It shows that scan data is captured when the clock is sent out.

If in-phase transfer exists with the circuit configuration shown above, the data scanned in in advance to the input flip-flops may be destroyed when the in-phase system clock is sent out. There is a danger that the data may be captured by the Therefore, the following measures will be taken.

As shown in FIG. 4, a test mode signal M41, an AND gate 42, and an OR gate 43 are added to the output flip-flop 16 which is in phase. FIG. 5 shows the operational specifications of the flip-flop modified in this way. When the inspection mode signal M=O, the operation is exactly the same as the conventional one. In other words, the operation specifications 51 to 53 are respectively 31 in FIG.
It corresponds to ~33. The operation specification 54 sets the inspection mode M to 1. When the scan data SI is set to O and the address of the flip-flop is selected, by sending the scan clock instead of the system clock,
Indicates that system data can be captured. By using this operation mode, it is possible to take measures against in-phase transfer. The inspection procedure for the following will be explained.

FIG. 6 shows the testing procedure in the present invention.

In process 100, the inspection mode is first set to O.

Process 110 is a scan-in operation, which is the same as the conventional method. Process 120 issues the system clock and captures system data to the output flip-flop. At this time, all systems of output flip-flops
It differs from the conventional method in that it does not transmit a clock, but excludes system clocks that are in phase. In other words,
In the example of FIG. 1, only the To clock is sent. Processing 13
0 sets the inspection mode to 1. Set scan data to O. Process 140 is a scan out operation.

The difference from the conventional method is that in process 120, a scan clock is sent to the in-phase flip-flops to which the system clock was not sent.

Compare the value scanned out in process 150 with the expected value,
Determine whether there is a failure. The above-described processes 100 to 150 are repeated for all test patterns of the combinational circuit, and after completion, the same process is repeated for the next combinational circuit.

In the above inspection method, the input flip-flop system
Since there is no need to send out a clock, it is possible to avoid data corruption in the input flip-flop in the in-phase transfer circuit, which has been a problem with conventional testing methods, and stable operation can be guaranteed.

The point to note here is the inspection method for the hard core. In the test method using the scan circuit described above, the scan circuit is the hard core, and it is necessary to test in advance whether or not this scan circuit operates normally. Output and check the operation (this is called an O-cycle test). The selection mechanism added for in-phase countermeasures in the present invention becomes a new hard core. In addition, since the system clock is not operated during testing for flip-flops with common-mode measures,
During the 0-cycle test, it is necessary to confirm in advance that the system data is correctly captured by the system clock.

In consideration of the above, in the present invention, an O-cycle test is performed according to the procedure shown in FIG. Processes 200, 210 are equivalent to a conventional 0 cycle test. At this time, inspection mode M=
Let it be O. Processes 220 to 290 are newly required processes, and are repeated only for flip-flops for which in-phase measures have been taken. First, in process 220, O is scanned in in advance and the value of the flip-flop is determined to be 0. Next, in process 230, the system clock is sent and system data is captured. Process 240 then uses the scan clock to capture system data. Processing 230.2
The values scanned out in step 40 are compared in step 250. Next, 1 is scanned in in process 260, and similar processes are performed in 270 to 290. Processing 250. If the comparison results in process 290 match, it can be considered that both the flip-flop selection mechanism and the system data acquisition mechanism using the system clock are operating normally. After completing the O-cycle test shown above, one entire circuit can be tested by testing according to the procedure shown in FIG.

〔Effect of the invention〕

The configuration and operation of the present invention have been described above. Second
As is clear from the comparison between Figure 3 and Figure 3, there are no new gates added to the system data and system clock signal paths during normal operation, and therefore the system delay during normal operation is There has been no increase at all.

That is, according to the present invention, a means for testing a circuit including in-phase transfer in a stable state can be provided without increasing the system delay, so that the operating speed of the circuit can be improved compared to the conventional method.

[Brief explanation of the drawing]

Fig. 1 is an overall configuration diagram of the circuit targeted by the present invention, Figs. 2 and 3 are operation definition diagrams showing an example of a flip-flop used therein, and Figs. 4 and 5 are as described above. An additional circuit diagram for common-mode countermeasures for the flip-flop and its operation definition diagram. Figure 6 is a flow chart showing the test procedure for the above circuit. Figure 7 is performed prior to the test in Figure 6. 2 is a flow chart of a 0 cycle test. 10... Combinational circuit to be tested, 11-14... Input flip-flop group, 15-16... Output flip-flop group, 31-33... Operation specifications of flip-flops before countermeasures, 51-54. ...Flip-flop operation specifications after countermeasures, 100-150...Inspection procedures, 200
~290...0 cycle test inspection procedure. %Z Figure 2θ Figure 3χ do't ctret, ρart z: ttris 4th Figure Zθ Atsushi 5 Figure m'it/l negation - ■ 6 Figure 7 Figure Procedure Amendment (Method) Showa 6 To 6FJ1

Claims (1)

[Claims] Inspection is performed by setting a unique scan address for every flip-flop in a logic circuit, storing scan data for the flip-flop specified by the address, and retrieving the scan data from the next stage flip-flop. In the logic circuit testing method to be performed, if the system clock of the flip-flop of interest and the system clock of the flip-flop in the preceding stage of the flip-flop of interest are in phase, the system clock is sent to the flip-flop of interest. In order to store system data without transmitting it, it has a selection mechanism for system data and scan data, and by making it possible to store system data by transmitting the scan clock, it ensures stable operation during inspection. A logic circuit inspection method characterized by: