JP2010122009A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for facilitating a test. <P>SOLUTION: A latch 40 with a through mode includes first and second latches 41, 42, an AND gate 43 and an OR gate 44, and is provided between a first combination logic circuit 22_1 and a second combination logic circuit 22_2 which constitute a combination logic circuit 22. When the latch 40 with the through mode is operated in a normal mode, data are inputted from the first combination logic circuit 22_1, passes therethrough, and is outputted to the second combination logic circuit 22_2. When the latch with the through mode is operated in a test mode, a scan chain is formed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including a plurality of flip-flops and a combinational logic circuit.

  2. Description of the Related Art Conventionally, a test using a scan test method has been widely used for testing a combinational logic circuit provided in a semiconductor integrated circuit. In a semiconductor integrated circuit to be tested by the scan test method, a plurality of flip-flops are connected in series to form a scan chain, and serial data (test pattern) is given to the combinational logic circuit to operate the combinational logic circuit. Built-in scan test circuit to test. In the scan test method, serial data is input from the tester to the scan chain that constitutes the scan test circuit, and the logic state of the serial data output to the observation terminal via the combinational logic circuit is observed on the tester side. As a result, whether the function and operation of the combinational logic circuit provided in the semiconductor integrated circuit is good or bad is determined.

  FIG. 4 is a diagram showing a circuit configuration of a conventional semiconductor integrated circuit employing a scan test method, and FIG. 5 is a diagram showing a circuit configuration of the flip-flop shown in FIG.

  The semiconductor integrated circuit 100 shown in FIG. 4 has a pipeline configuration in which flip-flops 101, 102, 103, and 104 and combinational logic circuits 111, 112, 113, 114, 115, and 116 are alternately connected.

  First, the circuit configuration of the flip-flops 101, 102, 103, and 104 will be described with reference to FIG. Although only the circuit configuration of the flip-flop 101 will be described here, the circuit configurations of the other flip-flops 102, 103, and 104 are the same as the circuit configuration of the flip-flop 101 shown in FIG.

  The flip-flop 101 shown in FIG. 5 includes a selector 101a and a built-in flip-flop 101b.

  The selector 101a includes a data terminal D to which data D from the combinational logic circuit 111 shown in FIG. 4 is input, a scan data terminal SD to which scan data (shift data) SD from a combinational logic circuit (not shown) is input, and a scan And a scan enable signal terminal SE to which the enable signal SE is input. In the selector 101a, when the 'L' level is input to the scan enable signal terminal SE, the data D from the data terminal D is output. On the other hand, when the “H” level is input to the scan enable signal terminal SE, the scan data SD is output from the scan data terminal SD.

  The built-in flip-flop 101b has a data terminal D to which data from the selector 101a is input, a clock terminal CK to which the clock signal CLK is input, and a data terminal Q to which data Q is output. In the built-in flip-flop 101b, the data input to the data terminal D is held at the timing of the clock edge of the clock signal CLK, and the held data is output from the data terminal Q. Returning again to FIG. 4, the description will be continued.

  In the semiconductor integrated circuit 100 shown in FIG. 4, during normal operation, the scan enable signal SE is set to the “L” level, and the scan enable signal terminals SE of the flip-flops 101, 102, 103, and 104 are set to the “L” level. Is entered. The flip-flops 101, 102, 103, and 104 hold the data D from the combinational logic circuits 111, 112, 114, and 116 at the timing of the clock edge of the clock signal CLK. The held data Q is output from the data terminal Q of the flip-flops 101, 102, 103, 104.

  On the other hand, during the scan test operation, the shift mode is first set. In this shift mode, the scan enable signal SE becomes ‘H’ level, and the scan enable signal terminals SE of the flip-flops 101 to 104 also become ‘H’ level. As a result, the flip-flops 101 to 104 are chain-connected in the order of 101 → 103 → 102 → 104. In this state, the clock signal CLK is supplied to each flip-flop 101-104. Accordingly, scan data SD (test data) is input from the flip-flop 101 and shifted in the order of chain connection. That is, first, the first bit of the scan data SD (test data) is held in the flip-flop 101 at the timing of the first clock edge of the clock signal CLK. At the timing of the next edge of the clock signal CLK, the first bit of the scan data SD is moved (shifted) to the flip-flop 103 and held. At the same timing, the flip-flop 101 holds the next bit of the scan data SD. Further, at the timing of the next clock edge, the first bit of the scan data SD is shifted to the flip-flop 102 and held. The flip-flops 101 and 103 each hold the next bit. In this way, by supplying the scan data SD to the first stage flip-flop connected in a chain while the scan enable signal SE is set to the “H” level, and supplying the clock signal CLK only for a predetermined period, Each of the chain-connected flip-flops can hold test scan data. The scan data held in each flip-flop is input to a combinational logic circuit connected to the Q output of each flip-flop. In each combinational logic circuit, a predetermined test logic operation is performed by the input scan data SD.

  Next, the shift mode is switched to the capture mode, and the scan enable signal SE changes from the ‘H’ level to the ‘L’ level only for one period of the clock signal CLK. For this reason, the scan enable signal terminal SE of the flip-flop 102 is also set to the “L” level, and the data from the combinational logic circuit connected to each D terminal is connected to each flip-flop at the timing of the clock edge of the clock signal CLK. (Test result) is retained.

  Further, the capture mode is switched to the shift mode again, and the scan enable signal SE changes from the “L” level to the “H” level. In this state, by supplying the clock signal CLK only for a predetermined period, the test results held in the respective flip-flops move (shift) in the chain-connected flip-flops, and in turn, the flip-flop 104 The data is output as data OUT from the observation terminal 12 connected to the data terminal Q. The quality of the combinational logic circuit provided in the semiconductor integrated circuit 100 is determined by comparing the data OUT with the expected value.

  However, in the test by the scan test method, it is difficult to detect a fault in a deep logic path of a combinational logic circuit having a large circuit scale, that is, a portion close to the flip-flop on the output side. That is, if it is a portion close to the input side flip-flop, it is easy to supply data suitable for failure detection by inputting scan data from the input side flip-flop. However, the scan data input from the flip-flop is supplied to the portion close to the flip-flop on the output side after being complicatedly changed by the logic operation of the portion close to the input side of the combinational logic circuit. For this reason, it is difficult to supply data suitable for failure detection.

  Here, as a technique for increasing the fault detection rate of a deep logic path in a combinational logic circuit having a large circuit scale in testing a combinational logic circuit provided in a semiconductor integrated circuit by adopting a scan test method, the following will be described. Two approaches are known.

  The first technique is to increase the number of pipeline divisions, reduce the size of each combinational logic circuit, and reduce the number of logic stages from one flip-flop to the other flip-flop.

The second method is a method in which a dedicated observation flip-flop is connected to an arbitrary position in a data path through which data is transmitted. As a technique corresponding to the second technique, for example, in Patent Document 1, a scan circuit group for diagnosis for facilitating diagnosis of a combinational logic circuit is provided and connected to an arbitrary gate output location and exists in the combinational logic circuit. There has been proposed a technique for detecting a failure location that does not go through an output flip-flop group. In addition, for example, Patent Document 2 includes a diagnostic scan flip-flop for reducing the number of test patterns, so that reading of data from the internal circuit is not limited to the flip-flop circuit and can be performed by any logic gate cell. Techniques that can be performed have been proposed.
JP-A-9-264927 Japanese Patent Laid-Open No. 10-223864

  However, in the above-described first method of dividing the pipeline and reducing the number of logic stages between the flip-flops, the number of pipeline stages increases, and therefore it is necessary to perform a scan test corresponding to the increased number of pipelines. Therefore, there is a problem that the test time increases. Further, when the pipeline is divided to reduce the number of logic stages between the flip-flops, there may be a case where a significant logic circuit change occurs.

  In addition, the second method of connecting an observation-specific flip-flop at an arbitrary position in the data path is suitable for detecting a failure in that portion even though the logic close to the flip-flop located on the output side can be observed. The problem that it is difficult to supply data is not solved. Therefore, there is still a problem that it is difficult to detect a failure of logic close to the flip-flop located on the output side.

  SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit that can be easily tested.

The semiconductor integrated circuit of the present invention that achieves the above object is as follows.
A plurality of flip-flops to which a clock signal is supplied and a combinational logic circuit, and the combinational logic circuit between the input-side flip-flop group and the output-side flip-flop group selected from the plurality of flip-flops during normal operation And the data held in the input side flip-flop group at the timing of the clock edge of the clock signal is supplied as input data to the combinational logic circuit and the combinational logic at the timing of the next clock edge of the clock signal. A semiconductor integrated circuit including a synchronous logic circuit that holds output data output from a circuit in the output-side flip-flop group,
Inserted into the combinational logic circuit, the clock signal is supplied and the control signal is supplied. Through the control signal, the input data is passed through and output, and the timing of the edge of the clock signal. It further has a latch with a through mode capable of switching between a latch mode for holding inputted data,
During the normal operation, the latch with the through mode is set as a through mode as a signal path in the combinational logic circuit,
During a test operation, a scan chain is formed by connecting at least a part of the plurality of flip-flops and the latch with through mode in series, and the test data supplied via the scan chain is held in the latch with through mode The held test data is supplied to the combinational logic circuit.

  The semiconductor integrated circuit according to the present invention is in a through mode in which input data is passed through and output during normal operation, and a latch with through mode that forms a scan chain connected in series with at least a part of a plurality of flip-flops during a test operation Is a configuration inserted in a combinational logic circuit. For this reason, there is no increase in the number of pipeline stages during normal operation, and during the test operation, the failure logic of that part is shifted from the latch with through mode to the part of the combinational logic circuit close to the flip-flop located on the output side. It is possible to supply test data suitable for detection. Therefore, the test can be facilitated even when the circuit scale of the combinational logic circuit provided in the semiconductor integrated circuit is large.

Here, the latch with the through mode is
When the clock terminal is at the first level, the input data is passed through and output, the input data is held at the timing when the clock terminal changes from the first level to the second level, and the clock is A first latch that outputs the held data when the terminal is at a second level;
When the clock terminal is at the second level, the input data is passed through and output, and the input data is held at the timing when the clock terminal changes from the second level to the first level. A second latch that outputs the held data when the terminal is at the first level is connected in series, and
The clock signal supplied when the control signal is at a third level is supplied to the clock terminals of the first and second latches, and the first signal is supplied when the control signal is at a fourth level. And a clock signal control circuit for fixing the clock terminal of the latch to the first level and fixing the clock terminal of the second latch to the second level.

  In this way, the latch with through mode can be realized with a simple configuration.

  In addition, a selector to which the control signal is supplied is provided on each input side of at least a part of the latch with through mode and the plurality of flip-flops, and when the test data is held in the latch with through mode, It is also a preferable aspect that the scan chain is configured by the control signal via the selector.

  When such a selector is provided, a scan chain having a latch with a through mode can be easily configured.

  According to the present invention, it is possible to provide a semiconductor integrated circuit that facilitates testing.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a circuit configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

  The semiconductor integrated circuit 1 shown in FIG. 1 includes flip-flops 11, 12, 13, and 14 and combinational logic circuits 21, 22, 23, 24, 25, and 26. Here, the circuit configuration of the flip-flops 11, 12, 13, and 14 is the same as the circuit configuration of the flip-flop 101 shown in FIG. The combinational logic circuit 22 includes a first combinational logic circuit 22_1 and a second combinational logic circuit 22_2.

  Further, the semiconductor integrated circuit 1 includes a selector 31 and a through mode latch 40 inserted between the first combinational logic circuit 22_1 and the second combinational logic circuit 22_2.

  In the semiconductor integrated circuit 1 of the present invention, a latch 40 with a through mode is inserted at an arbitrary position in the combinational logic circuit 22, and test data is input using the latch 40 with a through mode. Therefore, it is possible to easily detect a logic defect on the output side from the position where the is inserted.

  Although only one latch 40 with through mode is shown in FIG. 1, the latch 40 with through mode is normally connected to a plurality of positions in the middle of the combinational logic circuit 22 having a large circuit scale, respectively. Input data. Further, FIG. 1 shows a state in which the combinational logic circuit 22 is divided into a first combinational logic circuit 22_1 and a second combinational logic circuit 22_2, and a portion between them is connected by a latch 40 with a through mode. However, the combinational logic circuit 22 usually also has a signal path from the input side flip-flop to the output side flip-flop without going through the latch with through mode. Therefore, in actuality, the latch with through mode is embedded at a plurality of positions in the combinational logic circuit 22 of a large scale.

  The selector 31 receives a data terminal D to which data D from the first combinational logic circuit 22_1 is input, a scan data terminal SD to which scan data SD from the flip-flop 13 is input, and a scan enable signal SE. And a scan enable signal terminal SE. In the selector 31, when the 'L' level is input to the scan enable signal terminal SE, the data D from the first combinational logic circuit 22_1 is output. On the other hand, when the “H” level is input to the scan enable signal terminal SE, the scan data SD from the flip-flop 13 is output.

  The through mode latch 40 includes a first latch 41, a second latch 42, an AND gate 43, and an OR gate 44. Here, the AND gate 43 and the OR gate 44 correspond to an example of the clock signal control circuit according to the present invention. Both the AND gate 43 and the OR gate 44 are supplied with the clock signal CLK and the scan mode signal SM. The scan mode signal SM is a signal that is at the ‘L’ level during the normal operation and is at the ‘H’ level during the scan test operation.

  When the scan mode signal SM is at the ‘L’ level, the latch 40 with a through mode is in a through mode in which the input data is passed through and output. On the other hand, when the scan mode signal SM is at the “H” level, the latch mode is set to hold the data input at the edge timing of the clock signal CLK. Details will be described below.

  The AND gate 43 and the OR gate 44 fix the gate terminal G of the first latch 41 to the “L” level and the gate terminal G of the second latch 42 when the scan mode signal SM is at the “L” level. Fix to 'H' level. On the other hand, when the scan mode signal SM is at the “H” level, the supplied clock signal CLK is supplied to the gate terminals G of the first and second latches 41 and 42.

  The first latch 41 passes through and outputs the input data when the gate terminal G is at the ‘L’ level. The input data is held at the timing when the gate terminal G changes from the “L” level to the “H” level, and the held data is output when the gate terminal G is at the “H” level.

  The second latch 42 slews and outputs the input data when the gate terminal G is at the “H” level. The input data is held at the timing when the gate terminal G changes from the “H” level to the “L” level, and the held data is output when the gate terminal G is at the “L” level.

  In the semiconductor integrated circuit 1 configured as described above, the scan mode signal SM is set to the ‘L’ level during normal operation. This 'L' level scan mode signal SM is input to the AND gate 43. For this reason, the AND gate 43 outputs an ‘L’ level signal. This 'L' level signal is input to the gate terminal G of the first latch 41. Therefore, the first latch 41 is in a through mode in which the input data is passed through and output. Further, the scan mode signal SM of “L” level is also input to the OR gate 44. Therefore, the OR gate 44 outputs a “H” level signal. This 'H' level signal is input to the gate terminal G of the second latch 42. For this reason, the second latch 42 is also in a through mode in which the input data is passed through and output. Accordingly, during normal operation, the latch 40 with through mode is in a through mode in which the input data is passed through and output.

  In the normal operation, the scan enable signal SE is also set to the “L” level. The 'L' level scan enable signal SE is input to the flip-flops 11, 12, 13, 14 and the scan enable signal terminal SE of the selector 31. For this reason, the data D from the first combinational logic circuit 22_1 passes through the selector 31 → the first latch 41 → the second latch 42 and is transmitted to the second combinational logic circuit 22_2 as it is. The output data D from the second combinational logic circuit 22_2 is held in the flip-flop 12 at the timing of the clock edge of the clock signal CLK.

  As described above, during normal operation, the data from the first combinational logic circuit 22_1 is directly transmitted to the second combinational logic circuit 22_2 even though the latch 40 with through mode is inserted. Become. Therefore, in the normal operation, the combinational logic circuit 22 that is not affected by the insertion of the through mode latch 40 is realized.

  Next, the scan test operation will be described. During the scan test operation, the scan mode signal SM is set to the “H” level. This 'H' level scan mode signal SM is input to the AND gate 43 and the OR gate 44. For this reason, the AND gate 43 and the OR gate 44 serve to supply the clock signal CLK supplied to the AND gate 43 and the OR gate 44 to the gate terminals G of the first and second latches 41 and 42. . That is, during the scan test operation, the latch 40 with through mode is in a latch mode that holds data input at the edge timing of the clock signal CLK.

  In this scan test operation, the shift mode is first set. In this shift mode, the scan enable signal SE becomes the “H” level. In this state, the clock signal CLK is supplied for a predetermined period, and the test data is shifted and held in the chain-connected flip-flops. At this time, since the latch 40 with through mode is also scan-connected via the selector 31, the scan data for testing is also held in the latch 40 with through mode. This data is used to test the second combinational logic circuit 22_2. Specifically, the flip-flops 11, 12, 13, and 14 shown in FIG. 1 and the latch with through mode are: Chain connection is performed in order, and test data is shifted in this order.

  Next, the scan enable signal SE changes from the “H” level to the “L” level, and the shift mode is switched to the capture mode. Hereinafter, a description will be given with reference to FIGS. 1 and 2.

  FIG. 2 is a diagram showing an operation of the semiconductor integrated circuit shown in FIG. 1 during a period when the shift mode is switched to the capture mode and the shift mode is returned again.

  The clock signal CLK is shown at the top of FIG. 2, and the scan enable signal SE is shown in the second stage. The scan enable signal SE is at the “H” level during the shift mode, and the scan enable signal SE is at the “L” level during the capture mode. FIG. 2 further shows data held in the first latch 41 and the second latch 42, and the flip-flop 11 connected to the input side of the first combinational logic circuit 22_1, and the second latch Data held in the flip-flop 12 connected to the output side of the combinational logic circuit 22_2 is shown.

  The left side of FIG. 2 shows the last part of the shift mode immediately before switching to the capture mode. That is, the first two rising edges of the clock signal CLK shown in FIG. 2 are supplied during the shift mode in which the scan enable signal SE is at the “H” level. Then, at the timing of the second rising edge, the scan data “2” for testing the second combinational logic circuit 22_2 supplied through the scan chain is held in the first latch 41. This data passes through the second latch 42 and is input to the second combinational logic circuit 22_2. At the same time, data “1” for testing the first combinational logic circuit 22_1 is held in the flip-flop 11 connected to the previous stage of the first combinational logic circuit 22_1.

  Thereafter, the scan enable signal SE changes from the “H” level to the “L” level to switch to the capture mode. The capture mode lasts only for one clock cycle. Then, at the timing of the next rising edge of the clock signal CLK (the third rising edge from the left side in FIG. 2), the second combinational logic circuit 22_2 is used by the test data '2' input from the second latch 42. '(2)', which is the result of performing the logic operation (test result), is held in the flip-flop 12 connected to the output of the second combinational logic circuit 22_2. At the same time, the first latch 41 holds ‘(1)’, which is the result of the logical operation of the first combinational logic circuit 22_1 using the data ‘1’ supplied from the flip-flop 11.

  Thereafter, the scan enable signal SE changes from the “L” level to the “H” level, and switches to the shift mode again. The subsequent operation will be described with reference to FIG.

  FIG. 3 shows the operation of the semiconductor integrated circuit 1 of FIG. 1 after returning to the scan mode in FIG. The first rising edge (first from the left) of the clock signal CLK shown at the top in FIG. 3 is the next rising edge after the third rising edge in FIG. FIG. 3 shows data held in the first latch 41, the second latch 42, and the flip-flop 12 in addition to the clock signal CLK and the scan enable signal SE. Data held in the flip-flop 13 connected to the input side of the latch 41 and the flip-flop 14 connected between the second latch 42 and the flip-flop 12 in the shift mode are also shown. The data held in the flip-flop 12 is also a signal output from the observation output terminal OUT provided at the Q output of the flip-flop 12.

  First, the test result ‘(2)’ of the second combinational logic circuit 22_2 held in the flip-flop 12 in the capture mode is output from the output terminal OUT as it is. On the other hand, the test result '(1)' of the first combinational logic circuit 22_1 held in the first latch 41 in the capture mode is held in the second latch 42 and then the clock signal CLK shown in FIG. Is held in the flip-flop 14 at the timing of the first rising edge (first from the left). Then, at the timing of the next rising edge of the clock signal CLK, it is held in the flip-flop 12 and output from the output terminal OUT. In addition to these test results '(2)' and '(1)', the test result '(3)' of the combinational logic circuit 25 held in the flip-flop 14 in the capture mode, and the flip-flop in the capture mode as well The test result '(4)' of the combinational logic circuit 24 held in the group 13 is shifted at every rising edge of the clock signal CLK, held in the flip-flop 12, and outputted from the output terminal OUT.

  The quality of each combinational logic circuit can be determined by comparing each test result output from the output terminal OUT with an expected value. In particular, by comparing the test result '(2)' with an expected value, the pass / fail of the second combinational logic circuit 22_2, which is a portion of the combinational logic circuit 22 close to the flip-flop 12 located on the output side, is determined. be able to. Here, the test result “(2)” is input as the scan data SD in the shift mode, and performs the logical operation on the second combinational logic circuit 22_2 by the data “2” held in the second latch 42. This is the result data. The data “2” is supplied from, for example, a tester as a part of the scan data SD, and can be any data suitable for testing the second combinational logic circuit 22_2. Therefore, it is possible to supply the second combinational logic circuit 22_2 with appropriate data for performing the test, and to easily determine the quality. As described above, in the semiconductor integrated circuit 1 of the present embodiment, the combinational logic circuit 22 that is not affected by the insertion of the latch 40 with through mode is realized in the normal operation, and in the scan test operation. A scan test of the combinational logic circuit 22 having a large circuit scale can be easily performed.

  Instead of inserting the through mode latch 40 in the combinational logic circuit 22 as in the semiconductor integrated circuit 1 of FIG. 1, a flip flip-flop dedicated to the scan test provided separately from the combinational logic circuit 22 is provided. It is possible to connect only during the scan test. It is also possible to supply test data to the second combinational logic circuit 22_2 by using the flip-flop dedicated to the scan test. However, in this case, the connection between the first combinational logic circuit 22_1 and the second combinational logic circuit 22_2, which is used as part of the signal path in the normal operation, is disconnected during the scan test, and is dedicated to the scan test. It is necessary to replace the connection with a flip-flop. Therefore, there is a problem in that even when there is a defect in the connection between the first combinational logic circuit 22_1 and the second combinational logic circuit 22_2, it cannot be found.

It is a figure which shows the circuit structure of the semiconductor integrated circuit of one Embodiment of this invention. FIG. 2 is a diagram showing timing in a capture mode of the semiconductor integrated circuit shown in FIG. 1. FIG. 2 is a diagram showing timing in a shift mode of the semiconductor integrated circuit shown in FIG. 1. It is a figure which shows the circuit structure of the conventional semiconductor integrated circuit which employ | adopted the scan test system. FIG. 5 is a diagram illustrating a circuit configuration of the flip-flop illustrated in FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 11, 12, 13, 14 Flip-flop 21, 22, 22_1, 22_2, 24, 25, 26 Combination logic circuit 31 Selector 40 Latch with through mode 41 1st latch 42 2nd latch 43 And gate 44 Orgate

Claims (3)

A plurality of flip-flops to which a clock signal is supplied and a combinational logic circuit; and the combinational logic circuit between an input-side flip-flop group selected from the plurality of flip-flops and an output-side flip-flop group during normal operation And the data held in the input side flip-flop group at the timing of the clock edge of the clock signal is supplied as input data to the combinational logic circuit, and the combinational logic at the timing of the next clock edge of the clock signal. A semiconductor integrated circuit including a synchronous logic circuit that holds output data output from a circuit in the output-side flip-flop group,
Inserted into the combinational logic circuit, the clock signal is supplied and a control signal is supplied. Through the control signal, the input data is passed through and output, and at the timing of the edge of the clock signal It further has a latch with a through mode capable of switching between a latch mode for holding inputted data,
During the normal operation, the latch with through mode is set as a through mode as a signal path in the combinational logic circuit,
During a test operation, a scan chain is formed in which at least a part of the plurality of flip-flops and the latch with through mode are connected in series, and the test data supplied through the scan chain is held in the latch with through mode And supplying the held test data to the combinational logic circuit. The latch with through mode is
When the clock terminal is at the first level, the input data is passed through and output, the data input at the timing when the clock terminal changes from the first level to the second level is held, and the clock A first latch that outputs the held data when the terminal is at a second level;
When the clock terminal is at the second level, the input data is passed through and output, the data input at the timing when the clock terminal changes from the second level to the first level is held, and the clock A second latch that outputs the held data when the terminal is at the first level is connected in series;
The clock signal supplied when the control signal is at the third level is supplied to the clock terminals of the first and second latches, and the first signal is supplied when the control signal is at the fourth level. 2. The semiconductor integrated circuit according to claim 1, further comprising a clock signal control circuit for fixing a clock terminal of the latch to the first level and fixing a clock terminal of the second latch to the second level. circuit.   A selector to which the control signal is supplied is provided on each input side of at least part of the latch with through mode and the plurality of flip-flops, and the control signal is stored when the test data is held in the latch with through mode. The semiconductor integrated circuit according to claim 1, wherein the scan chain is configured through the selector.

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