JP4417092B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a test at the time of manufacturing an LSI, and more particularly to a semiconductor integrated circuit capable of detecting a failure of a hard macro using scan and a circuit connected to the hard macro and the hard macro.

  In recent LSI development, there are increasing opportunities to separate development of a hard macro such as a CPU core incorporated in an LSI and development of an LSI. In an LSI incorporating a hard macro manufactured by such development, it is necessary to separately perform a macro internal scan for testing a hard macro and a macro external scan for testing a circuit other than the LSI hard macro. If the conventional LSI is used as it is, the interface part that is the connection part between the hard macro and the circuit excluding the LSI hard macro cannot be tested. It is known (see Patent Document 1).

[Patent Document 1] Japanese Patent Application Laid-Open No. 11-101859 The conventional combination circuit failure detection uses a scan flip-flop of the same type (a flip-flop is referred to as “FF”) to sandwich a specific combination circuit and connects to the input side of the combination circuit By setting various values in the FF, receiving the output of the combination circuit reflecting the set value in the scan FF connected to the output side of the combination circuit, and confirming whether the value is as designed Is what you do.

  FIG. 5 is a diagram showing a configuration example of a conventional hard macro and a hard macro peripheral circuit, and FIG. 6 is an enlarged view showing an ExScan portion of the hard macro of FIG.

  The conventional hard macro 10 includes an input / output unit (IO unit) 20, an external scan unit (ExScan unit) 30, an IO unit 20 and an ExScan unit between a macro input terminal and a macro output terminal which are input / output terminals. The hard macro 10 is composed of a hard macro (macro part) 40 excluding 30.

  The macro input terminal of the hard macro 10 includes a plurality of macro input terminals A3 and the like connected to outputs of the combinational circuit A2 and the like, and control input terminals SI to SCANIN [14.0] for controlling the ExScan unit 30 and the macro unit 40. The macro output terminals are a plurality of macro output terminals B3 and the like connected to inputs of the combinational circuit B2 and the like, and control output terminals SO and SCANOUT [14.0] which are outputs of the ExScan unit 30 and the macro unit 40. Become.

  The IO unit 20 includes a plurality of buffers respectively connected to the macro input terminal A3 and the like, and the ExScan unit 30 is connected to each of the plurality of buffers, operates independently during normal operation, and includes a shift register configuration during testing. A plurality of boundary scan FFs connected in series to each other, and the boundary scan FF, and the IO unit 20 and the ExScan unit 30 are a logic circuit that controls the boundary scan FF circuit and the macro unit 4 by an input from a control input terminal. Consists of. Further, the ExScan unit 30 includes one scan FF and one selector circuit as shown in FIG. 6 in order to perform independent flip-flop operation and shift register operation.

  The macro unit 40 is provided between the input-side and output-side boundary scan FFs, and is composed of circuits A6, A7... B7, B6, etc. in which combination circuits having predetermined functions and scan FFs are alternately connected. Are similarly configured as circuits that are serially connected to each other in a shift register configuration during testing.

  Further, the macro input terminal A3 and the macro output terminal B3 of the hard macro 10 provide outputs to a plurality of combinational circuits A2,... B2, etc. and their combinational circuits A2,. Macro external scan FFA1... FFB1 etc. to be connected are provided.

In the above-described conventional hard macro, the following scan failure detection method is adopted by two operations of a shift operation and a capture operation. The description of the configuration and operation of the configuration of the boundary scan FF and the logic circuit that controls the boundary scan FF will be omitted.
The shift operation is an operation in which an arbitrary value for inspection is set in the boundary scan FF inside the macro including the boundary scan FFA5 that gives an input to the macro internal combination circuit A6 that detects the failure, and HIGH is set in the SCANEN terminal. LOW is input to the EXSCAN terminal from the SCANCLK terminal as many clocks as the number of boundary scan FFs, and values to be set in the respective boundary scan FFA5... FFB5 are serially input from the SI terminal.

  Each boundary scan FFA5... FFB5 is configured with a scan chain with the SI terminal at the top and the SO terminal at the end separately from the normal function. FFA5... Is set to FFB5. At this time, the value written in each boundary scan FF during the capture operation described later is serially output to the SO terminal through the scan chain.

  In the capture operation, the output of the combination circuit is written in the macro internal scan FF including the macro internal scan FFA 7 that receives the output from the macro internal combination circuit A 6 that detects the failure. This is executed by inputting LOW to the terminal and inputting a clock once from the SCANCLK terminal.

  It is possible to determine whether or not the operation of each combinational circuit has an original function by the shift operation and the capture operation of the scan failure detection method described above (hereinafter, the operation of this scan failure detection method is referred to as “ This is called “Pinch failure detection”).

  Next, a more specific operation of the conventional pinch failure detection will be described. In the pinch failure detection of the hard macro 10 shown in FIG. 5, a macro external scan test and a macro internal scan test are performed.

The macro external scan test is a test for detecting a failure on the macro input terminal side and the macro output terminal side, and performs the following test operation.
At the time of the macro external scan test on the macro input terminal side, in order to detect a failure of the macro external combinational circuit A2, a boundary scan FFA5 connected to input a signal output from the buffer A4 of the macro input terminal A3; Then, pinching failure detection is performed by pinching between the macro external scan FFA1 and the macro external combination circuit A2 that are giving inputs to the macro external combination circuit A2. In the macro external scan test on the macro output terminal side, in order to detect a failure of the macro external combination circuit B2, the macro external combination is performed by the macro external scan FFB1 and the boundary scan FFB5 receiving the output of the macro external combination circuit B2. By sandwiching the circuit B2, the sandwiching failure is detected.

The macro internal scan test is a test for detecting a fault inside the macro on the macro input terminal side and the macro output terminal side, and performs the following test operation.
At the time of the macro internal scan test on the macro input terminal side, for example, in order to detect a failure of the macro internal combination circuit A6, the macro internal combination circuit is composed of the boundary scan FFA5 and the macro internal scan FFA7 which are input to the macro internal combination circuit A6. By sandwiching A6, the sandwiching failure is detected. Further, during the macro internal scan test on the macro output terminal side, for example, in order to detect a failure of the macro internal combination circuit B6, the macro internal scan FFB7 and the boundary scan FFB5, which are input to the macro internal combination circuit B6, By sandwiching the combinational circuit B6, the sandwiching failure is detected.

  In tests such as LSI manufacturing, all the hard macro terminals should be connected to the chip terminals at the time of testing, but in many cases it is difficult to pull out all the hard macro terminals to the chip terminals. Both of the circuits (the part connected to the hard macro and the LSI other than the hard macro, especially the hard macro) to increase the fault detection rate. Must be operated simultaneously.

  However, since a hard macro is used in a plurality of LSIs, a hard macro designer does not have circuit information for each LSI. In addition, hard macro circuits are sometimes black boxed, and even if they are open to the public, it takes a lot of time to understand the functions and circuits of the hard macro, so LSI designers have to learn about hard macros. Does not have detailed knowledge. Therefore, since it is not possible to create a pattern for testing the interface unit by operating both circuits at the same time, the LSI and the hard macro cannot be tested at the same time.

  In this way, in the conventional technology, both tests (LSI test and hard macro test) cannot be operated at the same time. Therefore, a hard macro has a built-in boundary scan circuit that operates in both tests, and each test pattern for both tests. The interface part failure is detected by creating and operating.

  In the prior art, in order to increase the failure detection rate of the interface portion of the hard macro, it is necessary to operate the built-in boundary scan circuit in the hard macro, but the boundary scan circuit is connected to the terminal of the hard macro as shown in FIG. Since one scan FF (scan flip-flop) and one select circuit (MUX) are required at a minimum, the increase in the number of hard macro terminals causes an increase in circuit area that cannot be ignored by the boundary scan circuit. That is, the area of the boundary scan circuit is proportional to the number of input and output terminals of the hard macro, and an increase in area due to the boundary scan circuit cannot be ignored in a hard macro having a large number of terminals. If an attempt is made to increase the failure detection rate by incorporating the boundary scan circuit in this way, there is a problem that the size of the hard macro is increased by incorporating a circuit that is used only for testing.

  In addition, since it is difficult to create a test pattern unless the scan FFs that are operated simultaneously in each case of the macro external scan and the macro internal scan are the same method, in the scan method using the scan FF of the boundary scan circuit, the hard macro The scan method of the scan FF and the scan FF of the LSI must be the same, and there is a problem that the flip-flop circuit configuration of the same method is required.

(the purpose)
An object of the present invention is to increase the reliability of an LSI and reduce the cost by increasing the test failure detection rate and reducing the area of the boundary scan circuit portion.

  Another object of the present invention is to eliminate the need for the scan flip-flops in the hard macro and the LSI scan flip-flops to be the same scan flip-flop circuit, and to increase the versatility of the LSI.

  In the conventional technique, some combinational circuits for fault detection are arranged between an external scan FF of LSI (scan FF of a circuit excluding a hard macro) and a boundary scan FF (hard scan of a macro macro) during macro external scan. In the macro internal scan, some combinational circuits for failure detection are arranged between the internal scan FF (hard macro scan FF) and the boundary scan FF.

  In contrast, the present invention provides a new terminal and selector in the hard macro, so that the combinational circuit subject to failure detection is arranged between the external scan FF and the external scan FF during the macro external scan, and during the macro internal scan. By arranging it between the internal scan FF and internal scan FF, the area is reduced by eliminating the boundary scan FF that is used only during the test, and the scan of the external scan FF and the boundary scan FF, the internal scan FF and the boundary scan FF Eliminate the need for matching methods.

  A semiconductor integrated circuit according to the present invention includes a first scan chain that includes a function built-in hard macro and a peripheral circuit outside the function built-in hard macro, and detects a failure of a combinational circuit outside the function built-in hard macro; A semiconductor integrated circuit capable of detecting a failure by each of the second scan chains for detecting a failure of the combinational circuit in the built-in hard macro, wherein the function built-in hard macro includes an input / output unit, the first scan chain, An external scan unit having a select circuit for selecting any one of the second scan chains; and a macro unit obtained by removing the input / output unit and the external scan unit from the function built-in hard macro. The chain includes a first flip-flop in the peripheral circuit, the select circuit, and a second flip-flop in the peripheral circuit. It is formed by flip-flop, the second scan chain, a third flip-flop in the macro section, and the select circuit is formed by a fourth flip-flop in the macro section.

  A semiconductor integrated circuit according to the present invention includes a first scan chain that includes a function built-in hard macro and a peripheral circuit outside the function built-in hard macro, and detects a failure of a combinational circuit outside the function built-in hard macro; A semiconductor integrated circuit capable of detecting a failure by each of the second scan chains for detecting a failure of a combinational circuit in the function built-in hard macro, wherein the function built-in hard macro includes an input / output unit and the first scan An external scan unit having a first select circuit and a second select circuit for selecting either a chain or the second scan chain, and the input / output unit and the external scan unit are excluded from the function built-in hard macro A macro unit, and the first scan chain includes a first flip-flop in the peripheral circuit and the first scan chain. The second scan chain is formed by a select circuit, the second select circuit, and a second flip-flop in the peripheral circuit, and the second scan chain includes a third flip-flop in the macro section and the first select circuit. And the second select circuit and the fourth flip-flop in the macro section.

According to the present invention, instead of incorporating one FF for a boundary scan and one selection circuit (selector circuit) per one terminal inside a macro of a hard macro as in the conventional example, a selector 1 per terminal of the hard macro is provided. By adopting a configuration in which one buffer and one buffer are provided, the area of the hard macro can be reduced by the following formula compared to the prior art, and thus the problem of an increase in the area of the hard macro can be suppressed. It is.
Reduced area = (area of scan FF−area of buffer) × number of terminals

  Further, since the boundary scan FF is not used during the macro external scan, it is possible to eliminate the restriction that the scan FF inside the macro and the macro external must be the same.

In addition, two selection circuits and one buffer are required for each output terminal, and only one selection circuit is required for each input terminal. The problem of increased area can be solved.
Reduced area = (area of scan FF−area of buffer−area of selection circuit) × number of output terminals + area of scan FF × number of input terminals

  In addition, since the boundary scan FF is not used at the time of macro external scan, the problem that the scan FF inside the macro and the scan FF outside the macro must have the same scan method can be solved.

  Further, the macro terminals are divided into two groups A and B, and the macro external scan is performed for each terminal group, and the macro external scan is performed twice. In other words, the macro input terminal and the macro output terminal are divided into two groups, and the failure of the combinational circuit connected to the input terminal of one group is detected by using the macro output terminal of the other group as an additional output terminal. It is possible to suppress the increase in the number of terminals by adopting a configuration in which it is not necessary to add one output terminal per input terminal.

  As described above, according to the hard macro with a built-in scan function according to the present invention, the area of the circuit for testing the macro interface portion can be reduced, so that the area of the hard macro can be reduced. In addition, since it is not necessary to match the scanning system of the circuit excluding the inside of the macro and the LSI macro, the versatility of the macro can be improved.

  FIG. 1 is a connection diagram between a hard macro and a hard macro peripheral circuit according to the first embodiment of the present invention, and FIG. 2 is an enlarged view of an ExScan portion of the hard macro.

(Configuration of the first embodiment)
The scan function built-in hard macro 1 according to the present embodiment includes an input / output unit (IO unit) 2 and an external scan unit (ExScan unit) between the macro input terminal A3 and the like as input / output terminals and the macro output terminal B3. 3 and a part (macro part) 4 excluding the IO part 2 and the ExScan part 3 from the scan function built-in hard macro 1. In FIG. 1, the configuration of the hard macro 1 and the hard macro peripheral circuit (external circuit on the input / output side of the hard macro 1) is shown in a simplified manner by the configuration between the two macro input terminals and the macro output terminal. This will be described in detail below with reference to the attached circuit portion.

  The macro input terminal of the hard macro 1 includes a plurality of macro input terminals A3 and the like connected to the output of the combinational circuit A2 and the like, and control input terminals (EXSCAN, SCANIN [ 14.0]) and a newly added macro output terminal A9 and the like. The macro output terminal is a plurality of macro output terminals B3 connected to the input of the combinational circuit B2 and the like, and the output of the macro unit 4 It consists of a certain control output terminal (SCANOUT [14.0]), a newly added macro input terminal B9, and the like.

  The IO unit 2 includes a plurality of buffers A4 and the like connected to the macro input terminal A3 and the like, and a buffer A8 whose output is connected to the macro output terminal A9. The ExScan unit 3 includes a plurality of buffers A4 and B4 and the like. A plurality of selectors A5 and B5 connected to each other, a macro internal wiring 31 between the selectors B5 to the selector A5, and a logic in which the selectors A5, B5 and the macro unit 4 are controlled by an input from a control input terminal It consists of a circuit. The macro section 4 is provided between selectors on the input side and output side, and is composed of circuits A6, A7... B7, B6, etc. in which combination circuits having predetermined functions and scan FFs in the macro section are alternately connected, The scan FFs inside the macro unit operate independently in normal operation, and are configured as circuits that are connected in series to each other in a shift register configuration during testing.

  Further, the macro input terminal A3 and the macro output terminal B3 of the hard macro 1 provide outputs to a plurality of combinational circuits A2, B2, etc. and their combinational circuits A2, B2, etc., and are also connected in series to the shift register configuration. Macro external scan FFA1... FFB1 and the like.

  FIG. 2 is an enlarged view of the ExScan unit according to the first embodiment. The selectors A5 and B5 are controlled by the logic outputs of the two logic circuits C1 and C2 that are input to the SCANTEST terminal and the EXSCAN terminal and have the opposite phase relation to each other, and the above-described selection operation is controlled. In the present embodiment, the ExScan section is not provided with the macro external scan FF, and is composed only of selectors A5 and B5 instead.

  In FIG. 2, the selector A5 receives the signal from the input terminal A3 when the control signal, which is the logic output of the logic circuit C1 that receives the scan test signal at the SCANTEST terminal and the EX scan signal at the EXSCAN terminal, is in the “LOW” state. This is supplied to the additional output terminal A9 and the inside of the core (macro part). Similarly, when the control signal, which is the logic output of the logic circuit C2, is in the “HIGH” state, the selector B5 supplies the signal from the additional input terminal B9 to the output terminal B3 and the macro internal wiring. When the logic state of the control signal is opposite to the above, the selector A5 supplies the signal from the macro internal wiring to the additional output terminal A9 and the macro unit, and similarly the selector B5 applies the signal from the macro unit to the macro internal wiring and Supply to output terminal B3. A signal switching configuration and operation including a more detailed selector are as follows. A detailed description of the logic circuit and the like that controls the macro unit 1 and the selection circuit will be omitted.

  The selector A5 outputs the signal from the buffer A4 to the macro output terminal (additional output terminal) A9 via the buffer A8, branches to the macro internal combination circuit A6, and outputs the signal from the selector B5. Control is performed to selectively execute one of the functions of outputting to the additional output terminal A9 via the buffer A8 and branching to the macro internal combinational circuit A6.

  The selector B5 outputs the signal from the macro internal combinational circuit B6 to the macro output terminal B3 via the buffer B4 and branches to the selector A5 for output, or the signal from the buffer B8 via the buffer B4. Control is performed to selectively execute one of the functions of outputting to the output terminal A3 and branching to the selector A5.

More detailed configurations of the IO unit 2 and the ExScan unit 3 of the present embodiment are as follows:
A macro input terminal A3 for inputting a signal from the outside of the macro; a buffer A4 for amplifying the signal of the macro input terminal A3;
A select circuit A5 that outputs a signal from the buffer A4 to the macro internal combination circuit A6 during macro external scan and normal operation, and outputs a signal from the select circuit B5 to the macro internal combination circuit A6 during macro internal scan;
The macro internal combination circuit A6 for normal operation, the scan FFA 7 in the macro for normal operation and internal scan operation,
A buffer A8 for amplifying the signal from the select circuit A5, an additional macro output terminal (additional output terminal) A9 for outputting the signal from the buffer A8 to the outside of the macro,
A macro internal scan FFB7 for normal operation and internal scan operation, a macro internal combination circuit B6 for normal operation,
A select circuit B5 that outputs a signal from the macro internal combination circuit B6 during normal operation and internal scan, and outputs a signal from the buffer B8 during macro external scan;
A buffer B4 for amplifying the signal from the select circuit B5, a macro output terminal B3 for outputting the signal from the buffer B4 to the outside of the macro,
An additional macro input terminal (additional input terminal) B9 for inputting a signal from the outside of the macro; a buffer B8 for amplifying the signal from the additional input terminal B9 and outputting the amplified signal to the selection circuit B5;
Is composed of a plurality of circuits.

(Operation of the first embodiment)
In the first embodiment, a select circuit A5 for outputting a signal input to the macro input terminal A3 to the newly provided additional output terminal A9 is provided during the scan test outside the macro. Since the select circuit B5 for outputting the signal input to the additional input terminal B9 to the macro output terminal B3 is provided, the additional output terminal A9 and the additional input terminal B9 can be connected outside the macro during the macro external scan test. By connecting the macro external combination circuit A2 connected to the macro input terminal A3 and the macro external combination circuit B2 connected to the macro output terminal B3, the macro external combination circuit A2 is given an input. Macro external scan FFB receiving outputs from external scan FFA1 and macro external combinational circuit B2 By sandwiching between, it is made possible to perform the pinching failure detection in the path of A1 → A2 → A5 → A9 → B9 → B5 → B3 → B2 → B1.

  Furthermore, in the present embodiment, during the macro internal scan test, the signal input from the input terminal A3 is amplified by the buffer A4, and the buffer B4 is added to the macro output terminal B3 via the additional output terminal A9 and the additional input terminal B9. In the macro internal scan test, the failure of the macro internal combination circuit A6 connected to the macro input terminal A3 and the macro output terminal B3 are provided. The failure of the macro internal combination circuit B6 connected to the macro internal combination circuit B6 is sandwiched between the macro internal scan FFB7 that inputs the macro internal combination circuit B6 and the macro internal scan FFA7 that receives the output of the macro internal combination circuit A6. It is possible to detect pinching failure

  That is, by interposing a macro internal scan test for detecting a failure of the macro internal combination circuit A6 and a failure of the macro internal combination circuit B6 between the macro internal scan FFB7 and the macro internal scan FFA7, B7 → B6 → B5 → A5 → A6 → It is possible to detect pinching faults along the route A7.

  As can be seen from the above operation, in this embodiment, it is possible to detect a failure in the interface portion without adding a new boundary scan circuit to the hard macro. Therefore, when comparing the present embodiment with a conventional scan FF and a selection circuit built in a macro, the conventional technology requires one scan FF and one selection circuit per terminal. In the embodiment, since only one selection circuit and one buffer are required for each terminal, the area of the following equation can be reduced as compared with the prior art, and the problem of an increase in the area of the hard macro can be suppressed. .

Reduced area = (Scan FF area-Buffer area) x Number of terminals Also, since the boundary scan FF is not used during external scan, the problem that the scan FF inside and outside the macro must be the same is solved. Is possible.

(Second Embodiment)
FIG. 3 is a diagram showing the configuration of the hard macro and the hard macro peripheral circuit according to the second embodiment of the present invention, and FIG. 4 is an enlarged view of the ExScan portion of the hard macro.
In this embodiment, the macro terminals are divided into two groups, and the macro external scan is performed for each terminal group. In particular, in the configuration example shown in FIG. 3, adjacent macro input terminals are divided into A and B groups, and adjacent macro output terminals are divided into B and A groups, and connected to the terminals of each group. The macro external combination circuit A2, A12 or B2, B12 is configured to detect pinching faults, and the number of macro input terminals and macro output terminals can be detected by performing pinching fault detection (twice pinching fault detection). It is possible to suppress the increase of

(Configuration of Second Embodiment)
Compared with the first embodiment, the second embodiment omits the additional output terminal A9, the buffer A8, etc., and is connected to the adjacent macro input terminals A3, B13 and macro output terminals B3, A13, respectively. Buffers A4, B14 and buffers B4, A14, and selectors A5, B5, B15, and A15 connected to the respective buffers, an additional input terminal B9 and a buffer B8 of the selector B5, and an additional input terminal of the selector A15 A19 and buffer A18, macro internal wiring (first macro internal wiring) from selector A5 to selector B5, selector B15 to selector A15, macro internal wiring from selector B15 to selector A15, and selector A15 to selector B15 ( A plurality of two circuits each having a second macro internal wiring) Different in that it formed.

  FIG. 4 is an enlarged view of the ExScan unit according to the second embodiment. The selectors A5 and B5 and the selectors A15 and B15 have a function that the selection operation is controlled by the outputs of the two logic circuits C1 and C2 that receive the control signals of the SCANTEST terminal and the EXSCAN terminal and the scan mode signal of the SCANMODE terminal. In particular, the selectors B5 and A15 include selection circuits S2 and S2 ′ (second selection circuit) that are controlled by a scan mode signal in addition to the selection circuits S1 and S1 ′ similar to the selection circuit in the selector of FIG. ).

  In FIG. 4, when the SCANMODE terminal is in a “HIGH” state, a signal path from the input terminal A3 to the output terminal B3 of the selector B5 can be formed via the selector A5. That is, the selector B5 allows the second selection circuit S2 to pass a signal from the macro internal wiring from the selector A5, and the selector A15 allows the second selection circuit S2 ′ to pass the signal from the additional output terminal A19. And When the logic output of the logic circuit C1 is in the “LOW” state, the selector A5 supplies the signal from the input terminal A3 to the macro internal wiring and the macro unit to the selector B5. The selector B5 supplies a signal from the macro internal wiring to the output terminal B3 and the macro internal wiring when the logic output of the logic circuit C2 is in the “HIGH” state. The selector A15 supplies the signal from the additional input terminal A19 to the output terminal A13 and the macro internal wiring.

  When the logic state of the control signal is opposite to the above, the selector B15 supplies the signal from the input terminal B13 to the selector A15 via the macro internal wiring, and the selector A15 selects the signal from the second selection circuit S2 ′ and the selection signal. The signal is output to the output terminal A13 via the circuit S1 ′.

  A signal switching configuration and operation including a more detailed selector are as follows. A detailed description of the logic circuit that controls the macro unit 1 and the selector circuit is omitted.

  At the time of macro external scan, HIGH is input when scanning the group A terminal from the outside of the macro, and LOW is input when scanning the terminal of the B group, and the macro input terminal A3 that inputs a signal from the outside of the macro. A buffer A4 for amplifying the signal at the macro input terminal;

  A signal from the buffer A4 is output during macro external scan and normal operation, a select circuit A5 that outputs a signal from the select circuit B5 during macro internal scan, a macro internal combination circuit A6 for normal operation, and normal operation Macro internal scan FFA7 for macro internal scan operation,

  A signal from the select circuit A5 is output during macro external scan and HIGH is input to the SCANMODE terminal, and a signal from buffer B8 is output during macro external scan and LOW is input to the SCANMODE terminal. A select circuit B5 that outputs a signal from the macro internal combination circuit B6 during operation or a macro internal scan, a buffer B4 that amplifies the signal from the select circuit B5, and an additional output terminal that outputs the signal from the buffer B4 to the outside of the macro B3,

  A macro input terminal B13 for inputting a signal from the outside of the macro, a buffer B14 for amplifying the signal of the macro input terminal, a signal from the buffer B14 at the time of macro external scanning and normal operation, and a select circuit at the time of macro internal scanning A select circuit B15 that outputs a signal from A15, a macro internal combination circuit B16 for normal operation, a macro internal scan FFB17 for normal operation and macro internal scan operation,

  A signal from the select circuit B15 is output when LOW is input to the SCANMODE terminal during the macro external scan, and a signal from the buffer A18 is output during the macro external scan and HIGH is input to the SCANMODE terminal. During operation or macro internal scan, a select circuit A15 that outputs a signal from the macro internal combination circuit A16, a buffer A14 that amplifies the signal from the select circuit A15, and an additional output terminal that outputs the signal from the buffer A14 to the outside of the macro A13,

  Macro internal scan FFB7 for normal operation and macro internal scan operation, macro internal combination circuit B6 for normal operation, macro internal scan FFA17 for normal operation and macro internal scan operation, and macro for normal operation Internal combination circuit A16;

An additional input terminal B9 for inputting a signal from the outside of the macro, a buffer B8 for amplifying the signal from the additional input terminal B9, an additional input terminal A19 for inputting a signal from the outside of the macro, and a signal from the additional input terminal A19 A buffer A18 to be amplified;
It is composed of a plurality of circuits in units of

(Operation of Second Embodiment)
The operation of pinching failure detection by the terminals of the A group and the B group of the present embodiment will be described below.

(1) During macro external scanning of the A group terminal, HIGH is input from the outside of the macro to the SCANMODE terminal. In this state, the macro external combination circuits A2 and A12 are connected to the macro external scan FFA1 in the path of A1, A2, A3, A4, A5, B5, B4, B3, A19, A18, A15, A14, A13, A12, and A11. Pinching is performed between the macro external scan FFA11 and pinching failure detection is performed.

  More specifically, the buffer A4 amplifies and outputs the signal input to the macro input terminal A3, the signal from the buffer A4 is output from the select circuit A5, and the signal from the select circuit A5 is output from the select circuit B5. Then, the signal from the select circuit B5 is output from the buffer B4, and the signal from the buffer B4 is output from the macro output terminal B3.

  The signal input to the additional input terminal A19 is amplified and output by the buffer A18, the signal from the buffer A18 is output from the select circuit A15, and the signal from the select circuit A15 is amplified and output from the buffer A14. The macro output terminal A13 outputs a signal from the buffer A14.

  Then, by connecting the macro output terminal B3 and the additional input terminal A19 outside the macro, the macro external combination circuit A2 connected to the macro input terminal A3 and the macro external combination circuit A12 connected to the macro output terminal A13 are failed. The pinch failure detection is performed between the macro external scan FFA1 that provides input to the macro external combination circuit A2 and the macro external scan FFA11 that receives the output of the macro external combination circuit A12.

(2) During macro external scanning of the B group terminal, LOW is input from the outside of the macro to the SCANMODE terminal. In this state, the macro external combination circuits B2 and B12 are connected to the macro external scan FFB11 and the macro external on the route of B12 → B13 → B14 → B15 → A15 → A14 → A13 → B9 → B8 → B5 → B4 → B3 → B2 → B1. Pinching is performed with the scan FFB1, and pinching failure detection is performed.

  More specifically, the buffer B14 amplifies and outputs the signal input to the macro input terminal B13, the select circuit B15 outputs the signal from the buffer B14, and the select circuit A15 receives the signal from the select circuit B15. The signal is output from the select circuit A15 from the buffer A14, and the signal from the buffer A14 is output from the macro output terminal A13.

  The signal input to the additional input terminal B9 is amplified and output by the buffer B8, the signal from the buffer B8 is output from the select circuit B5, the signal from the select circuit B5 is amplified and output from the buffer B4, The macro output terminal B3 outputs a signal from the buffer B4.

  Then, by connecting the macro output terminal A13 and the additional input terminal B9 outside the macro, the macro external combination circuit B12 connected to the macro input terminal B13 and the macro external combination circuit B2 connected to the macro output terminal B3 are treated as macros. A pinch failure is detected by the macro external scan FFB11 that provides an input to the external combinational circuit B12 and the macro external scan FFB1 that receives the output of the macro external combinational circuit B2.

  The macro internal scan test of the second embodiment is the same as that of the first embodiment. In other words, the failure of the macro internal combination circuit A6 and the failure of the macro internal combination circuit B6 are sandwiched between the macro internal scan FFB7 and the macro internal scan FFA7, thereby pinching the failure in the path of B7 → B6 → B5 → A5 → A6 → A7. In addition, by interposing the failure of the macro internal combination circuit B16 and the failure of the macro internal combination circuit A16 between the macro internal scan FFA17 and the macro internal scan FFB17, the path A17 → B16 → A15 → B15 → B16 → B17 This makes it possible to detect pinching failures.

In the present embodiment, a failure in the interface portion can be detected without adding a new boundary scan circuit to the macro by the above operation.
Therefore, comparing this embodiment with the conventional technique in which the FF for the boundary scan and the selection circuit are built in the macro, the conventional technique requires one scanning FF and one selection circuit per terminal. In the configuration, only two selection circuits per output terminal and one buffer per one input terminal are required, so the area of the following equation can be reduced compared to the conventional technology, so the area of the hard macro is reduced. The increase problem can be solved.

Area to be reduced = (area of scan FF−area of buffer−area of selection circuit) × number of output terminals + area of scan FF × number of input terminals Also, since the boundary scan FF is not used during macro external scan, the macro internal and macro The problem that the external scan FFs must have the same scan method can be solved.

  As described above, in the second embodiment, by performing the macro external scan twice ((1), (2)), one output terminal is required for each input terminal required in the first embodiment. A configuration that does not need to be added can be realized.

  In the second embodiment, the macro input terminal and the macro output terminal are divided into two groups, and a failure of the combinational circuit connected to the macro input terminal of one group is detected. It can be detected by using it as an additional output terminal.

  As described above, according to the hard macro of the present invention, it is possible to reduce the area of the circuit for testing the macro interface portion, and thus it is possible to reduce the area of the hard macro. In addition, since it is not necessary to match the scanning system of the circuit excluding the inside of the macro and the LSI macro, the versatility of the macro can be improved.

It is a figure which shows the structure of the macro of the 1st Embodiment of this invention, and a macro peripheral circuit. It is the figure which expanded the ExScan part of 1st Embodiment. It is a figure which shows the structure of the macro of the 2nd Embodiment of this invention, and a macro peripheral circuit. It is the figure which expanded the ExScan part of 2nd Embodiment. It is a figure which shows the connection structure of the conventional macro and macro peripheral circuit. It is the figure which expanded the conventional ExScan part.

Explanation of symbols

1, 10 Hard macro (core)
2, 20 IO unit (input / output unit)
3, 30 ExScan section (external scan section)
4, 40 Macro section 31 Macro internal wiring A3, A9, B13 Macro input terminal B3, A13 Macro output terminal A9 Additional output terminal (additional macro output terminal)
B9, A19 Additional input terminal (additional macro input terminal)
A2, B12, B2, A12, A6, B6 Combinational circuit A7, B7 Scan flip-flop (scan FF)
C1, C2 logic circuit S1, S1 ′, S2, S2 ′ selection circuit

Claims (6)

A first scan chain that includes a function built-in hard macro and a peripheral circuit outside the function built-in hard macro, and detects a failure of the combination circuit outside the function built-in hard macro; and a combination circuit in the function built-in hard macro A semiconductor integrated circuit capable of detecting a failure by each of the second scan chains that perform the failure detection,
  The function built-in hard macro is
  An input / output unit;
  An external scan unit having a select circuit for selecting either the first scan chain or the second scan chain;
  A macro unit excluding the input / output unit and the external scan unit from the function built-in hard macro,
  The first scan chain is formed by a first flip-flop in the peripheral circuit, the select circuit, and a second flip-flop in the peripheral circuit,
  The second scan chain is a semiconductor integrated circuit formed by a third flip-flop in the macro section, the select circuit, and a fourth flip-flop in the macro section. A first scan chain that includes a function built-in hard macro and a peripheral circuit outside the function built-in hard macro, and detects a failure of the combination circuit outside the function built-in hard macro; and a combination circuit in the function built-in hard macro A semiconductor integrated circuit capable of detecting a failure by each of the second scan chains that perform the failure detection,
  The function built-in hard macro is
  An input / output unit;
  An external scan unit having a first select circuit and a second select circuit for selecting either the first scan chain or the second scan chain;
  A macro unit excluding the input / output unit and the external scan unit from the function built-in hard macro,
  The first scan chain is formed by a first flip-flop in the peripheral circuit, the first select circuit, the second select circuit, and a second flip-flop in the peripheral circuit,
  The second scan chain is a semiconductor integrated circuit formed by a third flip-flop in the macro section, the first select circuit, the second select circuit, and a fourth flip-flop in the macro section. . When detecting a failure of a combinational circuit outside the function built-in hard macro, the first select circuit outputs a signal input from the first flip-flop via the combinational circuit to the second select circuit. The second select circuit outputs the signal input from the first select circuit to the second flip-flop via a combinational circuit,
  When detecting a failure of a combinational circuit in the function built-in hard macro, the second select circuit outputs a signal input from the third flip-flop via the combinational circuit to the first select circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the first select circuit outputs the signal input from the second select circuit to the fourth flip-flop via a combinational circuit. 4. The first scan chain, wherein the first select circuit and the second select circuit are connected to each other via a wiring provided in the peripheral circuit. The semiconductor integrated circuit as described. 3. The first scan chain, wherein the first select circuit and the second select circuit are connected to each other via a wiring provided in the external scan unit. 3. The semiconductor integrated circuit according to 3. 6. The first select circuit and the second select circuit are connected to each other via the third flip-flop and the fourth flip-flop. Semiconductor integrated circuit.

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