JPS6210729A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To obtain the data transmission equipment which can propagate the data slowly and little by little by providing an indicating means to instruct the transfer timing of the data and a transfer timing control means to control the output timing of at least one C element in accordance with the instruction. CONSTITUTION:When a toggle switch 36 is turned from ON to OFF, the output of an inverter 35a comes to 0, and the data arrive at a C element 7h and stop once. At such a time, a momentary switch 39 is normally OFF, when this is pushed, the clock input of a D type flip flop 31 comes to 1, a Q output comes to 1, the P2 output of a C element 34 comes to 1 and a P1 output comes to 0. Further, since the output of an inverter 35d comes to 0, again, the P2 output of the C element 34 comes to 0 and the P1 output which is an inverting output comes to 1. Since the P1 output of the C element 34 comes to 0 once and comes to 1, a C element 7i returns the P1 output, sends the P2 output to the C element 7j and transmits the data of one word to the next stage. Thus, at the time of the necessity, the data can be slowly propagated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission device that primarily performs data transmission between systems that operate asynchronously.

[Conventional technology]

Conventionally, the method for transmitting data between asynchronous systems is FO (first-in, first-out).
A common method was to use memory as a buffer between systems (Inter 7 Engineering, August 1984, No. 26).
(Refer to pages 8 to 270), the FO memory simply has a data buffer function, so such FO memory
The FO memory is used for data transmission between asynchronous systems. □ and multiple asynchronous systems can only be connected in series, so the entire system connected by the FO memory is a simple cascade connection. However, the problem was that the degree of freedom was extremely low.

In response, the applicant has developed and filed an application for a data transmission device that can provide greater flexibility when constructing an entire system by connecting asynchronous systems (Japanese Patent Application No. 60-33035). , see Japanese Patent Application No. 60-33036). This data transmission device will be explained below.

FIG. 2 is a diagram showing the system of the data transmission device. In the figure, 5 is a data transmission path, 2a to 2c are branch parts, 3a to 3C are merging parts, 1a to IC are processing elements, and 4 is an interface. be.

In such a device, if the interface 4 is
Packet data flowing through network element 3
Processing elements 1a to I while circulating between a and 2a to 2C.
After reaching one of the processing elements 1a to 1C and being distributedly processed by the respective processing elements 1a to IC, the processing results are collected by the network elements 3b and 3C and sent out again to the external system via the interface 4.

Further, FIGS. 3 and 4 show an example of an asynchronous self-running shift register used in the data transmission path 5. In FIG.

In Figure 3, 6 is a parallel data latch, 7 is a 3-manpower N
This is a transfer control circuit (hereinafter referred to as C element) which is constituted by an AND8, two NANDs 9 and 10, and provides a rising edge trigger to the parallel data latch 6. An asynchronous self-running shift register is a register that automatically shifts input data in the output direction without using a shift clock, provided the next register is empty. It has a buffer function. This asynchronous free-running shift register is composed of a parallel data latch 6 and a C element 7, where the C element 7 is a PO.

It receives two inputs of P3 and outputs two outputs, PL and P2O, and the internal state of the C element 7 is determined by these four signals P.
It is determined by the status of O to P3, and as shown in the table below, s
, )-88. In the following explanation,
It is assumed that the logical value of 0.1 corresponds to the low level of the signal value, respectively.

Table 1 Next, the transition diagram of the above-mentioned 9 states 5Q-8B of the C element 7 is shown in Figure 5.
As shown in the figure. In the figure, Gin is a conditional state transition, - is an unconditional state transition, and P1↑, PI↓, etc. are each a signal value of 0.
to 1, indicating a change from 1 to O.

Whether it goes through cycle A or cycle B shown in FIG. 5 depends on the time when the next stage of the shift register becomes capable of receiving, and the time when the previous stage becomes capable of output.
In any case, by going through cycle A or cycle B, data from the previous stage can be propagated to the next stage.

By connecting such asynchronous free-running shift registers in multiple stages as shown in FIG. 3, the C element 7 performs the state transition shown in FIG. 5, and data autonomously propagates between the parallel data latches 6. It is done.

Further, FIGS. 6 and 7 show an example of the configuration of the branching part and the merging part shown in FIG. 2. Here, in this example, the data is in the form of a packet of words, and
Each word has two control bits, BOP to indicate that it is the first word and EOP to indicate that it is the last word, in addition to the data value, and the first word has preceding information that is a branch condition. shall have the following.

First, the branch section shown in FIG. 6 will be explained.

The head of the packet is input to the input data transmission path 5a, and C
When reaching the stage of element 7a, the P2 output of the element 7a changes from 0 to 1, and the data value of the first word stored in the parallel data latch 6a of the previous stage is changed to the parallel data latch 6.
stored in b. At this time, node A (BOP bit)
changes from 0 to 1, so the D-type flip-flop 1
1, the data value of the first word of the packet is latched in the same way as the parallel data latch 6b. This latched first word is sent to the comparison data register 1 by the exclusive OR circuit 12.
3, and is compared with the value of the mask data register 15 in the NAND gate circuit 14 to mask unnecessary comparison bits, and output the comparison result, that is, the branch decision, to the D5 flip-flop 16. During this time, the packet propagates on the input data transmission path 5a, and the first word of the packet is C
When the stage of element 7b is reached, the node B (BOP bit) changes from 0 to 1, and as a result, the branch decision result is latched in the above-mentioned flip-flop 16, and this result is sent to the D-type latch 17. Output.

On the other hand, the D-type latch 17 is connected to node c (uop bit) and node D after the packet preceding the above packet passes.
(C element 7017) P2 output) is 0. At the point in time, the input from the D-type flip-flop 16 is latched, thereby controlling the inputs to the four-manpower NAND gates 18a to 18d. That is, when the branch condition is 00, the NAND game) 18c is used to prevent branching.

Output 0 for 18d, NAND game) 18a,
18b is outputted to control the packet to be propagated to the output data transmission path 5b. Conversely, when the branch condition is 1, the opposite control is performed and the packet is propagated to the branch data transmission path 5C. At this time, as mentioned above, in order to ensure that a response is returned to the C element 7c no matter which direction the packet propagates, the NAND game) 18
Open collector N that performs the same operation as a, , 18c
AND gates 18t) and 18d are provided, and their outputs are wired ORed with negative logic and connected to the 2nd gate of C element 7C.
Sent to 3 people.

Next, the merging section shown in FIG. 7 will be explained.

In this case, the input data transmission line 5d and the output data transmission line 5
The data on the merging data transmission path 5f is merged into the main line consisting of e, but the flow of data is prioritized on the main line, and merging is only allowed when there is an empty buffer on the main line. It will be done. That is, when there is no data on the main line, the negative logic wired OR output of the oven collector inverter 19 becomes 1, so when data arrives at the merged data transmission line 5f and node A becomes 1, it becomes 2.
Both of the two manual inputs of the manual AND gate 20 become 1, the output thereof becomes 1, the SR flip-flop 21a is set, and the SR flip-flop 21'b is reset. As a result, for the combined data transmission path 5f, the input from the SR flip-flop 21a to the 4-input NAND gate 22a becomes 1, causing the C element 7d to perform the same operation as the other C elements. At the same time, the parallel data latch 6d becomes capable of outputting, so the data on the merged data transmission line 5f merges into the main line. On the other hand, for the input data transmission path 5d, the SR flip-flop 2
The input from 1b to the four-man power NAND gate 221) becomes 0, and therefore the C element 78 does not propagate the previous stage data. Note that at this time, since the output of the parallel data latch 6e is in a non-impedance state, even if data arrives at the input data transmission path 5d during the merging operation, the merging will not be hindered.

On the other hand, when the merging of one packet of data is completed, the data on the main line is controlled to flow again.

That is, when the C element 7f sends out the last word of the packet, the node B (KOP bit) becomes 0, and when the C element 7d receives this, the node C becomes 0. Therefore, the two-man power NOR gate 23a receives the signals from nodes B and O.
output becomes 1, the SR flip-flop 21a is reset, and the next node propagation is prevented from occurring between C elements 7f and 7d. Further, when the last word of the merged packet is received at the first stage of the output data transmission line 5e, that is, when the node D (KOP bit) and the node E are both set to 0, the input signal of the two-man NOR gate 23b is Since both are 0, the SR flip-flop 21
1) is set, the C element 70 begins to propagate the previous stage data, and data can now flow on the tree line.

The open collector NAND gate 24a returns .

[Problem that the invention seeks to solve]

By the way, the above-mentioned data transmission device can be used to configure an arithmetic processing device, and in this arithmetic processing device, there are cases in which it is generally desired to observe various states of various functional parts, and the method for doing so is to use data transmission. It is possible to observe this from the data flowing on the road.

However, in the above-mentioned data transmission device, the data transmission path is configured using a self-running shift register, and the data f
Since it is propagated very quickly, typically 25 ne θC to 50 n days θC, it is impossible to observe various functional parts from the data.

This invention was made in view of the above problems, and it is an object of the present invention to provide a data transmission device that can slowly propagate data little by little when necessary.

[Means for solving problems]

The present invention provides a data transmission device in which a data transmission path is configured using a self-propelled shift register including a data latch and a C element. A transfer timing control means for controlling the output timing of the control signal of at least one C element is provided.

[Effect]

In this invention, when the transfer timing control means is activated, the transfer timing control means stops outputting the control signal of the C element, and when an instruction is given from the instruction means, the transfer timing control means outputs the control signal from the C element. 8 is output.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a data transmission device according to an embodiment of the present invention. In the figure, 30 transfer timing control means are connected to D-type flip-flops 31. Negative logic AND gate 3
2. Negative logic OR gate 33. C element 34° inverter 3
5a-35e, toggle switch 36. Resistor 37a,
37b and a capacitor 38.

39 is constructed using an oven collector type four-man power NAND gate for a module for instructing data transfer timing.

Next, the operation will be explained.

When the toggle switch 36 is ON, the transmission line operates normally. Then, when the toggle switch 36 is turned OFF, the output of the inverter 35a becomes 0, so that the output reaches the data Ha element 7h that has been propagated through the transmission path, and is temporarily stopped there. At this time, the momentary switch 39 is normally off, but when it is pressed, the clock input of the D-type flip-flop 31 becomes 1, and the D-type flip-flop 31 outputs a clock input of 1.

The output will be l. As a result, the P2 output of the C element 34 is 1
, its inverted output is the P1 output Vio. Furthermore, since the output of the inverter 35d becomes 0 after passing through the inverters 35b and 35c, the P2 output of the C element 34 becomes 0 and the PL output, which is an inverted output, becomes 1 again. P1 of this C element 34
As the output becomes 0 and then becomes 1, the C element 71
The P2 output becomes 1 and becomes O, and the C element 71 becomes the 0 element in the previous stage. hK returns the P1 output that it has received, and transmits the P2 output of the C element 7j [P2 output of the next stage to transmit one word of data to the next stage.In this way, by operating the momentary switch 39, data is transmitted one word at a time. The Rukoto.

In the device of this embodiment as described above, the transfer timing control circuit controls the P2. Since the output timing of the PI is controlled, data can be propagated word by word, and as a result, when this device is used to configure an arithmetic processing unit, various states of various functional components can be changed slightly. It becomes possible to observe each part separately.

In the above embodiment, the C element has a two-stage structure, but it may have a one-stage structure as shown in FIG.

In addition, although the above embodiment describes the case where data is transmitted between asynchronous systems, the present invention can be similarly applied to the case where data is transmitted between synchronous systems.
In this case, the C element may be a synchronous control circuit.

Furthermore, the C element used in the above-mentioned asynchronous self-propelled shift register is the C element shown in FIG. 3 (hereinafter referred to as the first type C element).
7, for example, the second one shown in FIG. 8(a).
O-type element 50. Alternatively, a third type C element 51 shown in FIG. 8(b) or the like may be used. In Figure 8(a), the second
It has a two-stage configuration of 50 first type O elements 7', and in Fig. 8(b), □3rd
Type C element 51 is a two-man NAND game) 52a, 52b
.

52c, negative logic input OR gate 53 and inverter 54
It is made up of.

〔Effect of the invention〕

As described above, according to the present invention, in a data transmission device in which a data transmission path is configured using a self-propelled shift register consisting of a data latch and a C element, Since the output timing of the control signal of at least one C element is controlled by the transfer timing control means, data can be propagated slowly when necessary.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data transmission device according to an embodiment of the present invention, FIG. 2 is an overall block diagram of a data transmission device developed by the applicant, and FIGS. 3 and 4 are both used in the above device. Figures 2 and 5 are diagrams for explaining the functions of this asynchronous free-running shift register, and Figures 6 and 7 are diagrams showing specific examples of the above-mentioned device. Circuit configuration diagram, Figure 8(a)
, (1:+) is a diagram showing an example of another C element used in the present invention. 5... Data transmission line, 6... Parallel data latch, 7
...C element (transfer control circuit), 30...transfer timing control circuit (transfer timing control means), 39...
Momentary switch (instruction means). In the figures, the same reference numerals indicate the same or equivalent items.

Claims (1)

[Claims] (1) A data transmission line configured using a shift register consisting of a plurality of data storage means and a transfer control circuit in each stage that controls the data storage means in its own stage according to a control signal from a transfer control circuit in an adjacent stage. a data transmission device for transmitting data between systems through the data transmission path, the data transmission device comprising: instruction means for instructing the data transfer timing; and at least one of the transfer control circuits according to the output of the instruction means. 1. A data transmission device comprising: transfer timing control means for controlling output timing of a control signal.