JPH0128544B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an electronic circuit that increases the signal propagation speed by reducing the delay in signal propagation caused by the load capacitance of a signal line such as a bus line that transmits a digital voltage signal. In particular, the present invention provides an electronic circuit that is extremely effective when applied to signal lines in digital integrated circuits.

A signal line that carries a digital voltage signal and carries it to a receiving gate located at a remote location has considerable wiring resistance and capacitance, which delays signal propagation. especially,
Like the bus line of a microcomputer
Signal lines in MOS integrated circuits have a large amount of parasitic capacitance and gate input capacitance, as well as the amount of power required to drive the signal lines.
Since the impedance of the MOS transistor is relatively large, the delay in signal propagation is significant.

FIG. 1 shows changes in voltage on signal lines in a CMOS integrated circuit. At time t ₁ , when one of the gates driving the signal line transitions from low level to high level, the receiving gate changes as shown by the broken line with a curve approximately determined by the load capacitance of the signal line and the output impedance of the drive gate. appears in the input.
The threshold voltage of a CMOS gate is normally half the power supply voltage V _DD , and if this is V _TH , then the dashed curve is
At time t _B when V _TH is reached, the reception gate changes from “0” to “1”
receive. In other words, the propagation delay on the signal line is t _B −t ₁
It is.

By the way, if a circuit with the function of rapidly increasing the voltage of the signal line operates only in the voltage range between voltages V _L and V _H , then after time t ₂ the circuit will look like the solid line, The propagation delay of the signal line is reduced to _tA to _t1 , that is, the time _tB to _tA . At this time,
Assuming that the capacitance of the signal line is C and the output resistance of the drive gate is R, the power supply V _DD is set between the voltage V _L and V _H.
Assuming that _{the above} capacitance C is charged _{with an} equivalent resistance r _from It becomes a curve with a time constant. However, indicates the parallel resistance value. By setting r sufficiently small compared to R,
This effect becomes larger. Signal line voltage from V _L
Since it is only necessary to increase the voltage rapidly during V ₄ ,
Any device may be used as long as it has the function of charging the above C. In the embodiment of the present invention, the capacitor C is charged with a P-channel MOS transistor as shown at 8 in FIG.

In Figure 1, the voltage on the signal line changes from “0” to “1”.
Similarly, in the case of a transition from “1” to “0”, the voltage range V _H to V _L (from “0” to “1”) that includes V _TH V _L , V _H in case
), and the capacity C rapidly increases
All you have to do is discharge the voltage and rapidly lower the voltage. At this time, the propagation delay from "1" to "0" is significantly shortened.

FIG. 2 shows an embodiment of the present invention.

1 is a long signal line with a relatively large load capacity in a CMOS integrated circuit. 10 is a capacitance C representing the load capacitance of the signal line in the form of a lumped constant. Reference numeral 12 denotes a buffer of a circuit on the transmitting side that carries a signal onto the signal line 1. 11 is a resistance equivalently representing the output resistance of the buffer 12. 2 is the voltage of signal line 1
This is a V _H detection circuit that detects whether or not it is greater than V _H.
When voltage a of signal line 1 is 0<a<V _H , “0”;
It becomes "1" when V _H ≦a<V _DD . 3 is a V _L detection circuit that detects whether the voltage of the signal line 1 is higher than the detection means V _L like 2, and when the voltage a of the signal line 1 is 0<a<V _L , it is "0". ”, V _L ≦a<
It becomes "1" when V _DD . V _L has a relationship of V _L <V _H. 4, 5, 6, and 7 are an inverter, an R-S latch, a NOR gate, and a NAND gate, respectively. 8 and 9 are P channel MOS
The transistor is an N-channel MOS transistor, and its drain is connected to the signal line 1.

Next, the operation of the embodiment shown in FIG. 2 will be explained. FIG. 3 shows the output voltage waveforms S, a to g of each section S, a to g in FIG. 2, and the ON and OFF states of the P and N channel transistors 8 and 9. Batsuhua 12
These are waveforms of various parts corresponding to the case where the input S changes from "0" to " ₁ " at time t1 and from "1" to "0" at time _t4 . Time t ₂ during the transition from “0” to “1”
The output of the gate 7 becomes low level only between t3 and _t3 , and the P channel transistor 8 turns on, while the output of the gate 6 becomes low only between the time _t5 and _t6 during the transition from "1" to "0". It can be seen that the voltage becomes high level and the N-channel transistor 9 is turned on.
In the time chart shown in Figure 3, the times from t ₂ to t ₃ and from t ₅ to _{t 6} are expanded compared to the actual time, and other parts are compressed to make it easier to understand. . The signal propagation delay of the signal line is “0”→
In the case of “1” and “1”→“0”, respectively, t _A −t ₁ ,
t _B −t ₄ .

In this way, the V _H , V _L detection circuit, inverter,
By making the P-channel and N-channel transistors conductive using the RS latch and two NAND gates, the load capacitance of the signal line can be rapidly charged and discharged, and the signal transmission delay can be greatly shortened.

As seen in Figure 3a, for the purpose of the present invention, it is necessary that V _L < V _TH < V _H , and the voltage range changes rapidly in one direction (from V _L to V _H ). but,
Including the threshold voltages V _TH1 , V _TH2 , ......, V _THo of all gates that input the voltage of the signal line, that is,
It is necessary that V _L < (V _TH1 , V _TH2 , ......, V _THo ) < V _H.

The effects of the present invention are extremely significant in the case of a signal line connected to inputs and outputs of a large number of gates, such as a bus line of a microcomputer. In other words, in order to rapidly drive a bus with a large capacity, it is necessary to increase the gm of the output transistors of all the gates whose outputs are connected to the bus, which increases the area. Since there are a large number of gates, the total area will be large.
This will degrade the density and power consumption of the integrated circuit. On the other hand, all gates connected to the bus should be of appropriate size, and one gate should be connected to the signal line.
If only one circuit of the present invention is provided, the increase in area will be kept to a minimum.

As explained above, according to the present invention, the IC
It is possible to significantly reduce the signal propagation delay time of signal lines that require high-speed digital signal propagation despite the large load capacity, such as the bus lines of microcomputers that have been
It can be realized with a simple circuit configuration and is extremely valuable especially when applied to digital integrated circuits.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the main points of the present invention, Figure 2 is a specific circuit diagram of an electronic circuit according to an embodiment of the present invention, and Figure 3 is a diagram of output signal waveforms of various parts of the circuit in Figure 2. be. 1...Signal line, 2...V _H detection circuit, 3...V _L
Detection circuit, 8...P channel transistor, 9
...N-channel transistor.

Claims (1)

[Claims] 1. A detection means for detecting the voltage of a signal line transmitting a binary voltage signal, an inflow means for flowing a current into the signal line controlled by the output of the detection means, and an inflow means for flowing a current into the signal line controlled by the output of the detection means; a controlled outflow means for flowing a current from the signal line, the voltage of the signal line being within a predetermined voltage range sandwiched between the first voltage and the second voltage; If the voltage of the signal line exceeds the second voltage range, the inflow means causes current to flow into the signal line only when the voltage of the signal line is within the predetermined voltage range, and the voltage of the signal line falls below the second voltage. An electronic circuit characterized in that, when the voltage of the signal line falls within the predetermined voltage range, the outflow means causes current to flow out from the signal line only when the voltage of the signal line is within the predetermined voltage range. 2. The electronic circuit according to claim 1, wherein the predetermined voltage range includes input logic voltages of all logic circuits whose inputs are connected to the signal line. 3. The electronic circuit according to claim 1, wherein the inflow means and the outflow means are semiconductor switches. 4. Electronic circuit according to claim 3, characterized in that the inflow means are P-channel transistors and the outflow means are N-channel transistors.