JPH07321633A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by speeding up level confirmation when a tri-state buffer is set to a high impedance state with respect to the output buffer circuit providing the output of a digital signal. CONSTITUTION:A tri-state buffer circuit 1 provides the output of an output signal OUT corresponding to an input signal IN or interrupts the output signal OUT to set a high output impedance based on the selection under the control of a control signal CONT. A pull-up resistor Rup or a pull-down Rdwn (not shown) 8 is connected between the output terminal of the tri-state buffer circuit 1 and a high potential power supply VDD or a low potential power supply GND, and when the control signal CONT is changed to designate a high impedance, a switch means 3 conducted for a prescribed time is connected in parallel with the pull-up resistor Rup or the pull-down Rdwn. When the tri-state buffer 1 is set to a high impedance, a stray capacitance C of an output line is charged or discharged via the switch means 3 to confirm the level of the output line at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit which outputs a digital signal. In recent years, semiconductor integrated circuits are required to have higher operating speed and lower power consumption. Therefore, even in the output buffer circuit used in such a semiconductor integrated circuit, it is necessary to increase the operating speed and reduce the power consumption.

[0002]

2. Description of the Related Art Conventional pull-up type output buffer circuit
Is shown in FIG. In Fig. 7 (a) showing the configuration, 1 is 3
Tate buffer circuit, input logic circuit 11 and inverter
It consists of circuit 12. The input logic circuit 11 receives the input signal IN.
NAND gate 11a, NOR gate to which all data is input
11b, NAND gate 11 by inverting the control signal CONT
It has an inverter 11c for a and a NAND gate 11a
Output of NOR gate 11b input by control signal CONT
Are supplied to the inverter circuit 12, respectively. Inverter
The circuit 12 is the + power source V on the high potential side._DD(Eg 5V) and low potential
Connect in series with the ground GND (0V), which is the power supply on the side
Continued PMOSFET Q1, NMOSFET Q2
And the gate of Q1 is a NAND gate 11a
And the output of NOR gate 11b is applied to the gate of Q2.
available. Output is taken from the connection point of Q1 and Q2 to the output terminal.
Output from the printed wiring board wiring, etc.
Connected to the circuit in the subsequent stage. And the inverter circuit 12
The output line when the
To keep "H" level or "L" level,
V _DDBetween the pull-up resistor Rup and the output terminal
Pull-down resistor Rdwn between ground GND (in the figure
(Indicated by a dotted line) are connected. C is a floating parasitic on the output line
It is an equivalent representation of capacity (described below).

Next, the operation will be described with reference to FIG. When the control signal CONT is "L", it is in the normal operation state. When the input signal is "L", the gates of Q1 and Q2 are both
Since it becomes "H", Q1 is off, Q2 is on, "L" is output to the output terminal, and when the input signal is "H",
Since the gates of Q1 and Q2 are both "L", Q1 is on, Q2 is off, and "H" is output to the output terminal.
When the control signal CONT is "H", the gates of Q1 and Q2 are "H" and "L", respectively, regardless of the input signal, so that both Q1 and Q2 are OFF and the output becomes high impedance. When the output becomes high impedance, the stray capacitance C is charged or discharged with a predetermined time constant τ through the pull-up resistor Rup or the pull-down resistor Rdwn, and the potential of the output line is fixed to "H" or "L".

[0004]

By the way, the output of the LSI having such an output buffer circuit is used as the output of the latter stage LSI.
When a plurality of elements are connected in parallel to this output line, such as when designing a printed circuit board for a circuit that drives, the stray capacitance increases due to the input capacitance and wiring capacitance, and when switching to high impedance. In addition, there is a problem that the time τ until the output line is fixed at a predetermined level becomes long. This becomes more remarkable as the number of elements connected to the output line increases and as the wiring length increases, which is a value that cannot be ignored in a logic circuit that processes high-speed data. As a remedy for this, it is conceivable to reduce the resistance value of the pull-up / pull-down resistor to reduce the time constant τ, but if this resistance value is reduced, the output level is deteriorated and the power consumption is increased.

The present invention was created in view of the above problems, and an object thereof is to obtain a high-speed output buffer circuit with low power consumption.

[0006]

FIG. 1 is a block diagram showing the principle of the output buffer circuit of the present invention. In order to solve the above problems, the output buffer circuit of the present invention, as shown in FIG. 1, outputs the output signal OUT corresponding to the input signal IN, or cuts off the output signal OUT to make the output impedance high.
A 3-state buffer circuit 1 that is switched by a control signal CONT, and a pull-up resistor connected between the output terminal of the 3-state buffer circuit 1 and either the high-potential-side power supply _VDD or the low-potential-side power supply GND. Rup or pull-down resistor Rdwn (not shown), and switch means 3 connected in parallel with the pull-up resistor Rup or pull-down resistor Rdwn and conducting for a predetermined time when the control signal changes to specify high impedance. Is configured.

Further, the switch means 3 is operated or not controlled by a select signal SEL from the outside. Furthermore, this switch means is composed of a plurality of switch elements having different current limit values and a circuit for controlling which switch element is operated by a selection signal from the outside.

[0008]

[Function] Pull-up resistor Rup or pull-down resistor Rdw
Since the switch means 3 connected in parallel with n conducts for a predetermined time when the control signal changes to a direction designating high impedance, during that period, the pull-up resistor Rup or the pull-down resistor Rdwn1 is equivalently short-circuited. Become. Therefore, even if the stray capacitance C of the output line is large, the time constant becomes small and the stray capacitance is rapidly charged or discharged,
It is possible to set the output line to a predetermined level in a short time.

Further, a pull-up / pull-down operation by a normal fixed resistor and a forced pull-up / pull-down operation using a switch means can be selected as required by an external control signal.

Furthermore, since it is possible to select which transistor of the switch means is operated, it is possible to change the time until the level is determined as desired. In the case of a circuit configuration in which the charging current passing through the switch element and the power supply current of the 3-state buffer circuit are supplied from a common power supply line, if the operation speed is increased more than necessary and the charging current is increased, the common power supply Although the voltage drop due to the L component parasitic on the line may become large and the threshold value of the 3-state buffer may fluctuate, by making it possible to select an appropriate value suitable for the operating speed of the circuit as described above, This can be prevented.

[0011]

Embodiments of the present invention will be described below with reference to the accompanying drawings. 2 to 6 are views showing an embodiment of the present invention. Note that the same reference numeral represents the same object throughout the drawings.

FIG. 2 is a diagram of a first embodiment of the present invention.
It is an output buffer circuit (a) which performs forced pull-up and its operation waveform (b). In the figure, the portion other than the portion surrounded by the dotted line is a three-state buffer circuit, which includes an input logic circuit 11 and an inverter circuit 12. Rup is a pull-up resistor provided between the output line of the 3-state buffer circuit 1 and the high potential side power source V _DD . The configuration and operation of this part are the same as those of the conventional technique described above with reference to FIG. A switch circuit 31 is a feature of the present invention and corresponds to the switch means 3 in FIG. The switch circuit 31 is connected in parallel with the delay inverter 31a to which the control signal CONT is input, the NAND gate 31b to which the control signal CONT and the output of the delay inverter 31a are input, and the pull-up resistor Rup, and the gate is controlled by the output of the NAND gate 31b. And a PMOSFET Q3.

In the normal operation, when "L" is input as the control signal CONT, "L" and "H" appear on the output line corresponding to "L" and "H" of the input data. Now, when the control signal CONT changes from "L" to "H" while the output is "L", Q1 and Q2 are turned off regardless of the input data. On the other hand, the delay inverter 31a outputs a signal obtained by inverting the control signal CONT after delaying for a predetermined time,
The NAND gate 31b outputs an "L" level pulse signal having a predetermined time width. This "L" pulse signal is given to the gate of Q3, and Q3 becomes conductive for the predetermined time. Therefore, during that period, the power supply voltage of V _DD (for example, + 5V) is connected to the output line, and the stray capacitance C is rapidly charged without passing through the pull-up resistor. After the time corresponding to the "L" pulse width has elapsed, Q
Since the gate of 3 becomes "H", Q3 is turned off, the output line becomes "H" impedance state, and thereafter, the level of the output line is held at "H" through the pull-up resistor Rup.
If the control signal CONT transitions from "L" to "H" while the output is "H" during normal operation, the output line is originally at "H" level, so the above charging operation is continued. Is not done.

Next, FIG. 3 shows an output buffer circuit (a) for forcibly pulling down in the second embodiment of the present invention and its operation waveform (b). In this embodiment, when the output impedance of the 3-state buffer circuit is high, the output line is fixed at "L" level, a predetermined pull-down resistor Rdwn is connected between the output terminal and GND, and A characteristic switch circuit 32 is connected in parallel with the pull-down resistor Rdwn between the output terminal and GND. The switch circuit 32 is a delay inverter 32a to which the control signal CONT is input,
An NM in which the control signal and the output of the delay inverter 32a are connected in parallel with the AND gate 32b and the pull-down resistor Rdwn, and the gate is controlled by the output of the AND gate 32b.
It is composed of OSFET Q3 '. As shown in (b) of the figure,
When the output OUT is "H" and the control signal CONT is "L"
When changing from "H" to "H", Q1 and Q2 turn off regardless of the input data. Meanwhile, the delay inverter 32a
The signal that is the inverse of the control signal CONT is output after a predetermined time delay from the AND gate 32b.
A level pulse signal is output. This "H" pulse signal is given to the gate of Q3 ', and during this predetermined time Q3'.
Conducts. Therefore, during that period, 0V of GND is connected to the output line, and the electric charge stored in the floating capacitance C is rapidly discharged without passing through the pull-down resistor Rdwn. After the time corresponding to the "H" pulse width has elapsed, the gate of Q3 'becomes "L", so Q3' is turned off. This puts the output line in a high-impedance state and the pull-down resistor Rdw thereafter.
The level of the output line is held at "L" via n. When the control signal CONT transitions from "L" to "H" while the output is "L" during normal operation, the output line is originally at "L" level, so the above discharge operation is continued. Is not done.

Next, in the embodiments of FIGS. 4 and 5, the switch circuit 31 'in which a selector is added to the switch circuit of the first embodiment is used to selectively operate the forced pull-up by a select signal SEL from the outside. It was possible.

In FIG. 5, a select signal SE from the outside is supplied.
V _DD and NA are input to the selector 31c that selects and outputs the input with L
It is configured to select the "L" level pulse from the ND gate 31b, and the gate of the PMOS FET Q3 is controlled by the output of the selector 31c. As a result, it is possible to easily select the normal level determining operation using only the pull-up resistor and the rapid level determining operation using the forced pull-up as required. In the case of pull-down operation, between the gate of NNOSFET Q3 'and the AND gate 32b in the second embodiment,
The same can be realized by providing a selector that selects 0V or "H" pulse.

In FIG. 5, a select signal from the outside is used.
Select the input with SEL and output the selector 31d with NAND gate 31
It is provided before b and selects 0V or the control signal CONT by the selector 31d. When 0V is selected, the output of the NAND gate 31b is always at "H" level, so the forced pull-up operation is not performed. If CONT is selected, the operation is similar to that of the embodiment shown in FIG. In the case of the pull-down operation, a forced pull-down operation can be similarly performed by providing a selector for selecting 0V or a control signal in the preceding stage of the AND gate 32b in the embodiment circuit diagram of FIG.

Next, in the embodiment of FIG. 6, the switch circuit 34
Is composed of switch elements having different current values, and any one of them can be appropriately selected. That is, a plurality of PMOS FETs Q that have different drain current values when conducting
3, Q4, Q5 ... Are connected in parallel between the output terminals and V _DD as switching elements, and are configured in advance, and the control signal "L" generated from the common delay inverter 31a and the NAND gate 31b. → Master slice connection of connection circuit 34a in which "L" pulse at "H" change is added to the gate of PMOS FET (Q3 in the figure) with the desired current value, and V _DD is added to the gates of other PMOS FETs. It is formed by. The portion of the switch circuit 43 surrounded by the dotted line is configured by an integrated circuit different from the integrated circuit including the 3-state circuit,
For example, by adding the output lines to output buffer circuits with different stray capacitances and setting the switch elements with appropriate current values corresponding to the stray capacitances to operate, the same time constant is applied to all output lines. You can confirm the level with. In this embodiment, PM of desired current value
Although OSFET (one or more) is selected by the master slice connection, only a desired PMOSFET may be operated by an external selection signal.

[0019]

As described above, according to the present invention, the speed of determining the level of the output line of the output buffer circuit using the 3-state buffer and the low power consumption can be reduced without reducing the resistance value of the pull-up / pull-down resistor. Electrification can be achieved.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of an output buffer circuit of the present invention.

FIG. 2 is a diagram of a first embodiment of the present invention.

FIG. 3 is a diagram of a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a fourth embodiment of the present invention.

FIG. 6 is a configuration diagram of a fifth embodiment of the present invention.

FIG. 7: FIG. 1 of conventional output buffer circuit 1 ... 3-state buffer circuit, 11 ... Input logic circuit, 12 ...
Inverter circuit, 3 ... Switch means, 31, 31 ', 32, 34 ...
Switch circuit, Rup ... pull-up resistor, Rdwn ... pull-down resistor, C ... stray capacitance

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03K 19/017

Claims (4)

[Claims] 1. An output signal (OUT) corresponding to an input signal (IN)
A three-state buffer circuit (1) that switches between outputting the output signal or cutting off the output signal (OUT) and increasing the output impedance by the control signal (CONT), and an output terminal of the three-state buffer circuit (1). A pull-up resistor (Rup) or a pull-down resistor (Rdwn) connected between either the high-potential side power source (V _DD ) or the low-potential side power source (GND), and the pull-up resistor (Rup) or pull-down resistor Resistance (R
dwn) and a switch means (3) which is connected in parallel with the control signal (CONT) and conducts for a predetermined time when the control signal (CONT) changes to a direction designating high impedance. 2. A switch control signal generating section for generating a switch control signal which is active for a predetermined time from a delay element which delays a control signal for a predetermined time and an output of the delay element and a control signal. 2. The output buffer circuit according to claim 1, further comprising: a switch element which is turned on by the active of the switch control signal. 3. The output buffer circuit according to claim 1, wherein whether the switch means is in an operating state or in a high impedance state is selected by a select signal SEL from the outside. 4. The switch means comprises a plurality of switch elements having different current limit values and a circuit for controlling which switch element is operated by an external selection signal. The output buffer circuit according to 1 or 2.