JPS61276024A - Full adder - Google Patents

Abstract

PURPOSE:To secure a wide action voltage margin with a simple circuit by connecting additionally an FET, which is turned on by the inverting signal of one side input signal of exclusive 'or' and 'not' circuits, between an input terminal and an output terminal. CONSTITUTION:Between the input terminal 11 or 12 of the exclusive 'or' and 'not' circuit 6 of respective exclusive OR circuit and an output terminal 10, respective P channels FET 21 and 22 are applied, and the inverting signal of the input signal of the terminal 11 or 12 is given to respective gates. In the constitution, when two input signals are both 1 level, N channels FET 8 and 9 come to be the ON condition and simultaneously, the FET 21 and 22 are also turned ON in which a 0 level to occur as the inverting signal of one side input signal without fail is given to the gate. Thus, since 1 level input appears through the FET 21 and 22 in parallel through the FET 8 and 9 at the terminal 10, 1 signal having the sufficient level can be obtained without being influenced by the threshold voltage of the FET 8 and 9.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a full adder used in adders, multipliers, etc., and particularly relates to a full adder configured using complementary MO8-FETs. .

[Technical background of the invention]

As a full adder of this kind, the applicant of the present application filed a patent application filed in
No. 5395 (% Kaisho 58-211252), 0
It is suitable for configuring a circuit that uses MO8 type FETs (non-complementary R-gate field effect transistors) so as not to consume DC current, and also allows for high integration by reducing the number of elements. We have already proposed a method that reduces the load on signals and enables high-speed operation. That is,
In the full adder shown in FIG. 5, a first input signal A and a second input signal B are input to a first exclusive OR circuit 1, and the output signals (A and B) of this circuit 1 are Third input signal C
are input to the second exclusive OR circuit 2, and the selection circuit 3 selects the first input signal and the second input signal according to the logic level of the output signal of the first exclusive OR circuit 1. Either one of them and the third input signal are selectively extracted. As a result, the output signal of the second exclusive OR circuit 2 becomes the sum signal S.

The output signal of the selection circuit 3 is the carry signal co
obtained as. FIG. 6 shows a truth table representing the operation of such a full adder.

On the other hand, the above full adder is modified as shown in FIG.
If the inverted signal C is input instead of the input signal C of , an inverted sum signal So can be obtained. in this case,
The input signal B, which is one input of the selection circuit 3, is inverted by the CMOS inverter 4, and the output signal of the selection circuit 3 is converted to C.
It is inverted by a MOS inverter 5. A truth table representing the operation of such a full adder is shown in FIG.

Next, a specific example of the full adder shown in FIG. 5 will be described with reference to FIG. 9. 1st. The second exclusive OR circuits 1 and 2 each include an exclusive NOT OR circuit 6 and a CMOS inverter 7. The exclusive NOR circuit 6 has a first conductivity type (
In this example, the first channel (N channel). Second FET 8, 9
The ends of the above are connected together to form the output terminal 10, and the first F
The gate of the ET8 and the other end of the second FET 9 are connected to form the first input terminal 11, and the gate of the second FET 9 and the other end of the first FET 8 are connected to form the second input terminal 11. The input terminal 12 is a fixed potential terminal (1" level power supply potential terminal), and a conductivity type opposite to the first conductivity type (second conductivity type, p channel in this example) is connected between the input terminal 12 and the output terminal 10. Two FETs J'4゜15 are connected in series, and their respective gates are connected to the first and second input terminals 11 and 12, respectively. When the input signals (for example, A, B) of input terminals 11 and 12 of FET 8 are both at '0' level, FET 8.

9 are both off, FETs 14 and 15 are both on, and the output terminal 10 is at the "1#" level.
When input signals A and B are both 1 level, FET 8
, 9 are both on, FET 14 .

15 are both off, and the input signal level "l#" is F.
It appears at the output terminal 10 via ET 8 and ET 9. Also,
One of input signals A and B is at 1" level, the other is '
For 0″ level, FET 8.9 and FET 14
, 15, one of which is in the on state and the other is in the off state.The "0" level, which is one of the input signals A and H, is sent to the output terminal 10 through one of the FETs 8 and 9, which is in the on state. appear.

On the other hand, the selection circuit 3 selects the P channel F of the first set.
ET J 6 and N-channel FET 17 are connected in series, and their interconnection point is used as output terminal 18, and a second set of N-channel FET 19 and P-channel FET is connected.
20 are connected in series and their mutual connection points are connected to the output terminal 18, these two sets of series circuits are connected in parallel, and the third input signals C and C are connected correspondingly to both ends of this parallel circuit. The output signal Bi of the inverter 4 for inversion of the second input signal 8 is applied. Then, each output terminal of the exclusive NOR circuit 6 and the inverter 7 in the first exclusive OR circuit 1 is connected to the first set of FETs 16, 1.
7 and the gates of the second set of FETs 19 and 20.

Therefore, when the gate inputs of the first set of FETs 16 and 17 are '0' and the gate inputs of the second set of FETs 19 and 20 are 1', the FETs 16 and 19 are in the on state, and the FETs 27 and 20 are in the on state. When not in the off state, the output of inverter 4 (inverted signal B of input signal B) is
The signal appears at the output terminal 18 via ET 16 and 19, and the signal at the output terminal 18 is further inverted by the inverter 5. Also, contrary to the above, the first set of FETs 16
, 17 gate input is 1”, second set of FET 19
, 20 gate input is NO'', FET 17,
20 is on, FETs 16 and 19 are off, and the third input signal C appears at the output terminal 18 via the FETs 17 and 20, and the signal at the output terminal 18 is further inverted by the inverter 5. be done. In this way, carry signals co for the three input signals A, B, and C are obtained by the selection circuit 3 and the two inverters 4.about.5.

Note that in the selection circuit 3, FETs 19 and 20
may be omitted.

[Problems with background technology]

By the way, in the exclusive NOR circuit 6 in the first exclusive OR circuit 1, the first . Second input terminal 11.
When the 12 input signals A and B are both at the "1" level, the output terminal 10 logically outputs the "1#" level as described above.

However, considering the actual circuit operation, the "1" level appearing at the output terminal 10 in this case is the first . Second
Since the input signal is supplied from the input terminals 11 and 12 of the N-channel FETs 9 and 8 through the corresponding N-channel FETs 9 and 8, the input signal level is lower than the input signal level 11'' by the threshold voltage vTHN of the N-channel FETs 9 and 8. For example, the input Assuming that the signal level "1" is 5v and 1.5v in vTfIN, the "1" level appearing at the output terminal 10 is approximately 3.5v.
The problem is that it only becomes . In this case, further considering the substrate bias effect of the dark value voltage vT□,
Although it varies depending on the manufacturing method of the element and the device parameters, the 1'' level of the output terminal 1o further decreases from 0.5 V to about 1.5 V, resulting in a completely insufficient value.

The same problem as above occurs in the exclusive NOR circuit 6 in the second exclusive OR circuit 2 when both the input signals at the first and second input terminals 11 and 12 are at the ``''1# level ( , the third input signal C is at the '1' level, and the first and second input signals A and B are a combination of ('1', 'o') or ('O', '1'). This occurs when the output of the first exclusive OR circuit 1 is "1 level".

These problems reduce the stability of the operation of the entire circuit of the full adder, and especially when the operating voltage margin on the low voltage side is narrow, the reliability of the circuit operation decreases. This problem can be solved by assuming that in the exclusive NOR circuit 6, an N-channel FET is used.
Replace 8 and 9 k with P-channel FETs,
Almost the same problem occurs even if the fixed potential applied to the P-channel FETs 14 and 15 is replaced with the ground potential from the power supply potential.

In this case, when the two input signals are both at the 0# level, the ``O#'' level that appears at the output terminal 10 floats away from the ground potential, thereby impairing the reliability of the circuit operation.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and has a simple configuration without sacrificing the features of the 0M08 circuit, which is made up of a relatively small number of elements, such as high-speed circuit operation, low power consumption, and high integration. The present invention provides a full adder that can ensure a wide operating voltage margin.

[Summary of the invention]

That is, in the full adder of the present invention, when the two input signals of the exclusive NOR circuit as described above are both at the ``1# level, the MO# level always exists as an inverted signal of one input signal. Focusing on this, the present invention is characterized in that an FET that enters the Zion state by applying this "0" level to the gate is additionally connected between the first input terminal or the second input terminal and the output terminal. It is something to do.

As a result, “1# level input is added to the output terminal F
Since it appears as a sufficient level via ET, it becomes possible to secure a wide operating voltage margin. Also,
9. The number of additional FETs is small and existing signals can be used to control the additional FETs, so the circuit configuration is simple.9. It is possible to realize a highly integrated circuit while taking advantage of the features of the CMO8 circuit.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. The full adder shown in Figure 1 is an integrated circuit.
Compared to the conventional full adder described above with reference to FIG.
1) The first or second input terminal of the exclusive NOR circuit 6 of the first exclusive OR circuit 1 (in this example, the first input terminal 1
A P-channel FET 21 is added between 1) and the output terminal 10, and an inverted signal of the input signal of the first or second input terminal (in this example, the output signal of the inverter 4) is applied to the gate of this FET 21. (2) The first or second exclusive OR circuit 6 of the second exclusive OR circuit 2
A P-channel FET 22 is added between the input terminal (in this example, the second input terminal 12) and the output terminal 10, and this FET
An inverted signal of the input signal of the first or second input terminal (in this example, the output signal of the exclusive NOR circuit 6 in the first exclusive OR circuit 1 in the previous stage) is applied to the gate of the ET 22. The other points are different, and the other parts are the same as those in FIG. 9, so the same reference numerals are given and the explanation thereof will be omitted.

Next, the addition operation using positive logic in the full adder having the above configuration will be described, but since the operation of the selection circuit 3 is the same as that of the conventional example described above, the explanation thereof will be omitted. In the operation of the exclusive NOR circuit 6, when both of the two input signals are at the 0'' level, the P-channel FETs 2J and 22 are turned off with the 61'' level applied to their gates, unlike the conventional example. Similarly to the operation, the "1" level at the fixed -IT terminal 13 appears at the output terminal 10 as a "1" signal with a sufficient level through the P-channel FETs 14 and 15. ″.

P-channel FETs 21, 22 are turned on in case of a combination of (“0”) or (“O”, “1”).

Regardless of the OFF state, an "O" level appears at the output terminal 10, similar to the conventional operation.On the other hand, when both input signals are at the "1" level, the same operation as the conventional example occurs. The N-channel FETs 8 and 9 are turned on, but at the same time, the P-channel FET whose gate is given the 0'' level, which is always generated as an inverted signal of one of the input signals.
ET 21 and 22 are also turned on. by this,
The 1” level input to output terminal 10 is an N-channel FET.
8, 9 P channel FET 2 in parallel via f
1 and 22, so it is an N-channel FET.
A signal "1#" having a sufficient level can be obtained without being affected by the threshold voltages Va and N of V8 and V9.

Equal logic amplitudes can be obtained, and the operating voltage margin, especially on the low voltage side, which was a problem in the conventional example, has been improved.
Stable operation of the entire circuit can be obtained. Further, the threshold voltage v
Since it is no longer affected by substrate bias effects on THN, circuit operation is no longer affected by device process parameters such as substrate concentration, and the manufacturing margin during mass production is increased. In addition, if the number of elements used in the above full adder is 2 FETs per inverter, the total number of elements used is 22, so it is suitable for high integration and is 9.0M
It becomes industrially possible to realize the features of the O8 configuration, such as low power consumption operation and wide operating voltage margin.

It should be noted that the present invention is not limited to the above embodiment, and if the inverted signal A is input in place of the first input signal A in the full adder shown in FIG. 1, the full adder shown in FIG. As the output signal of the second exclusive OR circuit 2, the sum signal S,
is obtained. A truth table representing the operation of such a full adder is shown in FIG.

In addition, regarding the exclusive NOR circuit 6 in the full adder shown in FIG. 2, the fixed potential terminal 13 is set to the ground potential, and each F
By replacing each ET with one of opposite conductivity type, a negative logic full adder may be constructed as shown in FIG.

Here, 8/ and 9/ are P channel FETs, 14
', 15'.

21' and 22' are N-channel F'ETs, and the other parts are the same as in FIG. 2, so the same reference numerals are given. The operation of the full adder described above is expressed by the truth table shown in FIG. (potential), the P-channel FETs 8', 9' are turned on, and the N-channel FETs 21', 22' are given a "0" level (power supply potential) to their gates.
is also turned on, so the output terminal 10 has a ground potential of 1.
“You get a level.

〔Effect of the invention〕

As mentioned above, according to the full adder of the present invention, the high-speed circuit operation by the CMO8 circuit consisting of a relatively small number of elements;
A wide operating voltage margin can be secured with a simple configuration without sacrificing features such as low power consumption and high integration.
Suitable for use as a component of adders, parallel multipliers, etc.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the full adder of the present invention, FIGS. 2 and 4 are circuit diagrams showing other embodiments of the present invention, and FIG. 5 and 7 are block diagrams showing conventional full adders, respectively, and FIGS. 6 and 8 correspond to FIGS. FIG. 9 is a truth table showing the operation of the full adder shown in the figure, and FIG. 9 is a circuit diagram showing a specific example of the full adder shown in FIG. DESCRIPTION OF SYMBOLS 1...1st exclusive OR circuit, 2...2nd exclusive OR circuit, 3...selection circuit, 4,5.7...inverter circuit, 6...exclusive NOT OR Circuit, 8,9°14
', 15', 21', 22'...N channel F
ET, 8'. 9', 14.15821822...P channel F'E
T. 10... Output terminal, 11... First input terminal, 12
...Second input terminal. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 6

Claims (1)

[Claims] A first exclusive OR circuit that obtains an exclusive OR signal of a first input signal and a second input signal, and an exclusive OR circuit of an output signal of the first exclusive OR circuit and a third input signal. a second exclusive OR circuit for obtaining a signal; and one of the first input signal and the second input signal and the third input signal according to the output signal of the first exclusive OR circuit. a selection circuit that selects and outputs a selection circuit, and obtains a sum signal from the second exclusive OR circuit and a carry signal from the selection circuit; Each of the sum circuits includes an exclusive NOR circuit and an inverter circuit, and the exclusive NOR circuit includes a first FET (field effect transistor) of a first conductivity type and a second FE.
One end of the T is connected to the output terminal, and the first F
The gate of the ET and the other end of the second FET are connected to form a first input terminal, and the gate of the second FET and the other end of the first FE
The other end of the T is connected as a second input terminal, and two FETs of a second conductivity type, which is a conductivity type opposite to the first conductivity, are connected in series between the fixed potential terminal and the output terminal. , each gate of the two FETs is connected to the first input terminal and the second input terminal, and the first input terminal or the second input terminal is connected to the output terminal. between the second
One FET of conductivity type is connected to the gate of the one FET, and the one of the first input terminal or the second input terminal to which the one FET of the second conductivity type is not connected is connected. A full adder characterized in that it provides an inverted signal of an input signal.