JPH0451855B2 - - Google Patents
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- JPH0451855B2 JPH0451855B2 JP60118106A JP11810685A JPH0451855B2 JP H0451855 B2 JPH0451855 B2 JP H0451855B2 JP 60118106 A JP60118106 A JP 60118106A JP 11810685 A JP11810685 A JP 11810685A JP H0451855 B2 JPH0451855 B2 JP H0451855B2
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- 230000005669 field effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は加算器、乗算器等に使用される全加算
器に係り、特に相補型MOS−FETを使用して構
成される全加算器に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a full adder used as an adder, a multiplier, etc., and particularly relates to a full adder configured using complementary MOS-FETs.
この種の全加算器として、本願出願人は特願昭
57−95395号（特開昭58−211252号）により、
CMOS型FET（相補性絶縁ゲート型電界効果トラ
ンジスタ）を用いて直流的電流を消費しないよう
に回路構成するのに好適で、しかも素子数の低減
を図つて高集積化を可能とすると共に入力信号に
体する負荷を低減せしめて高速動作を可能とする
ものを既に提案した。即ち、第５図に示す全加算
器においては、第１の入力信号Ａと第２の入力信
号Ｂとを第１の排他論理和回路１に入力し、この
回路１の出力信号（ＡＢ）と第３の入力信号Ｃ
とを第２の排他論理回路２に入力し、選択回路３
により上記第１の排他論理和回路１の出力信号の
論理レベルに応じて前記第１の入力信号、第２の
入力信号のいずれか一方と前記第３の入力信号と
を選択的に取り出すようにしている。これによ
り、第２の排他論理和回路２の出力信号が和信号
S0として得られ、選択回路３の出力信号が桁上げ
信号C0として得られる。このような全加算器の
動作を表わす真理値表を第６図に示す。
As a full adder of this type, the applicant has
According to No. 57-95395 (Japanese Patent Application Laid-open No. 58-211252),
Suitable for configuring circuits that do not consume direct current using CMOS type FETs (complementary insulated gate field effect transistors), and also enables high integration by reducing the number of elements and input signals. We have already proposed something that reduces the load on the machine and enables high-speed operation. That is, in the full adder shown in FIG. 5, the first input signal A and the second input signal B are input to the first exclusive OR circuit 1, and the output signal (AB) of this circuit 1 and Third input signal C
is input to the second exclusive logic circuit 2, and the selection circuit 3
According to the logic level of the output signal of the first exclusive OR circuit 1, one of the first input signal and the second input signal and the third input signal are selectively taken out. ing. As a result, the output signal of the second exclusive OR circuit 2 becomes the sum signal
The output signal of the selection circuit 3 is obtained as a carry signal C0 . A truth table representing the operation of such a full adder is shown in FIG.
一方、上記全加算器を第７図に示すように変形
し、第３の入力信号Ｃに代えてその反転信号を
入力すると、反転された和信号0が得られるよう
になる。この場合、選択回路３の一方の入力とな
る入力信号ＢをCMOSインバータ４により反転
させ、選択回路３の出力信号をCMOSインバー
タ５により反転させている。このような全加算器
の動作を表わす真理値表を第８図に示す。 On the other hand, if the full adder is modified as shown in FIG. 7 and its inverted signal is input in place of the third input signal C, an inverted sum signal 0 can be obtained. In this case, the input signal B serving as one input of the selection circuit 3 is inverted by the CMOS inverter 4, and the output signal of the selection circuit 3 is inverted by the CMOS inverter 5. A truth table representing the operation of such a full adder is shown in FIG.
次に、上記第７図の全加算器の具体例を第９図
を参照して説明する。第１、第２の排他論理和回
路１，２は、それぞれ排他否定論理和回路６と
CMOSインバータ７とからなる。上記排他否定
論理和回路６は、第１導電型（本例ではＮチヤネ
ル）の第１、第２のFET８，９の一端同志を接
続して出力端子１０とし、上記第１のFET８の
ゲートと第２のFET９の他端とを接続して第１
の入力端子１１とし、上記第２のFET９のゲー
トと第１のFET８の他端とを接続して第２の入
力端子１２とし、固定電位端子（“１”レベルの
電源電位端子）１３と前記出力端子１０との間に
前記第１導電型とは逆導電型（第２導電型、本例
ではｐチヤネル）の２個のFET１４，１５を直
列に接続すると共にその各ゲートを対応して前記
第１、第２の入力端子１１，１２に接続してなる
ものである。したがつて、第１、第２の入力端子
１１，１２の入力信号（たとえばＡ，Ｂ）が共に
“０”レベルの場合、FET８，９は共にオフ状
態、FET１４，１５は共にオン状態になり、出
力端子１０は“１”レベルになる。また、入力信
号Ａ，Ｂが共に“１”レベルの場合、FET８，
９は共にオン状態、FET１４，１５は共にオフ
状態になり、入力信号レベル“１”がFET８，
９を経て出力端子１０に現われる。また、入力信
号Ａ，Ｂのいずれか一方が“１”レベル、他方が
“０”レベルの場合、FET８，９およびFET１
４，１５はそれぞれいずれか一方がオン状態で他
方がオフ状態になり、FET８，９のうちオン状
態の一方を経て入力信号Ａ，Ｂのうちの一方であ
る“０”レベルが出力端子１０に現われる。 Next, a specific example of the full adder shown in FIG. 7 will be described with reference to FIG. 9. The first and second exclusive OR circuits 1 and 2 are respectively an exclusive NOR circuit 6 and
It consists of a CMOS inverter 7. The exclusive NOR circuit 6 connects one ends of the first and second FETs 8 and 9 of the first conductivity type (N channel in this example) to form an output terminal 10, and connects the gate of the first FET 8 and Connect the other end of the second FET9 and
The gate of the second FET 9 and the other end of the first FET 8 are connected to form the second input terminal 12, and the fixed potential terminal (“1” level power supply potential terminal) 13 and the Two FETs 14 and 15 of a conductivity type opposite to the first conductivity type (second conductivity type, p-channel in this example) are connected in series between the output terminal 10 and the gates of the FETs 14 and 15 are connected in series to the output terminal 10. It is connected to the first and second input terminals 11 and 12. Therefore, when the input signals (for example, A and B) of the first and second input terminals 11 and 12 are both at the "0" level, FETs 8 and 9 are both off, and FETs 14 and 15 are both on. , the output terminal 10 becomes "1" level. In addition, when input signals A and B are both at “1” level, FET8,
9 are both on, FET14 and 15 are both off, and when the input signal level is "1", FET8,
9 and appears at the output terminal 10. In addition, when either input signal A or B is at "1" level and the other is at "0" level, FET8, 9 and FET1
One of FETs 4 and 15 is in the on state and the other is in the off state, and the "0" level, which is one of the input signals A and B, is sent to the output terminal 10 through one of the FETs 8 and 9, which is in the on state. appear.
一方、前記選択回路３は、第１の組をなすＰチ
ヤネルFET１６とＮチヤネルFET１７とを直列
に接続すると共にその相互接続点を出力端子１８
とし、第２の組をなすＮチヤネルFET１９とＰ
チヤネルFET２０とを直列に接続すると共にそ
の相互接続点を上記出力端子１８に接続し、これ
らの２組の直列回路を並列に接続し、この並列回
路の両端に対応して第３の入力信号および第２
の入力信号Ｂ反転用のインバータ４の出力信号
を印加する。そして、前記第１の排他論理和回路
１における排他否定論理和回路６およびインバー
タ７の各出力端を対応して上記第１の組のFET
１６，１７のゲートおよび第２の組のFET１９，
２０のゲートに接続している。したがつて、第１
の組のFET１６，１７のゲート入力が“０”、第
２の組のFET１９，２０のゲート入力が“１”
の場合、FET１６，１９がオン状態、FET１７，
２０がオフ状態になり、インバータ４の出力（つ
まり、入力信号Ｂの反転信号）が上記FET１
６，１９を経て出力端子１８に現われ、この出力
端子１８の信号がさらにインバータ５により反転
される。また、上記とは逆に、第１の組のFET
１６，１７のゲート入力が“１”、第２の組の
FET１９，２０のゲート入力が“０”の場合、
FET１７，２０がオン状態、FET１６，１９が
オフ状態になり、第３の入力信号が上記FET
１７，２０を経て出力端子１８に現われ、この出
力端子１８の信号がさらにインバータ５により反
転される。このように選択回路３および２個のイ
ンバータ４，５によつて、３つの入力信号Ａ，
Ｂ，に対する桁上げ信号C0が得られる。なお、
上記選択回路３において、FET１９，２０を省
略してもよい。 On the other hand, the selection circuit 3 connects the P channel FET 16 and the N channel FET 17 forming the first set in series, and connects the interconnection point to the output terminal 18.
and the second set of N-channel FET19 and P
Channel FET 20 are connected in series and their mutual connection point is connected to the output terminal 18, these two series circuits are connected in parallel, and a third input signal and a Second
The output signal of the inverter 4 for inverting the input signal B of is applied. Then, each output terminal of the exclusive NOR circuit 6 and the inverter 7 in the first exclusive OR circuit 1 is connected to the FET of the first set.
16, 17 gates and a second set of FETs 19,
Connected to 20 gates. Therefore, the first
The gate inputs of FETs 16 and 17 in the first set are “0”, and the gate inputs of FETs 19 and 20 in the second set are “1”.
In the case of , FET16 and 19 are on, FET17,
20 is turned off, and the output of inverter 4 (that is, the inverted signal of input signal B) is applied to FET 1.
6 and 19, and appears at the output terminal 18, and the signal at the output terminal 18 is further inverted by the inverter 5. Also, contrary to the above, the first set of FETs
16 and 17 gate inputs are “1”, and the second set of gate inputs is “1”.
When the gate inputs of FET19 and 20 are “0”,
FETs 17 and 20 are on, FETs 16 and 19 are off, and the third input signal is sent to the above FET.
The signal appears at the output terminal 18 via 17 and 20, and the signal at the output terminal 18 is further inverted by the inverter 5. In this way, the selection circuit 3 and the two inverters 4 and 5 select the three input signals A,
A carry signal C 0 for B is obtained. In addition,
In the selection circuit 3, the FETs 19 and 20 may be omitted.
ところで、前記第１の排他論理和回路１におけ
る排他否定論理和回路６において、第１、第２の
入力端子１１，１２の入力信号Ａ，Ｂが共に
“１”レベルのとき、前述したように出力端子１
０には論理的には“１”レベルが出力する。しか
し、実際の回路動作を考えてみると、この場合に
上記出力端子１０に現われる“１”レベルは、第
１、第２の入力端子１１，１２からそれぞれ対応
してＮチヤネルFET９，８を経て供給されてい
るので、入力信号レベル“１”から上記Ｎチヤネ
ルFET９，８の閾値電圧VTHNだけ低い値となる。
たとえば入力信号レベル“１”が5V、VTHN≒
1.5Vであるとすると、出力端子１０に現われる
“１”レベルは約3.5Vにしかならないという問題
がある。この場合、更に、上記閾値電圧VTHNの
基板バイアス効果を考慮すると、素子の製造方
法、デバイスパラメータによつても異なるが、出
力端子１０の“１”レベルはさらに0.5Vから
1.5V程度低下して全く不十分な値になつてしま
う。
By the way, in the exclusive NOR circuit 6 in the first exclusive OR circuit 1, when the input signals A and B at the first and second input terminals 11 and 12 are both at the "1" level, as described above, Output terminal 1
0 logically outputs a "1" level. However, considering the actual circuit operation, the "1" level appearing at the output terminal 10 in this case is transmitted from the first and second input terminals 11 and 12 through N-channel FETs 9 and 8, respectively. Therefore, the input signal level is lower than the input signal level "1" by the threshold voltage VTHN of the N-channel FETs 9 and 8.
For example, if input signal level “1” is 5V, V THN ≒
If the voltage is 1.5V, there is a problem in that the "1" level appearing at the output terminal 10 is only about 3.5V. In this case, if the substrate bias effect of the threshold voltage V THN is taken into account, the "1" level of the output terminal 10 will further increase from 0.5V, although it varies depending on the device manufacturing method and device parameters.
The voltage drops by about 1.5V, which is completely insufficient.
上記と同様な問題は、第２の排他論理和回路２
における排他否定論理和回路６においても第１、
第２の入力端子１１，１２の入力信号が共に
“１”レベルのとき（つまり、第３の入力信号
が“１”レベルであり、かつ第１、第２の入力信
号Ａ，Ｂが（“１”，“０”）または（“０”，“１”
）
の組み合わせであつて第１の排他論理和回路１の
出力が“１”レベルのとき）に生じる。 The same problem as above occurs when the second exclusive OR circuit 2
Also in the exclusive NOR circuit 6 in the first,
When the input signals of the second input terminals 11 and 12 are both at the “1” level (that is, the third input signal is at the “1” level, and the first and second input signals A and B are (“ 1”, “0”) or (“0”, “1”
)
This occurs when the output of the first exclusive OR circuit 1 is at the "1" level).
このような問題により、全加算器の回路全体の
動作の安定性が低下し、特に低電圧側の動作電圧
マージンが狭くなり、回路動作の信頼性が低下す
る。この問題は、前記排他否定論理和回路６にお
いて、仮にＮチヤネルFET８，９をそれぞれＰ
チヤネルFETに置き換え、ＰチヤネルFET１４，
１５へ与える固定電位を電源電位から接地電位に
置き換えてもほぼ同様に発生する。この場合は、
２つの入力信号が共に“０”レベルのときに出力
端子１０に現われる“０”レベルが接地電位から
浮くようになり、やはり回路動作の信頼性が損な
われる。 Such a problem reduces the stability of the operation of the entire circuit of the full adder, particularly narrows the operating voltage margin on the low voltage side, and reduces the reliability of the circuit operation. This problem can be solved by assuming that in the exclusive NOR circuit 6, the N channel FETs 8 and 9 are connected to P
Replaced with channel FET, P channel FET14,
Even if the fixed potential applied to 15 is replaced from the power supply potential to the ground potential, almost the same problem occurs. in this case,
When the two input signals are both at the "0" level, the "0" level appearing at the output terminal 10 floats from the ground potential, which again impairs the reliability of the circuit operation.
本発明は上記の事情に鑑みてなされたもので、
比較的少数の素子からなるCMOS回路による回
路動作の高速性、低消費電力、高集積性等の特長
を損なうことなく、簡易な構成により広い動作電
圧マージンを確保し得る全加算器を提供するもの
である。
The present invention was made in view of the above circumstances, and
To provide a full adder that can secure a wide operating voltage margin with a simple configuration without sacrificing the features such as high-speed circuit operation, low power consumption, and high integration due to a CMOS circuit consisting of a relatively small number of elements. It is.
即ち、本発明の全加算器は、前述したような排
他否定論理和回路の２つの入力信号が共に“１”
レベルのときには必らず一方の入力信号の反転信
号として“０”レベルが存在することに着目し、
この“０”レベルをゲートに与えることによりオ
ン状態になるFETを第１の入力端子または第２
の入力端子と出力端子との間に付加接続しておく
ことを特徴とするものである。
That is, in the full adder of the present invention, the two input signals of the exclusive NOR circuit as described above are both "1".
Focusing on the fact that there is always a "0" level as an inverted signal of one input signal,
By applying this “0” level to the gate, the FET, which is turned on, is connected to the first input terminal or the second input terminal.
It is characterized in that an additional connection is made between the input terminal and the output terminal of.
これによつて、出力端子には“１”レベル入力
が付加FETを経由して十分なレベルとして現わ
れるので、広い動作電圧マージンを確保すること
が可能になる。また、付加FET数は少なくて済
み、付加FETを制御するために既存の信号を利
用できるので、回路構成は簡易なものとなり、
CMOS回路の特長を活かしつつ高集積化回路を
実現することが可能である。 As a result, a "1" level input appears as a sufficient level at the output terminal via the additional FET, making it possible to secure a wide operating voltage margin. In addition, the number of additional FETs is small and existing signals can be used to control the additional FETs, so the circuit configuration is simple.
It is possible to realize highly integrated circuits while taking advantage of the features of CMOS circuits.
以下、図面を参照して本発明の一実施例を詳細
に説明する。第１図に示す全加算器は、集積回路
化されており、第９図を参照して前述した従来の
全加算器に比べて、(1)第１の排他論理和回路１の
排他否定論理和回路６の第１または第２の入力端
子（本例では第１の入力端子１１）と出力端子１
０との間にＰチヤネルFET２１を付加し、この
FET２１のゲートに上記第１または第２の入力
端子の入力信号の反転信号（本例ではインバータ
４の出力信号）を与えるようにした点、(2)第２の
排他論理和回路２の排他論理和回路６の第１また
は第２の入力端子（本例では第２の入力端子１
２）と出力端子１０との間にＰチヤネルFET２
２を付加し、このFET２２のゲートに上記第１
または第２の入力端子の入力信号の反転信号（本
例では前段の第１の排他論理和回路１における排
他否定論理和回路６の出力信号）を与えるように
した点が異なり、その他は第９図中と同じである
ので同じ符号を付してその説明を省略する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. The full adder shown in FIG. 1 is an integrated circuit, and, compared to the conventional full adder described above with reference to FIG. The first or second input terminal (first input terminal 11 in this example) of the sum circuit 6 and the output terminal 1
Add P channel FET21 between 0 and this
The gate of the FET 21 is given an inverted signal of the input signal of the first or second input terminal (in this example, the output signal of the inverter 4); (2) the exclusive logic of the second exclusive OR circuit 2; The first or second input terminal of the sum circuit 6 (in this example, the second input terminal 1
2) P channel FET2 between the output terminal 10 and
2 is added to the gate of this FET22, and the above first
The difference is that an inverted signal of the input signal of the second input terminal (in this example, the output signal of the exclusive NOR circuit 6 in the first exclusive OR circuit 1 in the previous stage) is provided; Since it is the same as in the figure, the same reference numerals are given and the explanation thereof will be omitted.
次に、上記構成の全加算器における正論理での
加算動作を説明するが、選択回路３の動作は前述
した従来例の動作と同じであるのでその説明を省
略する。排他否定論理和回路６の動作のうち、２
つの入力信号が共に“０”レベルの場合にはＰチ
ヤネルFET２１，２２はゲートに“１”レベル
が与えられてオフ状態であり、従来例の動作と同
様に固定電位端子１３の“１”レベルがＰチヤネ
ルFET１４，１５を経て十分なレベルを有する
“１”信号として出力端子１０に現われる。また、
２つの入力信号が（“１”，“０”）または（“０”，
“１”）の組み合わせの場合にはＰチヤンネル
FET２１，２２のオン、オフ状態にかかわりな
く従来例の動作と同様に“０”レベルが出力端子
１０に現われる。これに対して、２つの入力信号
が共に“１”レベルの場合には、従来例の動作と
同様にＮチヤネルFET８，９がオン状態になる
が、同時に一方の入力信号の反転信号として必ら
ず生じている“０”レベルがゲートに与えられて
いるＰチヤネルFET２１，２２もオン状態にな
る。これによつて、出力端子１０には“１”レベ
ル入力がＮチヤネルFET８，９を経由すると並
行してＰチヤネルFET２１，２２を経由して現
われるので、ＮチヤネルFET８，９の閾値電圧
VTHNの影響を受けずに十分なレベルを有する
“１”信号が得られる。 Next, the addition operation using positive logic in the full adder having the above configuration will be described, but since the operation of the selection circuit 3 is the same as that of the conventional example described above, the explanation thereof will be omitted. Of the operations of the exclusive NOR circuit 6, 2
When the two input signals are both at the "0" level, the P channel FETs 21 and 22 are in the off state with the "1" level applied to their gates, and the "1" level at the fixed potential terminal 13 is similar to the operation of the conventional example. passes through the P-channel FETs 14 and 15 and appears at the output terminal 10 as a "1" signal with a sufficient level. Also,
If the two input signals are (“1”, “0”) or (“0”,
P channel in case of combination “1”)
Regardless of whether the FETs 21 and 22 are on or off, the "0" level appears at the output terminal 10 as in the conventional operation. On the other hand, when the two input signals are both at the "1" level, the N-channel FETs 8 and 9 are turned on as in the conventional operation, but at the same time, they are inverted as an inverted signal of one of the input signals. The P-channel FETs 21 and 22 whose gates are given the "0" level also turn on. As a result, the "1" level input appears at the output terminal 10 via the N-channel FETs 8 and 9 and in parallel via the P-channel FETs 21 and 22, so the threshold voltage of the N-channel FETs 8 and 9
A "1" signal with sufficient level can be obtained without being affected by V THN .
したがつて、上記全加算器によれば、排他否定
論理和回路６の出力として供給電源電圧の振幅に
等しい論理振幅が得られるようになり、従来例で
問題となつていた特に低電圧側の動作電圧マージ
ンが向上し、回路全体の安定動作が得られる。ま
た、前記閾値電圧VTHNに対する基板バイアス効
果の影響を受けなくなるので、回路動作は基板濃
度等のデバイス・プロセスパラメータの影響を受
けなくなり、量産時の製造マージンが大きくな
る。また、上記全加算器は、使用素子数がインバ
ータ１個当り２個のFETを使用するものとすれ
ば計22個と少ないので、高集積化に適しており、
CMOS構成により低消費電力動作および広い動
作電圧マージンといつた特長を活かして他の
CMOS回路と組み合わせて大規模なシステム
（たとえば並列形乗算器）を１チツプに構築する
ことが工業的に可能になる。 Therefore, according to the full adder, a logic amplitude equal to the amplitude of the supply power supply voltage can be obtained as the output of the exclusive NOR circuit 6, and the problem with the conventional example, especially on the low voltage side, can be obtained. The operating voltage margin is improved and stable operation of the entire circuit is achieved. Further, since the threshold voltage V THN is no longer affected by the substrate bias effect, the circuit operation is no longer affected by device process parameters such as substrate concentration, and the manufacturing margin during mass production is increased. In addition, the full adder described above uses a small number of elements, 22 in total, if two FETs are used for each inverter, so it is suitable for high integration.
The CMOS configuration takes advantage of features such as low power consumption and wide operating voltage margin.
In combination with CMOS circuits, it becomes industrially possible to construct large-scale systems (for example, parallel multipliers) on a single chip.
なお、本発明は上記実施例に限られるものでは
なく、第１図の全加算器における第１の入力信号
Ａに代えてその反転信号を入力すれば、第２図
に示す全加算器のように第２の排他論理和回路２
の出力信号として和信号S0が得られる。このよう
な全加算器の動作を表わす真理値表を第３図に示
す。 Note that the present invention is not limited to the above-mentioned embodiment, and if the inverted signal of the first input signal A is inputted in place of the first input signal A in the full adder shown in FIG. 1, the full adder shown in FIG. the second exclusive OR circuit 2
A sum signal S 0 is obtained as the output signal. A truth table representing the operation of such a full adder is shown in FIG.
また、上記第２図の全加算器における排他否定
論理和回路６について、固定電位端子１３を接地
電位とし、各FETをそれぞれ逆導電型のものに
置き換えることによつて、第４図に示すように負
論理動作の全加算器を構成してもよい。ここで、
８′，９′はＰチヤネルFET、１４′，１５′，２
１′，２２′はＮチヤネルFETであり、その他は
第２図中と同じであるので同一符号を付してい
る。上記全加算器の動作は第３図に示した真理値
表で表わされるが、その特徴的な点は、排他否定
論理和回路６において２つの入力信号が共に負論
理の“１”レベル（接地電位）の場合に、Ｐチヤ
ネルFET８′，９′がオン状態になると共にゲー
トに“０”レベル（電源電位）が与えられるＮチ
ヤネルFET２１′，２２′もオン状態になるので、
出力端子１０には接地電位の“１”レベルが得ら
れる。 In addition, regarding the exclusive NOR circuit 6 in the full adder shown in FIG. 2 above, by setting the fixed potential terminal 13 to the ground potential and replacing each FET with one of the opposite conductivity type, as shown in FIG. A full adder with negative logic operation may also be configured. here,
8', 9' are P channel FETs, 14', 15', 2
1' and 22' are N-channel FETs, and the others are the same as in FIG. 2, so they are given the same reference numerals. The operation of the full adder described above is expressed by the truth table shown in FIG. (potential), the P channel FETs 8' and 9' turn on, and the N channel FETs 21' and 22' whose gates are given the "0" level (power supply potential) also turn on.
The "1" level of the ground potential is obtained at the output terminal 10.
上述したように本発明の全加算器によれば、比
較的少数の素子からなるCMOS回路による回路
動作の高速性、低消費電力、高集積性等の特長を
損なうことなく、簡易な構成により広い動作電圧
マージンを確保できるので、加算器とか並列乗算
器などの構成要素としての使用に適している。
As described above, the full adder of the present invention has a simple configuration that allows for a wide range of applications without sacrificing the advantages of a CMOS circuit consisting of a relatively small number of elements, such as high-speed circuit operation, low power consumption, and high integration. Since the operating voltage margin can be secured, it is suitable for use as a component of adders, parallel multipliers, etc.
第１図は本発明の全加算器の一実施例を示す回
路図、第２図および第４図はそれぞれ本発明の他
の実施例を示す回路図、第３図は第２図および第
４図の全加算器の動作を示す真理値表、第５図お
よび第７図はそれぞれ従来の全加算器を示すブロ
ツク図、第６図および第８図はそれぞれ対応して
第５図および第７図の全加算器の動作を示す真理
値表、第９図は第７図の全加算器の具体例を示す
回路図である。
１……第１の排他論理和回路、２……第２の排
他論理和回路、３……選択回路、４，５，７……
インバータ回路、６……排他否定論理和回路、
８，９，１４′，１５′，２１′，２２′……Ｎチヤ
ネルFET、８′，９′，１４，１５，２１，２２
……ＰチヤネルFET、１０……出力端子、１１
……第１の入力端子、１２……第２の入力端子。
FIG. 1 is a circuit diagram showing one embodiment of the full adder of the present invention, FIGS. 2 and 4 are circuit diagrams showing other embodiments of the present invention, and FIG. 5 and 7 are block diagrams showing conventional full adders, respectively, and FIGS. 6 and 8 correspond to FIGS. FIG. 9 is a truth table showing the operation of the full adder shown in the figure, and FIG. 9 is a circuit diagram showing a specific example of the full adder shown in FIG. 1... First exclusive OR circuit, 2... Second exclusive OR circuit, 3... Selection circuit, 4, 5, 7...
Inverter circuit, 6... exclusive NOR circuit,
8, 9, 14', 15', 21', 22'...N channel FET, 8', 9', 14, 15, 21, 22
...P channel FET, 10 ... Output terminal, 11
...first input terminal, 12...second input terminal.
Claims (1)
和信号を得る第１の排他論理和回路と、この第１
の排他論理和回路の出力信号と第３の入力信号と
の排他論理和信号を得る第２の排他論理和回路
と、前記第１の排他論理和回路の出力信号に応じ
て前記第１の入力信号および第２の入力信号のい
ずれか一方と前記第３の入力信号とを選択して出
力する選択回路とを具備し、前記第２の排他論理
和回路から和信号を得ると共に前記選択回路から
桁上げ信号を得るようにした全加算器において、
前記２個の排他論理和回路はそれぞれ排他否定論
理和回路とインバータ回路とからなり、上記排他
否定論理和回路は第１導電型の第１のFET（電界
効果トランジスタ）と第２のFETとの一端相互
を接続して出力端子とし、上記第１のFETのゲ
ートと第２のFETの他端とを接続して第１の入
力端子とし、前記第２のFETのゲートと第１の
FETの他端とを接続して第２の入力端子とし、
固定電位端子と前記出力端子との間に前記第１導
電型とは逆導電型である第２導電型の２個の
FETを直列に接続し、この２個のFETの各ゲー
トを対応して前記第１の入力端子および第２の入
力端子に接続し、さらに前記第１の入力端子また
は第２の入力端子と前記出力端子との間に第２導
電型の１個のFETを接続し、この１個のFETの
ゲートに前記第１の入力端子または第２の入力端
子のうち前記第２導電型の１個のFETを接続し
なかつた方の入力信号の反転信号を与えるように
してなることを特徴とする全加算器。1 A first exclusive OR circuit that obtains a first input signal, a second input signal, and an exclusive OR signal;
a second exclusive OR circuit that obtains an exclusive OR signal of the output signal of the exclusive OR circuit and a third input signal; a selection circuit that selects and outputs one of the signal and the second input signal and the third input signal, and obtains the sum signal from the second exclusive OR circuit and outputs the sum signal from the selection circuit. In a full adder designed to obtain a carry signal,
The two exclusive OR circuits each include an exclusive NOR circuit and an inverter circuit, and the exclusive NOR circuit consists of a first FET (field effect transistor) of the first conductivity type and a second FET. One end is connected to each other to form an output terminal, the gate of the first FET and the other end of the second FET are connected to form a first input terminal, and the gate of the second FET and the other end of the second FET are connected to form a first input terminal.
Connect the other end of the FET to the second input terminal,
between the fixed potential terminal and the output terminal, two conductive types having a second conductive type opposite to the first conductive type
FETs are connected in series, each gate of these two FETs is connected to the first input terminal and the second input terminal, and further the first input terminal or the second input terminal is connected to the second input terminal. One FET of the second conductivity type is connected between the output terminal and the gate of the one FET, and one of the first input terminal or the second input terminal is connected to the gate of the one FET. A full adder characterized in that it provides an inverted signal of the input signal to which no FET is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11810685A JPS61276024A (en) | 1985-05-31 | 1985-05-31 | Full adder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11810685A JPS61276024A (en) | 1985-05-31 | 1985-05-31 | Full adder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61276024A JPS61276024A (en) | 1986-12-06 |
| JPH0451855B2 true JPH0451855B2 (en) | 1992-08-20 |
Family
ID=14728162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11810685A Granted JPS61276024A (en) | 1985-05-31 | 1985-05-31 | Full adder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61276024A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0447254A3 (en) * | 1990-03-16 | 1993-07-28 | C-Cube Microsystems | Array multiplier |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58211252A (en) * | 1982-06-03 | 1983-12-08 | Toshiba Corp | Total adder |
-
1985
- 1985-05-31 JP JP11810685A patent/JPS61276024A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58211252A (en) * | 1982-06-03 | 1983-12-08 | Toshiba Corp | Total adder |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61276024A (en) | 1986-12-06 |
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