JPH11284500A - Logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide, in simple circuit configuration, a logic circuit which dispenses with a negative power source and is capable of being held even at power source turn off as well by detecting the state where a logic changes. SOLUTION: This logic circuit is provided with an MOS-FET 10 to be the load of a logic circuit part while controlling a substrate potential corresponding to an input signal, and an MFS-FET 14 to be a holding circuit. MOS-FET 13 to function as a switching circuit for turning off the connection of the source of the MFS-FET and a power source line when generating polarization at that MFS-FET, and logic circuit part having no load part for outputting a logic. For such a circuit, since the structure of sharing the MOS-FET 10 for controlling the substrate potential as the load of the logic circuit part is adopted, the circuit can be provided within a small area in comparison to the conventional examples, and the circuit can be held even at power source turn off as well, by detecting the state where the logic changes without the use of a negative power source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to an MFS-FE using a ferroelectric for a gate insulating film.
The present invention relates to a logic circuit configured using a transistor having a T (MFS: Metal Ferroelectric Semiconductor) structure.

[0002]

2. Description of the Related Art As a circuit for maintaining a signal state even when a power supply is turned off, there is a circuit using an MFS-FET, for example. FIG. 17 shows a structural example generally known as an example of the MFS-FET. FIG. 17A is a cross-sectional structure diagram of an N-channel MFS-FET. P-type substrate (1)
A source (2) and a drain (3), which are N type diffusion regions, are formed. Further, a ferroelectric film (4) is formed between the source (2) and the drain (3) to form a gate insulating film, and a gate electrode (5) is disposed thereon.

Similarly, FIG. 17B shows a P-channel MF
FIG. 2 is a sectional structural view of an S-FET. An N-type well (6) is formed in a P-type substrate (1), and a source (7) and a drain (8), which are P-type diffusion regions, are formed on the well (6). A gate insulating film is formed of a ferroelectric film (4) with the source (7) and the drain (8) interposed therebetween, and a gate electrode (5) is disposed thereon. Although not shown, the source (2), (7), drain (3), and (8) in FIG. 17 are further provided with wiring electrodes, and are connected to other circuits via the electrodes. Connection is made.

As described in detail below with reference to FIG. 3, the ferroelectric substance described above has a polarization characteristic. Once an electric field is applied, remanent polarization remains even when the electric field is returned to zero. To eliminate it, it is necessary to apply an electric field in the opposite direction.
MFS-FE using ferroelectric film having such characteristics
T, for example, in the N-channel MFS-FET of FIG. 17A, when 5 V is applied to the gate electrode (5), a channel is formed between the source (2) and the drain (3), and the channel is brought into a conductive state. At this time, since the P substrate (1) is biased to 0V, the ferroelectric film (4) causes polarization corresponding to the point A in FIG. 3, and after that, even if the gate potential is returned to 0V,
Since it has a remanent polarization corresponding to the point B in FIG. 3, the conduction state is maintained. To make the non-conductive state, a negative potential, for example, -5 V with respect to the potential 0 V of the P substrate (1) is applied to the gate electrode (5).
When the voltage is applied to the ferroelectric film (4), the ferroelectric film (4) causes polarization corresponding to the point C in FIG. 3, and the MFS-FET is turned off. After that, even if the gate potential is returned to 0 V, the non-conducting state is maintained because of the residual polarization corresponding to the point D in FIG.
The operation of the P-channel MFS-FET in FIG. 17B is substantially the same except that the polarity of the potential is reversed, and therefore the description is omitted. As described above, the circuit using the MFS-FET requires two positive and negative power supplies, and the circuit configuration is complicated.

A conventional example of a logic circuit using a ferroelectric film without using a negative power supply is disclosed in Japanese Patent Application Laid-Open No. 9-27191. The above-described conventional circuit is a D flip-flop circuit using a ferroelectric memory element,
It has three operation states: write, read, and standby.
The ferroelectric memory element includes two gates, that is, a control gate and a floating gate, and is configured such that the ferroelectric element is sandwiched between the two gates. In order to surely cause polarization of the ferroelectric element in response to input data during a write operation, a current mirror circuit and some MOS transistors are used to reduce the electric field applied between the two gates. The direction is switched according to the value of the input data.
In addition, in order to reliably read data during a read operation, a current is supplied to the ferroelectric memory element using a constant current source.

[0006]

As described above, when a circuit having a single gate electrode, that is, a so-called MFS-FET structure, is used as a circuit for maintaining a signal state, a ferroelectric element is polarized. The necessity of a negative power supply increases design complexity.

The D flip-flop circuit using a ferroelectric memory device as disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 9-27191 has the following problems. That is, at the time of data write operation, two gates are provided for switching the direction of the electric field applied to the ferroelectric element in accordance with the input data. There are three operating states that change, write / read / standby, and control becomes complicated. For example, during a read operation, the data input terminal
It must be kept at the “H” level. This does not require attention in a normal D flip-flop circuit. Considering these operation controls for a large number of holding circuits used in designing a large-scale logic circuit increases the complexity of the design and also the complexity for inspection such as test patterns. Further, since two gate electrodes are required to sandwich the ferroelectric film, the number of manufacturing steps increases. These problems lead to increases in development costs and product prices.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and does not require a negative power supply. It is an object of the present invention to provide a logic circuit which can be held even when the power is off.

[0009]

Means for Solving the Problems In order to achieve the above object, the present invention is configured as described in the claims. First, according to the first aspect of the present invention, a MOS-FET (for example, 10 in FIG. 1) which controls a substrate potential according to an input signal and serves as a load of a logic circuit unit,
When the S-FET is polarized, a MOS-FET (eg, 13 in FIG. 1) that functions as a switching circuit that turns off the connection between the source and the power supply line, and an MFS-FET (eg, FIG. 14) are all configured as P-channel type. This configuration corresponds to, for example, an embodiment shown in FIG. 1 described later, and the components other than the FET correspond to, for example, the following portions in FIG. That is,
The load is a resistor (15), the first signal input terminal is a res terminal (16), and the second signal input terminal is a res @ terminal (1
9), the output terminal of the signal is an OUT terminal (20), the first power supply terminal is a power supply line (21), the second power supply terminal is a ground line (22), and the logic circuit unit is a MOS-FET (11). 1
This corresponds to the part 2). With the configuration described above, the logic circuit, the substrate potential control circuit, and the ferroelectric memory unit are independently provided in the conventional example, but a part of the logic circuit is shared with the substrate potential control circuit. Because of the structure, it is possible to realize a circuit with a smaller area than the conventional example, and it is possible to detect the state of logic change without using a negative power supply and hold it even when the power is off. I can do it.

Further, according to the present invention, a MOS-FET (for example, 70 in FIG. 7) which controls a substrate potential according to an input signal and serves as a load of a logic circuit portion, and an MFS-FET which serves as a holding circuit are provided. An FET (for example, 74 in FIG. 7) is configured as a P-channel type, and when a MFS-FET is polarized, a MOS-FET (for example, see FIG. 7) that functions as a switching circuit that turns off the connection between its source and a power supply line. 7 of 7
3) is an N-channel type. This configuration corresponds to, for example, an embodiment of FIG. 7 described later. With this configuration, it is possible to directly connect the gate of an N-channel MOS-FET (for example, 73 in FIG. 7) to the first signal input terminal (for example, the res terminal 76 in FIG. 7). Other functions and effects are the same as those of the first aspect.

Further, in the invention according to claim 3,
MOS-FET (eg, 112 in FIG. 9) that controls the substrate potential according to the input signal and serves as a load on the logic circuit unit
And a MOS-FET (for example, 115 in FIG. 9) that functions as a switching circuit that turns off the connection between the source and the power supply line when the MFS-FET is polarized, and an MFS-FET (for example, 9) are all configured as an N-channel type. This configuration corresponds to, for example, an embodiment shown in FIG. 9 described later. Other functions and effects are the same as those of the first aspect.

Further, according to the present invention, a MOS-FET (eg, 152 in FIG. 12) which controls a substrate potential according to an input signal and serves as a load of a logic circuit unit, and an MFS- which serves as a holding circuit are provided. An FET (e.g., 154 in FIG. 12) is configured as an N-channel type, and when the MFS-FET is polarized, a MOS-FET (e.g., FIG. 12 155) is a P-channel type. This configuration corresponds to, for example, an embodiment of FIG. 12 described later. Other functions and effects are the same as those of the second aspect.

The invention described in claim 5 is the first invention.
7 shows a configuration of a logic circuit section in the invention according to claim 4, wherein the OR circuit comprises a plurality of MOS-FETs.
2 shows an example of a circuit and an AND circuit. The OR circuit is described in, for example, FIGS. 1, 7, 9, and 12, and the AND circuit is described in, for example, FIG.

[0014]

According to the present invention, a part of the logic circuit can be shared with the control circuit of the substrate potential, so that the circuit can be realized with a smaller area than the conventional example. In addition, a state in which the logic has changed without using the negative power supply can be detected and held even when the power is off. Furthermore, according to the present invention, the internal state is maintained even when the power is turned off, so that the power of the circuit parts that are not used in a timely manner when the electronic system is operating is turned off, and the power consumption of the entire electronic system is reduced. Becomes possible. When the present invention is applied, it is not necessary to apply the present invention to all the components of the circuit for turning off the power, but it may be applied to a necessary portion such as the last stage of the output portion of the circuit for turning off.

[0015]

(First Embodiment) FIGS. 1 to 4
1 is a diagram showing a first embodiment of the present invention. FIG. 1 is a circuit diagram of a two-input OR logic state detection and holding circuit, FIG. 2 is a partial cross-sectional view of a structure, and FIG. FIG. 4 is a signal waveform diagram in the circuit of FIG.

First, the circuit configuration of FIG. 1 will be described. 2-input O
The R logic state detection and holding circuit is a P-channel MOS-FET
(10), N-channel MOS-FET (11), N-channel MOS-FET (12), P-channel MOS-FE
T (13), a P-channel MFS-FET (14), and a resistor (15). And P-channel MOS-F
ET (10) source and its substrate and P-channel M
The source of the OS-FET (13) and its substrate (N well 32 in FIG. 2) are connected to the power supply line (21), and the gate of the P-channel MOS-FET (10) and the P-channel MOS
Substrate of FS-FET (14) (N well 33 in FIG. 2)
And the res (reset) terminal (16) are connected, and P
A drain of a channel MOS-FET (10), a gate of a P-channel MFS-FET (14),
OS-FET (11) drain and N-channel MOS
The drain of the FET (12) is connected; Also, N
The gate of the channel MOS-FET (11) is connected to an IN terminal 1 (17) which is an input terminal of a logic signal, and the gate of the N-channel MOS-FET (12) is an IN terminal 2 which is an input terminal of another logic signal. (18), the gate of the P-channel MOS-FET (13) is connected to the res￣ terminal (19), and the P-channel MOS-FET (1
3) Drain and P-channel MFS-FET (14)
Of the P-channel MFS-FET (1
The drain of 4) and one end of the resistor (15) are connected to an OUT terminal (20) which is a data output. Further, the source and its substrate of the N-channel MOS-FET (11), the source and its substrate of the N-channel MOS-FET (12), and the other end of the resistor (15) are connected to the ground line (2).
Connected to 2).

In the above circuit, the N-channel MOS-
The FET (11) and the N-channel MOS-FET (12) form a two-input OR circuit,
The FET (10) and the P-channel MFS-FET (14) constitute a logic state detection and holding circuit. The above P
The channel MOS-FET (10) also functions as a load for the two-input OR circuit. Also, P-channel MOS-F
ET (13) uses the P-channel M
It functions as a switching circuit that turns off the connection between the source of the FS-FET (14) and the power supply line (21) (details will be described later). In FIG. 1, a two-input OR circuit is illustrated as the logic circuit unit.
If the channel MOS-FETs are connected in parallel by the number of inputs (each source is connected, the drains are connected), it can be easily configured.

FIG. 2 is a circuit diagram of the circuit shown in FIG.
Channel MOS-FET (13) and P-channel MFS-
It is sectional drawing of the part of FET (14). In FIG.
The P-channel MOS-FET (13) is formed on a P substrate (31), and has an N well (32) and a substrate contact (3).
4), a source (35), a gate oxide film (36),
It comprises a gate electrode (37) and a drain (38).
The P-channel MFS-FET (14) is also a P substrate (3
1) An N-well (33), a substrate contact (39), a source (40), and a ferroelectric film (41)
And a gate electrode (42) and a drain (43).

In the circuit of FIG. 1, the P-channel MOS-
FET (10), N-channel MOS-FET (11),
Although the structures of the N-channel MOS-FET (12) and the resistor (15) are not particularly shown, it is assumed that the device has a device structure made by a general CMOS process. In the description of the connection of the circuit in FIG. 1, the term “substrate” does not refer to the entire substrate (31) shown in FIG. 2, but a portion where each FET is formed (for example, N Wells 32 and 33). The same applies to FETs not shown in FIG.

Here, the polarization characteristics of the ferroelectric will be outlined with reference to FIG. FIG. 3 shows an electric field E applied to the ferroelectric film,
FIG. 4 is a characteristic diagram showing a relationship with polarization P generated in a ferroelectric film. When a certain electric field is applied to the ferroelectric film in the positive direction of the E-axis in FIG. 3, a polarization corresponding to the point A in FIG. 3 is generated in the ferroelectric film. This polarization reduces the applied electric field to zero.
And remains as the remanent polarization and has the value at point B in FIG. Further, when an electric field having a magnitude in the negative direction of the E axis is applied to the ferroelectric film in this state, polarization corresponding to the point C is generated. This polarization remains even when the applied electric field is returned to 0, and has a value at point D in FIG. 3 as remanent polarization.

Next, FIG. 4 shows the res terminal (16), res
￣Terminal (19), IN terminal 1 (17), IN terminal 2 (1
It is a waveform diagram of the input signal of 8), and the output signal of OUT terminal (20). In the following description, the power supply line (2
It is assumed that the power supply voltage VDD is applied to 1). The res @ terminal (19) has a res terminal (1
A signal having the opposite phase to the signal input to 6) is input.

Hereinafter, the circuit operation will be described with reference to FIG. This circuit has two operation states, a reset operation and a detection holding operation. First, the state of the potential of each part of the circuit in the reset operation will be described. The potential level of the res terminal (16) is GND (the res￣ terminal is “H”)
, The P-channel MOS-FET (10) turns on, the P-channel MOS-FET (13) turns off, and the potential level at point a in the figure becomes VDD. At this time, since the substrate potential of the P-channel MFS-FET (14) is GND, an electric field is applied to the ferroelectric film (41) of the P-channel MFS-FET (14), and the P-channel MFS-FET (14)
Polarization such that (14) becomes non-conductive occurs in the ferroelectric film (41) (point C in FIG. 3). Since the P-channel MFS-FET (14) is in a non-conductive state as described above, the potential level of the output OUT terminal (20) becomes GND.
In this state, the circuit has been reset.

Here, the P-channel MOS-FET (1
The switching function according to 3) will be described. When the above polarization is caused, the P-channel MFS-FET (1
4) The connection between the source and VDD is made by a P-channel MOS-
The disconnection using the FET (13) is performed for the following reason. That is, since the source of the P-channel MFS-FET (14) is P-type and the substrate (N-well 33) is N-type, a PN junction exists between them. If the source is set to VDD, the substrate is set to GND when polarization occurs.
This PN junction becomes a forward bias and a large current flows. Therefore, when the reset operation is performed, that is, when the substrate is set to GND, the source of the P-channel MFS-FET (14) is connected to VDD using the P-channel MOS-FET (13).
The connection is turned off.

Next, the state of the potential of each part of the circuit in the detection and holding operation will be described. If the potentials of the IN terminal 1 (17) and the IN terminal 2 (18) remain at GND, the N-channel MOS-FET (11) and the N-channel MOS-FET
Since (12) is off, P-channel MFS-FET
Since the polarization state of (14) does not change and is not conducting,
The potential level of the UT terminal (18) becomes GND.

On the other hand, the potential of the IN terminal 2 (18) is
From VDD to VDD, N-channel MOS-FET (12)
Turns on, and the potential level at point a in the figure becomes GND. At this time, since the potential level of the res terminal (16) is VDD, P
The substrate potential of the channel MFS-FET (14) becomes VDD, and the ferroelectric film (41) of the P-channel MFS-FET (14) is polarized so that the P-channel MFS-FET (14) becomes conductive. (Point A in FIG. 3) occurs. At this time, since the P-channel MOS-FET (13) and the P-channel MFS-FET (14) are conducting, the potential level of the output OUT terminal (20) becomes VDD. Similarly, the same operation is performed even when the potential of the IN terminal 1 (17) changes from GND to VDD. In other words, this circuit is the IN terminal 1
A state in which at least one of (17) and the IN terminal 2 (18) is "H", that is, a two-input OR (logical sum)
Is detected and held.

Further, once the OR output ("H") of the IN terminal 1 (17) and the IN terminal 2 (18) is detected and held, then the IN terminal 1 (17) and the IN terminal 2 (18)
Does not change the potential level of the OUT terminal (20). Because the res terminal (16) in the steady state
Is VDD, the P-channel MFS-FE
The substrate of T (14) also becomes VDD, and even if the point a in the drawing becomes VDD or GND, the P-channel MFS-FET
This is because no polarization occurs in the ferroelectric film (41) such that (14) is turned off.

As described above, in this circuit, the P-channel MF
The substrate potential control circuit for causing polarization in the ferroelectric film (41) of the S-FET (14) is basically composed of only the P-channel MOS-FET (10). And
This transistor is a logic circuit section [in this embodiment, N
Channel MOS-FET (11) and N-channel MOS-
2 input OR circuit composed of an FET (12)]. That is, Japanese Patent Application Laid-Open No. 9-2
In the prior art disclosed in Japanese Patent No. 7191, a logic circuit, a substrate potential control circuit, and a memory unit are independently provided to configure a state detection and holding circuit. Since the structure is shared with the potential control circuit, it is possible to realize a circuit that detects and holds a change in logic state in a smaller area than in the conventional example.

Even if the supply of power is cut off, the polarization state of the ferroelectric film (41) of the P-channel MFS-FET (14) remains, so that the logic state of this circuit is preserved. That is, the state detection and holding circuit according to the present invention can have a function of holding the logic state when the power is off with a smaller area than the conventional example, and does not require a negative power supply.

(Second Embodiment) FIG. 5 and FIG.
FIG. 5 is a diagram showing a second embodiment of the present invention, FIG. 5 is a circuit diagram of a two-input AND state detection and holding circuit, and FIG. 6 is a signal waveform diagram of FIG. The circuit shown in FIG. 5 differs from the circuit shown in FIG. 1 only in that a two-input AND logic is configured in the logic circuit section. That is, N channel M
OS-FET (51) and N-channel MOS-FET (5
2) constitutes a two-input AND circuit, and the other parts are the same as those in FIG. In FIG. 5, reference numeral 50 denotes a P-channel MOS-FET, and 51 denotes an N-channel MOS-FE.
T and 52 are N-channel MOS-FETs, 53 is a P-channel MOS-FET, 54 is a P-channel MFS-FET,
55 is a resistor, 56 is a res terminal, 57 is IN terminals 1, 5
8 is an IN terminal 2, 59 is a res @ terminal, 60 is an OUT terminal, 61 is a power supply line, and 62 is a ground line. In addition,
Here, a two-input AND circuit is illustrated, but three or more inputs may be used. For example, a plurality of N-channel MOS-F
ETs are connected in series (the source of one FET is sequentially connected to the drain of the next FET), and the other end of the source and the substrate of each FET are connected to the ground line (6
2), and each gate may be used as an input terminal for each logic signal.

The operation of this circuit, as shown in FIG.
Both N terminal 1 (57) and IN terminal 2 (58) are VDD
, The potential level of the OUT terminal (60) becomes “H”. The above state is maintained even when the power is turned off, as in FIG.

(Third Embodiment) FIG. 7 and FIG.
FIG. 7 is a diagram showing a third embodiment of the present invention, FIG. 7 is a circuit diagram of a two-input OR state detection and holding circuit, and FIG. 8 is a cross-sectional view showing a partial structure. The difference from the first embodiment is that
N instead of the P-channel MOS-FET (13) in FIG.
That is, a channel MOS-FET (73) is used. That is, in the circuit of FIG. 7, when the reset operation, that is, when the substrate is set to GND, the P-channel MFS-FE
An N-channel MOS-FET (73) is used to cut off the connection between the source of T (74) and VDD. By doing so, the N-channel MOS-F is connected to the res terminal (76).
The gate of the ET (73) can be directly connected. Therefore, the res￣ signal having the opposite phase becomes unnecessary. However, since the N-channel MOS-FET 73 is turned on at the VDD level, the “H” level of the output potential of the OUT terminal 79 is (VDD−Vthn). Where Vthn
Is the threshold value of the N-channel MOS-FET (73).

Further, an N-channel MOS-FET (7
3) and the structure of the P-channel MFS-FET (74) are as shown in the sectional view of FIG. 7 and 8
, 70 is a P-channel MOS-FET, 71 is N
A channel MOS-FET 72 is an N-channel MOS-F
ET, 73 is an N-channel MOS-FET, 74 is a P-channel MFS-FET, 75 is a resistor, 76 is a res terminal,
77 is an IN terminal 1, 78 is an IN terminal 2, 79 is an OUT terminal, 80 is a power supply line, 81 is a ground line, 90 is a P substrate,
91 is a source, 92 is a gate oxide film, 93 is a gate electrode, 94 is a drain, 95 is a substrate contact, 96 is a source, 97 is a ferroelectric film, 98 is a gate electrode, 99 is a drain, 100 substrate contact, 101 is P channel M
An N well serving as a substrate of the FS-FET (74).

Further, in this embodiment, the case where the two-input OR circuit is configured as the logic circuit unit is exemplified, but the two-input AND circuit as shown in FIG. 4 can also be configured. In addition, the same is possible with three or more inputs.

(Fourth Embodiment) FIGS. 9 to 11 are diagrams showing a fourth embodiment of the present invention. FIG. 9 is a circuit diagram of a two-input OR state detection and holding circuit, and FIG. FIG. 11 is a sectional view showing a part of the structure, and FIG. 11 is a signal waveform diagram of the circuit of FIG.
This embodiment shows a configuration in which the P-type and N-type in the first embodiment are inverted. In FIG. 9, a P-channel MOS-FET (110) and a P-channel MOS-FE
T (111) forms a two-input OR circuit. Also,
The N-channel MOS-FET (118) is an N-channel M-FET.
It has both functions of a substrate potential control circuit for causing polarization in the ferroelectric film (135) of the FS-FET (114) and a load transistor of the logic circuit portion. Also, N
The channel MOS-FET (115) corresponds to the P-channel MOS-FET (13) in FIG.

FIG. 10 shows MFS-F of N channels.
ET (114) and N-channel MOS-FET (11
Fig. 5 shows a cross-sectional view of the part. The illustrated structure has a double well structure in which a P well (132) is further provided in an N well (131) provided in a P substrate (130), and a substrate potential of an N channel MFS-FET (114) is set. VDD
The feature is that it can be done.

Note that in FIGS. 9 and 10, 110
Is a P-channel MOS-FET, 111 is a P-channel MO
S-FET, 112 is an N-channel MOS-FET, 11
3 is a resistor, 114 is an N-channel MFS-FET, 115
Is an N-channel MOS-FET, 116 is IN terminals 1 and 1,
17 is the IN terminal 2, 118 is the res terminal, 119 is re
s￣ terminal, 120 is an OUT terminal, 121 is a power supply line, 12
2 is a ground line, 130 is a P substrate, 131 is an N well,
132 is a P well, 133 is a substrate contact, 134 is a drain, 135 is a ferroelectric film, 136 is a gate electrode,
137 is a source, 138 is a substrate contact, 139 is a drain, 140 is a gate oxide film, 141 is a gate electrode,
142 is a source and 143 is a substrate contact.

In the signal waveform in the circuit of FIG. 9, as shown in FIG. 11, the potential of each part of the circuit is opposite to that of FIG. Note that in this embodiment, the logic circuit portion is a two-input OR circuit, but a two-input AND circuit can also be configured. In addition, the same is possible with three or more inputs.

(Fifth Embodiment) FIGS. 12 and 13
12 is a diagram showing a fifth embodiment of the present invention, and FIG.
FIG. 13 is a circuit diagram of a two-input OR state detection and holding circuit, and FIG. In this embodiment, the P-type and the N-type of the first embodiment are inverted, and the MO for reset operation is further changed.
As a S-FET, a P-channel MOS-FET (15
5) is used. With this configuration, r
The P-channel MOS-FET (1) is connected to the es terminal (158).
55) can be directly connected. However, the gate of the P-channel MOS-FET (155) is G
The OUT terminal (15
The “L” level of the output potential in 9) is GND + {Vthp}. Vthp is a P-channel MOS-FET (1
55).

FIG. 13 shows MFS-FE of N channels.
T (154) and P-channel MOS-FET (155)
3 is a structural cross-sectional view of a portion of FIG. In FIG. 13, similarly to FIG. 10, an N-channel MFS-FET (154)
Double well structure (1) so that the substrate potential can be set to VDD.
71 and 172).

In FIGS. 12 and 13, 150 is P
The channel MOS-FET 151 is a P-channel MOS-
FET, 152 is an N-channel MOS-FET, 153 is a resistor, 154 is an N-channel MFS-FET, and 155 is a P-channel MOSFET.
Channel MOS-FETs 156 are IN terminals 1 and 157
Is an IN terminal 2, 158 is a res terminal, 159 is an OUT terminal, 160 is a power supply line, 161 is a ground line, 170 is P
171 is an N well, 172 is a P well, 173 is an N well, 174 is a substrate contact, 175 is a drain, 176 is a ferroelectric film, 177 is a gate electrode, 178
Is the source, 179 is the substrate contact, 180 is the source,
181 is a gate oxide film, 182 is a gate electrode, 183 is a drain, 184 is a substrate contact, and 185 is a substrate contact.

In this embodiment, the logic circuit section is a two-input OR circuit.
A D circuit can also be configured. In addition, the same is possible with three or more inputs.

As described above, the ferroelectric FET
In the conventional logic circuit, the logic circuit unit, the substrate potential control circuit unit, and the holding circuit unit are independently provided to constitute the state detection and holding circuit in the related art. Is shared with the substrate potential control circuit. This makes it possible to realize a state detection and holding circuit with a smaller area than in the conventional example.

In the embodiments described above, the internal state is maintained even when the power is turned off. Therefore, when the electronic system is operating, the power supply of the unused circuit parts is turned off in a timely manner, and the entire electronic system is turned off. Power saving can be achieved.

In the above description, the device structure of the junction separation type has been described as an example. However, the device structure can also be realized with the SOI structure. In this case, the device structure as shown in the fourth and fifth embodiments can be realized. No heavy well structure is required.

A two-input OR circuit is used as a logic circuit part,
The case of a two-input AND circuit has been described, but these are merely examples, and it is of course possible to combine other logic circuits such as NOR, NAND, and EXOR. That is, in the circuits of the above embodiments, other logic may be incorporated as the logic circuit portion.

(Sixth Embodiment) Next, FIGS. 14 and 15 are views showing a sixth embodiment of the present invention.
FIG. 14 is a circuit diagram of the complementary inverter, and FIG. 15 is a signal waveform diagram of the circuit of FIG.

First, the circuit configuration will be described. The portion of the ferroelectric inverter (220) enclosed by the broken line is a P-channel MF
S-FET (209), N-channel MFS-FET (2
10), resistors (212-a) and (212-b), and ferroelectric capacitors (211-a) and (211-b). Then, the P-channel MFS-FET (20
The source and the substrate of 9) are connected to the power supply line (213) and one end of the resistor (212-a), and the P-channel MFS-
The gate of the FET (209) is connected to the other end of the resistor (212-a) and one end of the ferroelectric capacitor (211-a). The source and the substrate of the N-channel MFS-FET (210) are connected to a ground line. (214) and the resistor (212−
b) and connected to one end of an N-channel MFS-FET (2
The gate of 10) is connected to the other end of the resistor (212-b) and one end of the ferroelectric capacitor (211-b), and the other end of the ferroelectric capacitors (211-a) and (211-b). Are connected to the input terminal (215). MFS-F
The drains of ET (209) and (210) are both connected to output terminal (216).

The operation of the circuit of FIG. 14 will be described below with reference to FIG. In the following description, the power supply line (2
It is assumed that a power supply voltage of 5 V is applied to 13). First, the state of the potential of each part of the circuit when the input rises from 0V to 5V will be described. Gp in FIG. 14 indicates a ferroelectric capacitor (211-a) and a resistor (212-a).
When the potential of the input signal is constant, it is 5 V, and when it rises from 0 V to 5 V, the differential circuit shown in FIG.
A differential pulse as shown in FIG. As a result, an electric field is momentarily applied to the ferroelectric film of the P-channel MFS-FET (209), causing polarization such that the P-channel MFS-FET (209) is turned off. Similarly, at the point Gn in FIG. 14, a differential circuit composed of a ferroelectric capacitor (211-b) and a resistor (212-b) causes the voltage to be 0V when the potential of the input signal is constant and 0V → When the voltage rises to 5 V, a differential pulse as shown in FIG. 15 is applied.
As a result, an electric field is momentarily applied to the ferroelectric film of the N-channel MFS-FET (210),
Polarization occurs such that the FET (210) becomes conductive. Therefore, the output terminal (216) changes from 0V to 5V. This logic state indicates that the P-channel MFS-F
ET (209) and N-channel MFS-FET (210)
Is maintained by the polarization of the ferroelectric film.

Next, when the input falls from 5V to 0V, the above operations are all reversed, and the P-channel MFS-FE
T (209) is conductive, N-channel MFS-FET
(210) is turned off. Therefore, the output terminal (21
6) becomes 5V → 0V. This logic state is maintained in the same manner as described above even when the power is turned off.

Thus, the ferroelectric inverter (220)
Performs exactly the same logical operation as a normal inverter, and retains its logical state even when the power supply is cut off. That is, the ferroelectric inverter (220) according to the present invention can maintain a logic state when the power is turned off without a negative power supply or complicated control required in the related art.

(Seventh Embodiment) FIG. 16 is a circuit diagram showing a seventh embodiment of the present invention, and shows an example of a ferroelectric latch circuit. First, the circuit configuration will be described. The portion of the ferroelectric latch circuit (230) surrounded by the broken line is the same as that shown in FIG.
4 shows a ferroelectric inverter (220), a CMOS inverter (221), and a transmission gate (22).
2-a), a transmission gate (222-b). The data input terminal D of the ferroelectric latch circuit (230) is connected to the transmission gate (222).
-B), the other end of the transmission gate (222-b) is connected to one end of the transmission gate (222-a) and the CMOS inverter (22-b).
1) and connected to the input terminal of the CMOS inverter (22).
The output terminal of 1) is connected to the input terminal of the ferroelectric inverter (220), and the output terminal of the ferroelectric inverter (220) is connected to the other end of the transmission gate (222-a) and the ferroelectric latch circuit. (230) is connected to the data output terminal Q. The transmission gate (2
The control terminal of 22-b) has a ferroelectric latch circuit (23
0) is connected to the latch enable terminal G of the ferroelectric latch circuit (230), and the control terminal of the transmission gate (222-a) is connected to G # via the inverter after the latch enable terminal G of the ferroelectric latch circuit (230). Here, G and G￣ indicate that signals of opposite phases are input.

The above-mentioned transmission gate is a P-channel MOS-FET and an N-channel MOS-F
ET are connected in parallel, one gate and the other gate are connected via an inverter, and a P-channel MOS-FET and an N-channel MOS-FET are connected according to a gate signal.
Are switching circuits that are turned on and off at the same time.

Next, the circuit operation will be described. Note that the ferroelectric inverter (220) operates exactly the same as in the sixth embodiment.

First, the latch enable terminal G is "H", that is, the transmission gate (222-b) is on,
When the transmission gate (222-a) is off, the data input terminal D of the ferroelectric latch circuit (230)
Is output to the output terminal of the ferroelectric latch circuit (230) in a through state via the CMOS inverter (221) and the ferroelectric inverter (220).

Next, when the latch enable terminal G is "L", that is, the transmission gate (222-b) is off,
When the transmission gate (222-a) is turned on, the data input to the ferroelectric latch circuit (230) is cut off, and the latch enable terminal G is set to "L" by the CMOS inverter (221) and the ferroelectric inverter (220). The value of the data input terminal D of the ferroelectric latch circuit (230) immediately before the value is held and output to the output terminal of the ferroelectric inverter (220).

In this embodiment, as in the sixth embodiment, since the logic state is maintained in the ferroelectric inverter (220) even when the power is turned off, the ferroelectric latch circuit (230) ) Is naturally retained. As described above, the ferroelectric latch circuit (230) performs exactly the same logical operation as a normal latch circuit, and even if the power supply is cut off without a negative power supply or complicated control required in the prior art, It is possible to maintain that logic state.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a two-input OR state detection and holding circuit according to a first embodiment of the present invention.

FIG. 2 is a structural cross-sectional view of a part of a traffic transistor in the first embodiment.

FIG. 3 is a characteristic diagram showing polarization characteristics of a ferroelectric substance.

FIG. 4 is a signal waveform diagram showing a potential level of each part of the circuit according to the first embodiment.

FIG. 5 shows a two-input AND according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram of a state detection holding circuit.

FIG. 6 is a signal waveform diagram showing a potential level of each part of the circuit according to the second embodiment.

FIG. 7 is a circuit diagram of a two-input OR state detection and holding circuit according to a third embodiment of the present invention.

FIG. 8 is a structural sectional view of a part of a traffic transistor in the third embodiment.

FIG. 9 is a circuit diagram of a two-input OR state detection and holding circuit according to a fourth embodiment of the present invention.

FIG. 10 is a structural sectional view of a part of a traffic transistor in a fourth embodiment.

FIG. 11 is a signal waveform diagram showing a potential level of each part of the circuit according to the fourth embodiment.

FIG. 12 shows a two-input OR according to a fifth embodiment of the present invention.
FIG. 4 is a circuit diagram of a state detection holding circuit.

FIG. 13 is a structural sectional view of a part of a traffic transistor in the fifth embodiment.

FIG. 14 is a circuit diagram of a ferroelectric inverter according to a sixth embodiment of the present invention.

FIG. 15 is a signal waveform diagram showing a potential level of each part of the circuit according to the sixth embodiment.

FIG. 16 is a circuit diagram of a ferroelectric latch circuit according to a seventh embodiment of the present invention.

FIG. 17 shows a P-channel MFS-FET and an N-channel MF
Sectional drawing of the conventional example of S-FET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P substrate 2 ... Source 3 ... Drain 4 ... Ferroelectric film 5 ... Gate electrode 6 ... N well 7 ... Source 8 ... Drain 10 ... P channel MOS-FET 11 ... N channel MOS-FET 12 ... N channel MOS- FET 13 ... P-channel MOS-FET 14 ... P-channel MFS-FET 15 ... Resistance 16 ... res terminal 17 ... IN terminal 1 18 ... IN terminal 2 19 ... res
￣Terminal 20 OUT terminal 21 Power line 22 Ground line 31 P substrate 32 N well 33 N well 34 Substrate contact 35 Source 36 Gate oxide film 37 Gate electrode 38 Drain 39 Substrate contact 40 ... Source 41 ... Ferroelectric film 42 ... Gate electrode 43 ... Drain 44 ... Substrate contact 50 ... P-channel MOS-FET 51 ... N-channel MOS-FET 52 ... N-channel MOS-FET 53 ... P-channel MOS-FET 54 ... P Channel MFS-FET 55 ... resistance 56 ... res
Terminal 57 ... IN terminal 1 58 ... IN terminal 2 59 ... res @ terminal 60 ... OUT
Terminal 61 Power supply line 62 Ground line 70 P-channel MOS-FET 71 N-channel MOS-FET 72 N-channel MOS-FET 73 N-channel MOS-FET 74 P-channel MFS-FET 75 Resistor 76 res Terminal 77 ... IN terminal 1 78 ... IN terminal 2 79 ... OUT
Terminal 80 Power supply line 81 Ground line 90 P substrate 91 Source 92 Gate oxide film 93 Gate electrode 94 Drain 95 Substrate contact 96 Source 97 Ferroelectric film 98 Gate electrode 99 Drain 100 Substrate contact 101 N-well 110 P-channel MOS-FET 111 P-channel MOS-FET 112 N-channel MOS-FET 113 Resistor 114 N-channel MFS-FET 115 N-channel MOS-FET 116 IN terminal 1 117 ... IN
Terminal 2 118 ... res terminal 119 ... re
s￣ terminal 120 OUT terminal 121 power supply line 122 ground line 130 P substrate 131 N well 132 P well 133 substrate contact 134 drain 135 ferroelectric film 136 gate electrode 137 source 138 substrate Contact 139 Drain 140 Gate oxide film 141 Gate electrode 142 Source 143 Substrate contact 150 P-channel MOS-FET 151 P-channel MOS-FET 152 N-channel MOS-FET 153 Resistance 154 N-channel MFS- FET 155: P-channel MOS-FET 156: IN
Terminal 1 157 ... IN terminal 2 158 ... re
s terminal 159 OUT terminal 160 power supply line 161 ground line 170 P substrate 171 N well 172 P well 173 N well 174 substrate contact 175 drain 176 ferroelectric film 177 gate electrode 178 source 179 substrate contact 180 source 181 gate oxide film 182 gate electrode 183 drain 184 substrate contact 185 substrate contact 209 P-channel MFS-FET 210 N-channel MFS-FET 211-a, 211-b strong Dielectric capacitors 212-a, 212-b: Resistor 213: Power line 214: Ground line 215: Input terminal 216 ... Output terminal 220: Ferroelectric inverter 221: CMOS inverter 230: Ferroelectric latch circuit 222-a, 222 -B ... Tran Smission gate

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 H03K 3/356 D 29/792 H03K 3/356 19/20

Claims (5)

[Claims] 1. A first P-channel MOS-FET and a second P-channel MOS-FET.
P-channel MOS-FET and P-channel MFS-F
ET, a load, a first signal input terminal, and a second signal to which a signal having an opposite phase to the signal input to the first signal input terminal is input.
Signal input terminal, signal output terminal, first power supply terminal, second power supply terminal having a different potential from the first power supply terminal, and a logic circuit portion having no load portion for outputting logic And wherein the source and the substrate of the first P-channel MOS-FET and the source and the substrate of the second P-channel MOS-FET are connected to the first power supply terminal; A gate of the first P-channel MOS-FET and a substrate of the P-channel MFS-FET are connected to the first signal input terminal; a drain of the second P-channel MOS-FET; A source of the FET, a drain of the P-channel MFS-FET, and one end of the load connected to the output terminal; a drain of the first P-channel MOS-FET; The gate of the P-channel MFS-FET is connected to the output terminal of the logic circuit unit, and the other end of the load and the power supply terminal of the logic circuit unit are connected to the second power supply terminal. Logic circuit to be characterized. 2. A P-channel MOS-FET, an N-channel MOS-FET, a P-channel MFS-FET, a load, a first signal input terminal, a signal output terminal, a first power supply terminal, A second power supply terminal having a potential different from that of the first power supply terminal, and a logic circuit portion having no load portion for outputting logic; and a source of the P-channel MOS-FET and the substrate; A drain of the N-channel MOSFET is connected to the first power supply terminal; a gate of the P-channel MOSFET; a gate of the N-channel MOSFET;
A source of the N-channel MOS-FET, a source of the P-channel MFS-FET, a drain of the P-channel MFS-FET, a substrate of the FET connected to the first signal input terminal; One end of the load is connected to the output terminal, a drain of the P-channel MOS-FET and a gate of the P-channel MFS-FET are connected to an output terminal of the logic circuit unit, A logic circuit, wherein a substrate of an FET, the other end of the load, and a power supply terminal of the logic circuit unit are connected to the second power supply terminal. 3. A first N-channel MOS-FET and a second N-channel MOS-FET.
N-channel MOS-FET and N-channel MFS-F
ET, a load, a first signal input terminal, and a second signal to which a signal having an opposite phase to the signal input to the first signal input terminal is input.
Signal input terminal, signal output terminal, first power supply terminal, second power supply terminal having a different potential from the first power supply terminal, and a logic circuit portion having no load portion for outputting logic A source of the first N-channel MOS-FET and the substrate, and a source of the second N-channel MOS-FET and the substrate are connected to the second power supply terminal; A gate of the first N-channel MOS-FET and a substrate of the N-channel MFS-FET are connected to the first signal input terminal; a drain of the second N-channel MOS-FET; A source of the FET, a drain of the N-channel MFS-FET, and one end of the load connected to the output terminal; a drain of the first N-channel MOS-FET; The gate of the N-channel MFS-FET is connected to the output terminal of the logic circuit unit, and the other end of the load and the power supply terminal of the logic circuit unit are connected to the first power supply terminal. Logic circuit to be characterized. 4. An N-channel MOS-FET, a P-channel MOS-FET, an N-channel MFS-FET, a load, a first signal input terminal, a signal output terminal, a first power supply terminal, A second power supply terminal having a potential different from that of the first power supply terminal, and a logic circuit portion having no load portion for outputting logic; and a source of the N-channel MOS-FET and the substrate; A drain of the P-channel MOS-FET is connected to the second power supply terminal; a gate of the N-channel MOS-FET; a gate of the P-channel MOS-FET;
A source of the P-channel MOS-FET, a source of the N-channel MFS-FET, a drain of the N-channel MFS-FET, and a substrate of the FET connected to the first signal input terminal. One end of the load is connected to the output terminal, the drain of the N-channel MOS-FET and the gate of the N-channel MFS-FET are connected to the output terminal of the logic circuit unit, and the P-channel MOS -A logic circuit, wherein a substrate of an FET, the other end of the load, and a power supply terminal of the logic circuit unit are connected to the first power supply terminal. 5. The logic circuit section comprises a plurality of MOSFETs, whose sources and drains are connected to each other, one of which serves as the output terminal, the other serves as the power supply terminal, and each gate has a plurality of gates. An OR circuit serving as a logic signal input terminal, or a plurality of MOSFs
ET, the source of one MOSFET is the next MO
An AND circuit sequentially connected to the drains of the SFETs, one of an extreme end source and the other extreme end drain being the output end, the other being the power supply end, and each gate being an input terminal for a plurality of logic signals. The logic circuit according to any one of claims 1 to 4, wherein