JP2001298090A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce leakage current generated in a logical cell in a semiconductor device for lower current consumption. SOLUTION: A semiconductor device is divided into circuit blocks 22. A branch power line 25 for each circuit block 22 is connected to a main power line 23 by a power control circuit 27 having a power switch, which is turned on in response to a signal change of an input signal line to the circuit block 22. During a period other than signal changes, current required to maintain logic is supplied by off current of the power switch and leakage current generated in each circuit block 22 during this period is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device suitable as an LSI constituting a portable telephone, a portable information terminal, etc., which requires low current consumption.

[0002]

2. Description of the Related Art With the miniaturization and high integration of the constituent elements of a semiconductor device, the leak current of each constituent element cannot be ignored. In particular, in LSIs used for mobile phones, personal digital assistants, and the like, a reduction in current consumption is required due to the limitation of power supply capacity. Therefore, there is a particularly strong demand for a reduction in leakage current in constituent elements.

Japanese Patent Application Laid-Open No. Hei 5-206420 discloses a master slice type integrated circuit device for the purpose of reducing current consumption. It is divided into circuit parts that do not need to be operated. A power supply line of a circuit portion which does not need to be temporarily operated is connected to a power supply line via a transistor which is turned on and off by a control signal.
By inputting a control signal from the control signal input terminal, a circuit portion that does not need to operate temporarily is disconnected from the power supply line at that time. As a result, leakage current generated in the circuit portion is reduced, and low current consumption is realized.

Japanese Patent Application Laid-Open No. 9-231756 describes a configuration in which the inside of a DRAM is divided into a plurality of circuit blocks constituting each module, and each circuit block is connected to a power supply line via a MOSFET. Have been.
When power supply to the entire circuit is started, each MOSFET is sequentially turned on by an operation control signal to reduce a peak current generated in the power supply line, and when any of the circuit blocks is in an inactive state. The operation control signal turns off the MOSFET corresponding to the circuit block, disconnects the circuit block from the power supply line, and reduces the current consumption by reducing the leak current.

[0005]

According to the techniques described in the above publications, the inside of an integrated circuit device is divided into a plurality of circuit blocks according to functions, and power is supplied to each functional block or not. Are collectively determined by the operation control signal.

[0006] However, today, as integrated circuit devices have become multifunctional and have a large number of functional blocks accordingly, controlling the activation or deactivation of each circuit block by an operation control signal requires an operation. There is a problem that the control signal itself becomes complicated and a complicated control circuit is required. Here, when the operation control signal is simplified, fine control of each circuit block is not performed, and therefore, a desired reduction in current consumption cannot be obtained.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention does not require a complicated operation control signal, and therefore does not require a complicated control circuit, thereby reducing current consumption by reducing leakage current. Accordingly, an object of the present invention is to provide a semiconductor device which is particularly suitable as an LSI for a portable information terminal or the like.

[0008]

In order to achieve the above object, a semiconductor device according to the present invention has a power supply line connected to a power supply device and a branch power supply line, and power is supplied from the branch power supply line. A logic circuit, a signal change detection circuit for detecting a change in a logic signal of a logic input signal line or a logic output signal line of the logic circuit, and the logic circuit is connected between the power supply line and the branch power line, A power switch that is turned on in response to a change in the logic signal.

According to the semiconductor device of the present invention, when the signal changes, the power supply line and the branch power supply are turned on by the power switch which is turned on in response to the logical signal change of the logical input signal line or the logical output signal line of the logical circuit. Since the line is connected, the current necessary for the logic change of the logic circuit is supplied, but when there is no change in the logic signal, the power switch is turned off, so that no leak current occurs in the logic circuit, or In addition, at least the leakage current can be suppressed, and the current consumption can be reduced.

The semiconductor device of the present invention is not particularly limited, but is required to reduce current consumption more than high-speed operation performance, such as a mobile phone, a portable information terminal, a digital camera, and a notebook. It can be particularly suitably used for portable devices such as portable personal computers, or gas meters, power meters, gas detectors, and the like.

In a preferred semiconductor device according to the present invention, the logic circuit includes a plurality of logic blocks or logic cells, and the signal change detection circuit detects changes in logic signals of a plurality of input signal lines or a plurality of output signal lines in parallel. To detect. In this case, 1
One signal change detection circuit can be shared by a plurality of input signal lines or a plurality of output signal lines.

Further, the semiconductor device according to the present invention is also characterized in that the semiconductor device is divided into a plurality of areas having substantially equal areas, and a set of the branch power supply line and the circuit block is provided for each area. This is a preferred embodiment. The hanging configuration can be particularly suitably adopted for a standard cell type semiconductor device or the like. In this case, it is not necessary to divide the entire chip area of the semiconductor device into a plurality of areas having the same area, and it is sufficient to divide a predetermined range of the area into a plurality of areas having substantially the same area.

It is a particularly preferred embodiment of the semiconductor device according to the present invention that the power switch is turned off after a predetermined time has passed since the power switch was turned on. In this case, complicated control is not required when turning off the power switch.

When a current for maintaining the logic of each logic cell in the logic circuit is required during the period when the power switch is off, the power switch is used to reduce a small amount of logic required for maintaining the logic during the off period. Or a separate switch that keeps the ON state between the power supply line and the branch power supply line, and supplies a small amount of current necessary for maintaining the logic of the logic cell by the other switch. It is preferable to adopt any of the configurations described above.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail based on embodiments of the present invention with reference to the drawings. FIG.
1 shows an overall configuration of a semiconductor device according to an embodiment of the present invention. The semiconductor device 10 is an ASIC configured as a system LSI, and includes an internal circuit area 11 and an external circuit area 12. Internal circuit area 1
Reference numeral 1 denotes a CPU 13 and a memory 14 configured as macro blocks having a predetermined layout, and a UA configured as a module having no predetermined layout.
RT (Universal Synchronous Asynchronous Reciever)
Transmitter) 15, timer 16, and A / D converter 1
7 and other circuit parts 18. Each module 15, 16, 17 and other circuit parts 18
Is composed of standard cells. UART,
It is a serial bus interface that supports both start-stop synchronous and asynchronous systems. In the external circuit area 12,
An input / output buffer (not shown) is arranged.

In this embodiment, the chip area of the semiconductor device 10 is assigned to a macro block 1 having a predetermined arrangement.
In addition to the modules 3 and 14, the modules 15, 16, 17 and other circuit sections 18 constituted by standard cells are also divided according to their arrangement, and the divided circuit sections are used as circuit blocks.

FIG. 2 shows a part of a portion (for example, a circuit portion 18) constituted by standard cells in the semiconductor device of FIG. Various logic cells 2 formed by a combination of standard cells adjacent in the row direction
1 are arranged at random, and a block of a predetermined length of a row of standard cells constitutes one circuit block 22. A main power supply (VDD) line 23 and a main ground (GND) line 24 forming a power supply line are arranged near both ends of each circuit block 22.

In each circuit block 22, a branch VDD line 25 and a branch GND line 26 forming a branch power supply line extend in the row direction, and the branch VDD line 25 and the branch GND line 2
Power is supplied to each logic cell 21 from 6. The branch GND line 26 is directly connected to the main GND line 24. Each circuit block 22 has a pair of power control circuits (power managers) 27, 27 attached to both ends of the circuit block 22 close to each other. Each power supply control circuit 27, 27
Performs the same operation, monitors the signal levels of all input signal lines or output signal lines connected to the corresponding circuit block 22, and when the signal level changes, the main VDD
The line 23 is connected to the corresponding branch VDD line 26.

FIG. 3 shows an example of the circuit block 22 shown in FIG. The illustrated circuit block 22 is a circuit block in which a signal change of an input signal line is detected. The circuit block 22 includes a NAND cell, a NOR cell, a flip-flop (FF) cell, and an inverter (INV).
An input signal line 31 connected to each logic cell 21 is connected to a signal change detection line 33 via a capacitor 32. The branch VDD line 25 and the GND line 26 are not shown.

FIG. 4 is a circuit diagram showing the connection of the inverter cells 21 in the circuit block 22 of FIG. Also,
FIGS. 5A and 5B respectively show the inverter cell 2 of FIG.
1 is a plan view and a sectional view taken along line AA of FIG. An external input signal line 31 is connected to gate electrodes 53 of a pch transistor 51 and an nch transistor 52. A signal detection line 33 common to each cell has a contact 55 with a capacitor diffusion layer 54 of which one electrode forms the other electrode of the capacitor 32 connected to the signal input line 31.
Connected via The diffusion layer 56 of the pch transistor 51 is connected to the nc via drain contacts 57 and 58.
It is connected to the diffusion layer 59 of the h transistor 52 and forms the signal output line 34 of each cell. The diffusion layer 56 of the pch transistor 51 is connected to a branch VDD line 61 via a source contact 60, and the diffusion layer 59 of the nch transistor is connected to a branch GN via a source contact 62.
Connected to D line 63.

As shown in FIG. 5A, the capacitor 32
Has a pair of diffusion layers 54, and these diffusion layers 54
The transistors are provided on both sides of the h transistor 51 and the nch transistor 52. Gate electrodes 53 of pch and nch transistors 51 and 52 are formed in a wide shape above a pair of capacitor diffusion layers 54, and are required to face capacitor diffusion layers 54 via gate oxide films (capacitor oxide films) 64. The capacity is secured. Branch GND
The line 63 is connected to the gate electrode 53 via the interlayer insulating film 65.
, And the upper insulating film 66 further covers it.

FIG. 6 shows another example of the circuit block shown in FIG. The illustrated circuit block 22A is a circuit block in which a signal change of an output signal line is detected. The circuit block 22A includes various logic cells 21 similar to the circuit block 22 shown in FIG.
The output signal line 34 from 1 is connected to the signal change detection line 33 via the capacitor 32. The branch VD
The D line 25 and the GND line 26 are not shown.

FIG. 7 shows an example of the power supply control circuit 27 shown in FIG. The power supply control circuit 27 includes a signal change detection unit 40 that detects a signal change of the signal change detection line 33.
And the main VDD line 23 in response to the detected signal change.
And a power supply switch (switching transistor) 47 connecting the power supply switch (switching transistor) 47 to the branch VDD line 25.

The signal change detection section 40 includes inverters 41 and 42 whose inputs are connected to a signal change detection line 33 (node (a)), and an output node (b) of the inverter 41 connected to a first input. A NAND gate 44 having an output 42 connected to the second input via an output node (c) of the inverter 43; a CR time constant 45 having an input line connected to the output node (d) of the NAND gate 44;
The CR time constant circuit 45 includes an inverter 46 whose input is connected to an output line (node (e)).

The power switch 47 is connected to the signal change detector 40.
Is turned on when the output of the inverter 46 is "H" and turned on when the output is "L". The power switch 47 is designed to supply a desired leakage current during the off period, and supplies a current necessary for maintaining the logic of each logic cell when there is no signal change in the input signal line of the circuit block. I have. During the ON period, a current necessary for a logic change of the logic cell is supplied through a large current.

FIG. 8 is a timing chart of signals in the power supply control circuit 27 responding to changes in the input signal.
The example of FIG. 1 shows a case where the input signal In to the logic circuit repeatedly changes “H” or “L” according to the clock signal. When the logical level of the input signal In on any of the signal input lines 31 of the circuit block 22 changes, the potential of the signal change detection line 33 (node (a)) changes from zero due to capacitive coupling with the signal line 31. It changes transiently in the positive or negative direction. Inverter 41
Is a pulse signal which has an appropriate threshold value for a positive polarity signal generated at the node (a), and becomes "L" for a short time in response to the change of the input signal In from "L" to "H". Is output to the node (b).

The inverter 42 has an appropriate threshold value for the negative signal generated at the node (a), and the inverter 43 receiving the output thereof changes the input signal In from "H" to "L". , A pulse signal which becomes "L" for a short time is output to the node (c). NAND gate 44
Outputs “L” to the node (d) for a short time in response to “L” of both the nodes (b) and (c). As a result, C
The potential of the node “e” forming the output of the R time constant circuit 45 is
It decreases for a predetermined time defined by the CR time constant. The power switch 47 is controlled by the output of the inverter 46 which receives the output of the CR time constant circuit 45 as an input.
The main VDD line and the branch VDD line are connected during the ON period during the ON period. The ON period is longer than the “L” period output from the NAND gate 44 due to the operation of the CR time constant circuit 45.

FIG. 9 is a circuit diagram showing another example of a power supply control circuit including a signal change detection circuit. In the signal detection circuit of FIG. 3, a signal change occurs in a plurality of signal input lines 31,
In addition, when the number of signal lines 31 indicating a signal change from “H” to “L” and the number of signal lines 31 indicating a signal change from “L” to “H” are the same (in such a case) Is considered very rare), no signal change can be detected. The circuit of FIG. 9 overcomes this drawback.

FIG. 9 shows a cell which constitutes a detection target of a change in an input signal and has a branch VDD line 90 and a GND line 101.
, A first detection circuit 71 for detecting a signal change from “L” to “H” on the signal input line 31, and a signal from “H” on the signal input line 31.
An output circuit 73 including a pch transistor 89 for connecting the branch VDD line 90 and the main VDD line 100 based on the outputs of the two detection circuits 71 and 72; , Each detection circuit 71, 7
2, capacitors 74 and 75 for capacitively coupling the corresponding detection circuit 71 or 72 and the input signal line 31;
Charging capacitor 91 for branch VDD line 90
Is shown.

The first detection circuit 71 includes resistors 75 and 76
And the pch transistor 77 and the nch transistor 7
8 and an inverter 79 for inverting the signal of the detection inverter. Capacitor 7
The gate electrode of the detection inverter coupled to the input signal line 31 through 4 is connected to the main VDD line 100 via a 1 MΩ resistor 75 and to the GND line 101 via a 100 MΩ resistor 76. . Resistance 75, 7
6 and the parasitic capacitance of the gate electrode of the detection inverter form a CR circuit.

Pch transistor 77 of detection inverter
And the ratio of the gate width of the nch transistor 78 is 1: 1. Generally, a pch transistor and n
Since the driving capability of the n-channel transistor is approximately twice the driving capability of the p-channel transistor when the gate widths of both transistors are equal, the driving capability of the n-channel transistor 78 is pch
The driving capability of the transistor 77 is 0.5 units. That is, in this detection inverter, the driving ability to lower the output line to the GND level is twice the driving ability to raise the output line to the VDD level. In addition, when the driving capability is similarly evaluated, the pch of the inverter 21 to be detected is determined.
And the driving capability of each of the nch transistors is about 1000.
The unit, the driving capability of the pch and nch transistors of the inverter 79 is 0.5 unit.

The second detection circuit 72 includes resistors 81 and 82
And the pch transistor 83 and the nch transistor 8
4 and a cascade-connected inverter 85, 86 for transmitting a signal of the detection inverter. The gate electrodes of the pch and nch transistors of the detection inverter are capacitively coupled to the signal input line 31 via a capacitor 80 and connected to the main VDD line 100 via a 100 MΩ resistor 81.
It is connected to the GND line 101 via a resistor 82 of Ω.

The driving capabilities of the pch transistor 83 and the nch transistor 84 of the detection inverter of the second detection circuit are 1 unit and 0.5 unit, respectively, based on the above-mentioned criteria. That is, the driving ability to raise the potential to the VDD level is larger than the driving ability to lower the potential to the GND level. The driving capability of each of the inverters 85 and 86 is the same for the pch transistor and the nch transistor.
5 units.

The output circuit 73 has two detection circuits 71,
When the output (node j) of the two-input NAND gate 87 having its output 72 as an input, the inverter 88 having its output as an input, and the inverter (L) becomes "L", the main VDD line 100 and the branch VDD line 90 are connected. And a power switch 89 formed of a pch transistor. N
The driving capability of the pch transistor and the nch transistor of the AND gate 87 is 1.5 units and 3
Is a unit. Also, the pch and nch of the inverter 88
The driving capability of the transistor is 5 units, and the driving capability of the power switch 89 is 50 units.

FIG. 10 is a timing chart showing the operation of the signal detection circuit of FIG. Now, as shown in FIG. 10, when the logic level of the input signal (node k) from the signal input line 31 changes from “H” to “L”, the node h
Decreases from the steady potential VDD / 100 and returns to the steady level after a time corresponding to the CR time constant. When the logic of the signal input line 31 changes, the operation of the inverter 21 inverts the potential of the output node i of the target inverter,
As a result of the cell operation, the potential (node g) of the branch VDD line 90 decreases.

On the other hand, the drop in the potential of the signal line (node h) of the second detection circuit causes the pch transistor and the nch transistor of the detection inverter to be turned off and on, respectively, and the potential of the node j, which is the output line of the output circuit 73, Decreases to “L”. As a result, the power switch 89 is turned on to connect the branch VDD line 90 and the main VDD line 100, so that the branch VDD
The potential at node g on line 90 is restored. When the potential of the node h recovers, the pch transistor 83 and the nch transistor 84 of the detection inverter are inverted, so that the node j is again inverted to “H”. As a result, the power switch 89 is turned off, and the semiconductor device shifts to the leak current reduction mode (leak period).

In the semiconductor device of the present invention, the reduction of the leak current in all the cells for which the change of the input or output signal is to be detected is reduced by the operation current and the operating current of the power supply control circuit including the newly provided signal change detection circuit. By being larger than the leak current, the effect of reducing the current consumption can be obtained. In this regard, the effect of reducing the leakage current has been confirmed by simulation. The simulation of the leak current of the target inverter and the entire power supply control circuit was performed for the case where the number of target inverters 21 was 1000, employing the power supply control circuit of FIG. FIG. 11 shows the simulation result. For comparison, as a conventional circuit, the circuit of FIG. 9 is similar to the circuit of FIG. 9 except that the output of the inverter 88 is open, the pch transistor 47 is always on, and the branch VDD line 90 is always connected to the main VDD line 100. The circuit was simulated for leakage current. FIG. 12 shows the result.

In FIG. 11, an input signal (node k)
Shifts from “H” to “L”, and the branch VDD line becomes the main VDD.
In the leakage period excluding the normal operation period connected to the D line and the subsequent short period, the entire power supply current, that is, the leakage current was about 2.5 μA. In FIG. 12, the leak current during the same leak period was 90 μA. Strictly speaking, the simulated conventional circuit also includes the leak current of the power control circuit. For a strict comparison, it is necessary to exclude the leak current of the power control circuit from this 90 μA. From the simulation results of No. 11, it is at most 2.5 μA and can be ignored. Therefore, the above simulation confirmed the effect of sufficiently reducing the leak current in the present invention.

Although the embodiment of FIG. 9 shows an example in which a signal change of the input signal line of the logic cell is detected and the power switch is operated, the output of the logic cell is changed as in the embodiment of FIG. A configuration in which a signal change in a signal line is detected and power is supplied to a circuit block including the logic cell can also be employed. In this case, the logic cell itself that outputs a signal change needs to operate to some extent beforehand to drive the signal output line to the threshold value of the inverter that detects the change in the output signal. The drive current at this time is covered by the off current of the power switch, and the on current of the power switch is involved only in the subsequent continuous operation of the logic cell. In this case, the logical operation is somewhat delayed as compared with the case where the change in the signal level of the input signal line is detected. However, in mobile phones and the like, the operating speed of the LSI does not matter so much, and therefore, depending on the target device, its signal delay can be tolerated.

Further, the resistance value and the driving ability of the transistor are not limited to the above-mentioned values, but can take various values without departing from the gist of the present invention.

Further, in the embodiment of FIG. 9, an example in which the main VDD line is connected to the branch VDD line by the power switch has been described. However, the semiconductor device of the present invention is not limited to this example, and the main switch is connected by the power switch. Branch GND line GND
A structure in which both the VDD line and the GND line are connected to the branch line by a pair of power switches may be employed.

In the above embodiment, the present invention is applied to a standard cell type ASIC. However, the present invention can be applied to any type of semiconductor device.

As described above, the present invention has been described based on the preferred embodiment. However, the semiconductor device of the present invention is not limited to the configuration of the above-described embodiment, but is based on the configuration of the above-described embodiment. Various modifications and changes are included in the scope of the present invention.

[0044]

As described above, according to the semiconductor device of the present invention, the power supply line and the logic circuit are provided by the power switch responding to the signal change of the logic input signal to the logic circuit or the logic output signal from the logic circuit. , The leakage current generated inside the logic circuit can be reduced without requiring a complicated operation control signal, and thus without using a complicated control circuit. Has the effect of reducing current consumption.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing one circuit portion of the semiconductor device of FIG. 1;

FIG. 3 is a schematic plan view showing one example of a circuit block shown in FIG. 2;

FIG. 4 is a circuit diagram showing connections in the logic cell when the logic cell in FIG. 3 is an inverter.

FIGS. 5A and 5B are a plan view and a cross-sectional view, respectively, showing the structure of the inverter of FIG.

FIG. 6 is a schematic plan view showing another example of the circuit block shown in FIG.

FIG. 7 is a circuit diagram illustrating an example of a signal change detection circuit illustrated in FIG. 2;

FIG. 8 is a timing chart showing signals of the signal change detection circuit.

FIG. 9 is a circuit diagram showing another example of the signal detection circuit.

FIG. 10 is a timing chart showing an operation in the embodiment using the signal detection circuit of FIG. 9;

FIG. 11 is a timing chart showing a simulation result showing a leakage current reduction effect of the present invention.

FIG. 12 is a simulation result of a leak current in a conventional circuit.

[Explanation of symbols]

 10: Semiconductor device 11: Internal circuit area 12: External circuit area 13: CPU 14: Memory 15: UART 16: Timer 17: A / D converter 18: Other circuit parts 21: Logic cells 22, 22A: Circuit block 23 : Main VDD line 24: Main GND line 25: Branch VDD line 26: Branch GND line 27: Power supply control circuit 31: Input signal line 32: Capacitor 33: Signal change detection line 34: Output signal line 41, 42, 43, 46 : Inverter 44: NAND gate 45: CR time constant circuit 47: Power switch 51: pch transistor 52: nch transistor 53: gate electrode 54: capacitor diffusion layer 55: capacitor contact 56: diffusion layer for pch transistor 57, 58: drain contact 59: Expansion for nch transistor Sputtered layers 60, 62: source contact 61: branch VDD line 63: branch GND line 71: first detection circuit 72: second detection circuit 73: output circuit 74, 80: capacitors 75, 76, 82: resistors 77, 83: pch transistors 78, 84: nch transistors 79, 85, 86, 88: inverter 87: NAND gate 89: power switch 90: branch VDD line 91: charging capacitor 100: main VDD line 101: main GND line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/00 H01L 27/08 321L F-term (Reference) 5F038 AV06 BB06 CA03 CD02 CD05 CD08 CD16 DF07 DF08 DF11 DF17 EZ20 5F048 AA07 AB02 AB04 AC03 AC10 BF11 BF16 DA09 5F064 AA04 BB04 BB05 BB06 BB07 BB09 BB19 BB27 BB28 BB37 CC12 CC23 DD25 DD34 EE16 EE52 FF07 5J056 AA00 BB17 BB49 CC00 CC03 DD12 DD28 DD51 DD55 DD51 DD51

Claims (6)

[Claims] 1. A power supply line connected to a power supply device, a logic circuit having a branch power supply line and supplied with power from the branch power line, and a logic input signal line or a logic output signal line of the logic circuit. A signal change detection circuit that detects a change in a logic signal; and a power switch that is connected between the power supply line and the branch power supply line and that is turned on in response to the change in the logic signal. Semiconductor device. 2. The logic circuit according to claim 1, wherein the logic circuit includes a plurality of logic blocks or logic cells, and the signal change detection circuit detects changes in logic signals of a plurality of input signal lines or a plurality of output signal lines in parallel. 3. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the logic circuit is divided into a plurality of areas having substantially equal areas, and the logic circuit is provided for each of the areas. 4. The semiconductor device according to claim 1, wherein said power switch is turned off after a lapse of a predetermined time from being turned on. 5. The power switch supplies a current necessary for maintaining logic of the logic cell in an off state.
The semiconductor device according to claim 1. 6. A switch connected between the power supply line and the branch power line, the switch further comprising a switch which is always on, the switch having a lower current driving capability than the power switch. Item 5. The semiconductor device according to any one of Items 1 to 4.