WO2001024364A1

WO2001024364A1 - Electronic digital circuit operable active mode and sleep mode

Info

Publication number: WO2001024364A1
Application number: PCT/EP2000/009084
Authority: WO
Inventors: Paul R. Van Der Meer
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 1999-09-28
Filing date: 2000-09-15
Publication date: 2001-04-05
Also published as: EP1166444A1; JP2003510941A; KR20010080575A

Abstract

A digital electronic circuit is operable in an active mode and a low power sleep mode. A power interruption transistor interrupts supply current in the sleep mode. The circuit contains a node that retains a voltage representing stored information in both the active mode and the sleep mode. The stored information indirectly controls control electrodes of a low and high threshold storage transistor. The main current channels of the low threshold storage transistor and the power interruption transistor are coupled in series between the node and the power supply connection. The main current channel of the high threshold storage transistor is connected in parallel with the main current channel of the power interruption transistor, to supply current to the node, if necessary, during the sleep mode. Leakage current is reduced by changing the polarity of the gate source voltage of the power interruption between the active mode and the sleep mode and/or by connecting the main current channel of the high threshold transistor to a further node between the main current channels of the low threshold transistor and the power interruption transistor. In an embodiment, the transistors are part of a slave storage cell in a master slave flip-flop and inverters in the storage cell are kept outside the critical timing paths.

Description

Electronic digital circuit operable active mode and sleep mode.

The invention relates to an electronic digital circuit that is operable alternatively in an active mode and a low power sleep mode.

Reduction of power consumption is an important design aspect of digital electronic circuits, especially of digital electronic circuits for use in battery powered equipment. An important reduction of power consumption can be realized by using a low supply voltage. In order to retain sufficient operating speed at low supply voltage, however, transistors with relatively low threshold voltage must be used for processing signals.

Unfortunately, transistors with low threshold voltage suffer from subthreshold leakage current.

When such a transistor is logically "off a zero voltage difference is applied between its gate and source and the main current channel of the transistor should not conduct. But with a low threshold a subthreshold leakage current will flow even in this "off state. This increases power consumption.

In the IEEE journal of solid state circuits, Vol. 30, No. 8, August 1995 an article has been published titled "1-V Power supply high speed digital circuit technology with multithreshold- voltage CMOS", by Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya,

Takahiro Aoki, Satoshi Shigematsu and Junzo Yamada (Mutoh et al.). Mutoh et al. describe how power consumption due to subthreshold leakage current can be reduced by operating the circuit alternatively in an active mode or in a sleep mode. The circuit contains a power interruption transistor. In the sleep mode the power interruption transistor interrupts the connection between part of the circuit and the power supply. Thus, power consumption due to subthreshold leakage current is minimized in the sleep mode, which is the mode in which the circuit operates most of the time.

Mutoh et al. use a power interruption transistor is manufactured to have a higher intrinsic threshold voltage than the other transistors in the circuit. Thus, the power interruption transistor does not suffer from the high subthreshold leakage current of the other transistors. The higher intrinsic threshold may be realized during manufacturing of the circuit by additional mask and implantation steps. Alternatively, different thresholds may be realized by creating gate oxides of different thickness for high and low threshold transistors. The circuit described by Mutoh et al. also contains storage circuits, such as flip- flops. The storage circuits receive power both in the active mode and the sleep mode, in order to preserve information stored in those storage circuits also in the sleep mode. The transistors in the storage circuit are manufactured to have a higher intrinsic threshold. Thus, the storage circuits consume less subthreshold leakage current. However, the higher threshold causes the problem that too little current flows in the "on" state. When a transistor is logically "on" the supply voltage difference is applied between its gate and source and the main current channel of the transistor should conduct. But with a high threshold voltage the power supply voltage applied to the gate is not much above the threshold, so that little current flows through the main current channel in the "on" state. This reduces the speed of the circuit and it limits the possibilities of raising the threshold.

Mutoh et al. speed up the storage circuits by including an additional inverter with low threshold transistors in parallel with an inverter with high threshold transistors in the storage circuits. The additional inverter is connected to the power supply via a high threshold power interruption transistor, which interrupts power supply to the additional inverter in the sleep mode. The additional inverter provides higher speed in the active mode and does not consume significant power in the sleep mode.

It is an object of the invention to speed up a digital electronic circuit with such a storage circuit that uses transistors with different intrinsic thresholds.

The circuit according to the invention is described in Claim 1. According to the invention, the power interruption transistor and a storage transistor that sustains the stored information during the sleep mode by drawing current in parallel with the power interruption transistor are each adapted in a different way in to realize the reduction of subthreshold leakage current. The stored information controls control electrodes of the low and high threshold storage transistor, usually indirectly via an inverter. One storage transistor has a high intrinsic threshold to reduce leakage current. Current through the power interruption transistor is controlled by its gate-source voltage. Current leakage through the power interruption transistor is reduced by giving opposite polarity to the gate-source voltage in the sleep mode and the standby mode respectively. Thus, with the same amount of leakage, a power interruption may have a lower threshold than the storage transistor that is connected in parallel with the power interruption transistor. This increases the speed of the circuit.

In case of an NMOS power interruption transistor for example, the gate-source voltage is positive in the active mode and negative in the sleep mode. A negative gate-source voltage is realized for example by connecting the source to the negative power supply connection and boosting the gate voltage below the voltage at the power supply connection. Alternatively, the gate may be connected to the negative power supply connection and the source to a node that carries a higher voltage than the negative power supply. In case of a circuit with PMOS transistors the polarities are reversed as compared with the circuit with NMOS transistors.

An embodiment of the circuit according to the invention is described in claim 2. This embodiment contains a master-slave flip-flop with a slave storage cell that contains a pair of cross-coupled inverters that both contain transistors as described in claim 1. Information from a master storage cell of the flip-flop is passed to further circuits via a connection path. The slave storage cell is attached to the connection path, so that the slave storage cell can hold information on the connection path, but the connection path does not run through the inverters of the slave storage cell. Thus, information transmission from the master storage cell to the further circuits does not suffer from an increase in delay due to the use of the high threshold transistors in the inverters. Preferably high threshold transistors are used to bridge power interruption transistors substantially only in storage cells that need to preserve information in the sleep mode. Other circuits, which do not need to preserve information in the sleep mode, are preferably substantially all disconnected from the power supply without a remaining current path through a high threshold transistor in parallel with the power interruption transistor. Thus, a maximum of power is saved with a minimum of additional transistors.

Also preferably, the storage cell comprises two complementary parts connecting the node that stores information to respective power supplies, each part containing storage transistors as claimed in claim 1. Thus, power is saved upon return to the active mode both when the node stores a logic low level and when the node stores a logic high level. As a result twice as much power is saved on average with the two parts as with only a single part. In addition, power is saved because internal unpowered nodes will assume a voltage between the power supply voltages, so that less power is needed to recharge these nodes upon return to the active mode. In an embodiment of the circuit according to the invention, the power interruption transistor has its source and drain connected to the source and drain of the high threshold storage transistor respectively. Them main current channel of a low threshold storage transistor is connected between the drains on one hand and a node whose voltage represents the stored information on the other hand, so that the main current from the node can flow through the low threshold storage transistor to the main current channel of either the power interruption transistor or the high threshold storage transistor or both. The voltage on the node controls both the low and high threshold storage transistors (indirectly via another inverter). Because the storage transistors will either both conduct or both block current at the same time, the main current channel of the high threshold storage transistor does not need to be connected directly to the node that stores information. When the leakage current must flow through the storage transistors in series instead of in parallel this reduces the leakage current. Additionally, this may simplify the layout of the circuit. Also, the main current channel of other transistors may be included in series with the low threshold storage transistor for various functional purposes, without interference from the high threshold storage transistor.

These and other advantageous aspects of the circuit according to the invention will be described in more detail using the following figures.

Figure 1 shows a circuit with a master slave flip-flop; Figure 2 shows an inverter for use in a storage element.

Figure 1 shows a circuit with a master slave flip-flop. The circuit contains an input gate 10, a master storage element 12, an intermediate gate 14, a slave storage element 16, power interruption transistors 17a,b, a booster circuit 18 and further circuits 19. The master storage element 12 comprises a first inverter 120 with an input coupled to an output of the input gate 10 and an output coupled to an input of the intermediate gate 14. The master storage element 12 comprises a second inverter 122 with an input and output coupled to the output and input of the first inverter 120 respectively. The second inverter 122 is a gated inverter. The intermediate gate 14 is a gated inverter and has an output coupled to the further circuits 19 and the slave storage element 16. The power supply connections of the input gate 10, the inverters 120, 122 in the master storage element 12, the intermediate gate 14 and the further circuits 19 are connected to the overall power supply power connections Vss, Vdd via the main current channel of the power interruption transistors 17a,b respectively. The booster circuit 18 has an output connected to the gate of the power interruption transistors 17a,b.

The slave storage element 16 contains a cross-coupled first and second inverter 160a,b. The inverters 160a,b each contain an output node 161a,b, coupled to a first power supply connection Vss via the main current channels of a first storage transistor 163a,b and a further power interruption transistor 170a, 171a in series with one another. The node 161a,b is also coupled to the first power supply connection Vss via the main current channel of a second storage transistor 164a,b, in parallel with the power interruption transistor 17a. The node 161a,b is connected to a second power supply connection Vdd via a circuit 166a,b (including further power interruption transistors 170b, 171b) that is a complementary version of the circuit with the first and second storage transistor 163a,b 164a,b and the further power interruption transistors 170a, 171a. The output node 161a of the first inverter 160a is coupled to the gates of the first and second storage transistors 163b, 164b of the second inverter 160b. The output node 161b of the second inverter 160b is coupled to the gates of the first and second storage transistors 163 a, 164a of the first inverter 160a. The output node 161b of the second inverter 160b is coupled to the output of the intermediate gate 14. The second inverter 160b differs from the first inverter 160a in that a gating transistor 168 is included, with a main current channel between the output node 161b and the main current channels of the first and second storage transistors 163b, 164b.

The second storage transistors 164a,b have higher intrinsic thresholds than other transistors in the circuit, in particular higher than the first storage transistors 163a,b and power interruption transistors 17a, 170a, 171a. This may be realized for example by including additional implantation steps in a manufacturing process for manufacturing an integrated circuit that contains the circuit of figure 1. Thus, different concentrations of doping atoms may be realized for the second storage transistors 164a,b on one hand and for other transistors including the first storage transistors 163a,b on the other hand, which leads to different intrinsic thresholds. Alternatively, different thresholds may be realized by creating gate oxides of different thickness for high and low threshold transistors.

Although only a single master/slave storage element 12, 16 is shown in figure 1 for reasons of clarity, normal circuits will of course contain many of these storage elements. In operation, the storage elements 12, 16 perform a two-phase storage function. A phase signal

0 indicates the phase and controls the gated inverters. In a first phase, the input gate 10 is enabled, the second inverter 122 of the master storage element 122 is disabled, the intermediate gate 14 is disabled and the gating transistor 168 is made conductive, as well as its counterpart in the complementary circuit 166b. In the first phase slave storage element holds the data at the output of the intermediate gate 14 for use in the further circuits 19 at a time when data in the master storage element is changed. In the second phase, input gate 10 is disabled, second inverter 122 in the master storage element 12 is enabled, intermediate gate 14 is enabled and gate transistor 18 as well as its counterpart in the complementary circuit 166b is made conductive. In the second phase the master storage element 12 holds data for use by the further circuits 19.

In operation, the circuit can operate alternatively in an active mode and a sleep mode. In the active mode, the booster circuit 18 applies a voltage Vdd to the gate of the power interruption transistors 17a, 170a, 171a that connect circuits to the first power supply Vss. Similarly, a voltage Vss is applied to the gate of the power interruption transistors 17b, 170b, 171b that connect circuits to the second power supply Vdd. Thus, the main channels of the power interruption transistors will conduct and the circuits connected to the power interruption transistors 17a,b, 170a,b, 171a,b will operate.

In the sleep mode, the booster circuit 18 applies a voltage below Vss to the gate of the power interruption transistor 17a, 170a, 170b that connect circuits to the first power supply Vss. Preferably, the boosted voltage is 100 to 800 millivolt below Vss, typically 400 to 500 millivolt. Larger voltages will lead to increased gate induced leakage currents. If different thresholds are realized by using a gate oxides of different thickness, a wider range of gate voltages may be used. Similarly, the booster circuit 18 applies a voltage above Vdd to the power interruption transistors 17b, 170b, 171b that connect circuits to the second power supply Vdd. Thus, power supply to the circuit connected to the power interruption transistors 17a,b will be interrupted and the circuits will normally stop operating. Subthreshold current leakage through the power interruption transistors 17a,b 170a,b, 171a,b is reduced by boosting their gate voltage outside the power supply range. The use of the booster circuit 18 does not slow down the circuit in the active mode, because the booster circuit 18 does not need to be switched on and off during operation in the active mode.

The slave storage element 16 retains stored information also in the sleep mode. The second storage transistors 164a,b are connected to the power supply Vss in parallel with the power interruption transistors 170a, 171a. Therefore, the main current channel of these transistors 164a,b can conduct current even in the sleep mode if a high gate source is applied (dependent on the stored data). Similarly, the complementary circuits 166a,b are able to draw current in parallel with the power interruption transistors 170b, 171b (with an opposite dependence on the stored data). The gate transistor 18 is kept conductive. As a result, the slave storage element 16 also retains data in the sleep mode. The power interruption transistors 170a,b, 171a,b used for the storage transistors 163a,b are preferably connected to the first storage transistors 163a,b separate from the connection between the power interruption transistors 17a,b and combinatorial circuits, like the further circuits 19. This prevents a parasitic current to those combinatorial circuits from the power supply connections Vdd, Vss via the second storage transistors 164a,b, the output nodes 161a,b, and the first storage transistors 163a,b successively. Instead of separate power interruption transistors 170a,b, 171 a,b for the different inverters 160a,b a shared power interruption transistor may be used for these inverters 160a,b, but this will also increase parasitic leakage currents, although to a lesser extent than for power interruption transistors shared with many combinatorial circuits. Because the second storage transistors 164a,b are in parallel and not in series with the power interruption transistor 17a, these second storage transistors 164a,b will conduct subthreshold leakage currents also in the sleep mode, which might lead to high power consumption. By using second storage transistors 164a,b with a high threshold the subthreshold leakage current of the second storage transistors 164a,b is reduced. According to the invention similar combinations of high and low threshold transistors as storage transistors 163a,b, 164a,b are used in the complementary circuits 166a,b. However, even without such transistors in the complementary circuit 160a,b the subthreshold leakage current would already be reduced by half due to the high threshold in second storage transistors 164a,b.

Use of the high threshold for these transistors 164a,b will make them operate slower than a lower threshold transistor of equal size, but this problem is reduced since no switching is needed in the sleep mode and since first storage transistors 163a,b with a lower threshold are present that can perform the same data retention function as the second storage transistors 164a,b on their own in the active mode.

In addition, the slave storage element 16 is provided outside the critical timing path from the master storage element 12 to the further circuits 19. The signal path from the intermediate gate 14 to the further circuits 19 short circuits the path from an input of the inverters 160a,b to an output of these inverters 160a,b. Thus, the time needed to propagate to propagate signal changes from an input of the inverters 160a,b to an output of these inverters 160a,b does not significantly affect the time needed for propagating those signal changes from the master storage element 12 to the further circuits 19. This reduces any slowdown of this time due to the use of higher threshold in the second storage transistors 164a,b.

Of course, the invention is not limited to the embodiment of figure 1. For example, if increased delay from the slave storage element 16 is not a problem, one of the inverters 160a,b of the slave storage element 16 may be incorporated in the signal path from the master storage element 12 to the further circuits 19, just as the inverters 120, 122 in the master storage element are shown as part of the signal path between the input gate 10 and the intermediate gate 14. Furthermore, although a single power interruption transistor 17a,b has been shown for the entire circuit of figure 1 , separate power interruption transistors 17a,b may be provided for separate circuits. Instead of a booster circuit 18 that boosts the gate voltage of the power interruption transistors 17a,b beyond the power supply voltage, a circuit that may be used that brings the gate voltages substantially at the power supply voltages, but shifts the source voltage of the power interruption transistors 17a,b to within the supply voltage range. Thus, the same effect is reached of changing the sign of the gate-source voltage in the sleep mode as compared to the active mode.

Instead of cross-coupled inverters 160a,b other cross-coupled inverting circuits, like NAND gates may be used. In this case, several low threshold transistors may be used in the inverting circuit in addition to the first storage transistors 163a,b, for performing a combinatorial logic function. The main current channels of all low threshold transistors should preferably be coupled to the power supplies Vss, Vdd only via the main current channel of at least one of the power interruption transistors 17a,b. High threshold transistors may be provided as companions for some of the low threshold transistors, bridging the power interruption transistors 17a,b so as to ensure that a functional equivalent of a current that would flow through a low power transistor when the power interruption transistor 17a,b conducts will flow through a high threshold transistor when the power interruption transistor 17a,b does not conduct. This can be realized for example by providing a respective high threshold transistor as a companion for every low threshold transistor in the slave storage element as far as those low threshold transistors are connected directly to the main current channel of a power interruption transistor 17a,b. The drains of the low threshold transistor and its companion high threshold transistor are coupled together and the source of the high threshold transistor is coupled to the power supply. As a result the main current channel of the high threshold transistor bridges the series connection of the main current channels of the power interruption transistor and its companion low threshold transistor. Also, although the gates of the first and second storage transistor 163a,b, 164a,b are shown directly connected to one another, the gates may of course be connected other ways. It suffices that the first storage transistors 163a,b (with a lower threshold) function to store data in at least the active mode and the second storage transistors 164a,b (with a high threshold) function to retain that data in at least the sleep mode. The voltage supplied to the gate of the first storage transistors 163a,b in the sleep mode is not relevant for the function of the circuit. Similarly, the second storage transistors 164a,b may be kept non-conductive during the active mode without affecting the function of the circuit. Separate connections for driving the gates of the first and second storage transistors 163a,b, 164a,b for realizing the cross- coupling of the inverters 160a,b in different ways.

Figure 2 shows an alternative inverter 20 for use instead of inverter 160a,b of figure 1. The inverter 20 contains a first storage transistor 22, a second storage transistor 23, a power interruption transistor 24, a complementary circuit 26, an output node 27 and a further node 29. The second storage transistor 23 has a higher intrinsic threshold than the first storage transistor 22 and the power interruption transistor 24. The output node 27 forms the output of the inverter 20. The output node 27 is coupled to the further node 29 via the main current channel of the first storage transistor 22. The further node 29 is coupled to a first power supply connection Vss via the main current channels of the second storage transistor 23 and the power interruption transistor 24 in parallel. The gates of the first and second storage transistors 22, 23 are connected to one another and form the input of the inverter 20. The complementary circuit 26 is coupled between the output node 27 and the second power supply Vdd and is complementary to the circuit of the first and second storage transistor 22, 23 and the power interruption transistor.

In operation the inverter of figure 2 can be used alternatively in the active mode and the sleep mode. In the active mode the power interruption transistor 24 is conductive. As a result the first storage transistor 22 (low threshold) mainly determines the operation of the inverter, the current through its main current channel being drained mainly by the power interruption transistor 24. In the sleep mode, the power interruption transistor 24 is made non- conductive. Preferably the gate source voltage of the power interruption transistor has opposite signs in the active mode and the sleep mode, so that little subthreshold leakage current will flow through the power interruption transistor 24 in the sleep mode.

The current through the main current channel of the first storage transistor depends on the data stored in the storage element, i.e. on its state. In the sleep mode the current from the main current channel of the first storage transistor 22, if any, is drained via the main current channel of the second storage transistor 23 (high threshold voltage). By using a high threshold for the second storage transistor 23 there will be less subthreshold leakage current. The layout of the inverter 20 provides an alternative to that of the inverter 160a because the main current channel of the second storage transistor 23 is not connected to the output node 27. As a result less leakage current will flow in the inverter of figure 2. In the circuit of figure 1 , leakage current will flow through the main current channels of the first and second storage transistor in parallel, whereas in the circuit of figure 2 the leakage current will flow through the main current channels in series. The series connection reduces the leakage current. Of course, the series connection may also decrease the speed of the circuit, but this is usually not critical, so that minimum size transistors may be used. Dependent on the context in which the inverter is used, this may also have layout advantages. An inverting circuit with a combinatorial function, such as a NAND gate, may be used instead of the inverter of figure 2. In this case one high threshold transistor for each power interruption transistor 24 suffices, with drains and sources of the high threshold transistor connected to the drain and source of the power interruption transistor 24. However, for each inverter a separate power interruption transistor 24 is needed.

In summary, a low power storage circuit 16 can be realized by using a power interruption transistor 17a,b, 24, of which the gate source voltage alternate signs in an active mode and a sleep mode respectively, in parallel with a second storage transistor 164a,b with a raised intrinsic threshold whose gate source voltage is controlled dependent on the stored data. Although the invention has been illustrated in the context of a master slave flip- flop, it can of course be applied to other storage circuits, such as SRAM memory cells as well.

Claims

CLAIMS:

1. A digital electronic circuit that is operable in an active mode and a low power sleep mode, the circuit comprising

- a power supply connection;

- a power interruption transistor for conducting and interrupting current from the supply connection in the active mode and the sleep mode respectively;

- a control voltage supply circuit for applying a control voltage to the power interruption transistor so that the control voltage has mutually opposite signs in the operating mode and the sleep mode;

- a storage circuit comprising a node, a low threshold storage transistor and a high threshold storage transistor, the high threshold storage transistor having been manufactured to have higher intrinsic threshold than the low threshold storage transistor, the node retaining a voltage representing stored information in both the active mode and the sleep mode, the stored information controlling control electrodes of the low and high threshold storage transistor at least in the active mode and in the sleep mode respectively, main current channels of the low threshold storage transistor and the power interruption transistor being coupled in series between the node and the power supply connection, a main current channel of the high threshold storage transistor being connected between the node and the power supply connection in parallel with the main current channel of the power interruption transistor.

2. A digital electronic circuit according to claim 1 , the storage circuit comprising a master storage cell, a gated transmission circuit, a slave storage cell, a connection path and further circuits, the master storage cell being coupled to the slave storage cell through the gated transmission circuit, the slave storage cell comprising a pair of cross coupled inverters, the first and second inverter each comprising a high and low threshold transistor coupled according to claim 1, the connection path connecting an output of the gated transmission circuit to the further circuits, the node being connected to the connection path for feeding the stored information to the further circuits, the connection path running through neither the first nor the second inverter.

3. A digital electronic circuit according to claim 1, comprising a further node between the main current channel of the low threshold storage transistor and the main current channel of the power interruption transistor, the main current channel of the high storage threshold transistor being coupled between the further node and the power supply connection.

4. A digital electronic circuit according to claim 1 wherein the main current channel of the high threshold transistor is coupled in parallel with the main current channels of both the low threshold transistor and the power interruption transistor.

5. A digital electronic circuit according to Claim 4, the storage circuit being one of a plurality of identical storage circuits that share the power interruption transistor.

6. A digital electronic circuit according to claim 1 , the storage cell comprising two complementary parts connecting the node to respective power supplies, each part containing transistors as claimed in claim 1.

7. A digital electronic circuit that is operable in an active mode and a low power sleep mode, the circuit comprising

- a power supply connection; - a power interruption transistor for conducting and interrupting current from the supply connection in the active mode and the sleep mode respectively;

- a storage circuit comprising a node, a further node, a low threshold storage transistor and a high threshold storage transistor, the high threshold storage transistor having been manufactured to have higher intrinsic threshold than the low threshold storage transistor and the power interruption transistor, the node retaining a voltage representing stored information in both the active mode and the sleep mode, the stored information controlling control electrodes of the low and high threshold storage transistor at least in the active mode and in the sleep mode respectively, a main current channel of the low threshold storage transistor, the further node and a main current channel of the power interruption transistor being coupled successively in series between the node and the power supply connection, a main current channel of the high threshold storage transistor being connected between the further node and the power supply connection in parallel with the main current channel of the power interruption transistor.

8. A digital electronic circuit according to claim 7, the storage circuit comprising a master storage cell, a gated transmission circuit, a slave storage cell, a connection path and further circuits, the master storage cell being coupled to the slave storage cell through the gated transmission circuit, the slave storage cell comprising a pair of cross coupled inverters, the first and second inverter each comprising a high and low threshold transistor coupled according to claim 1, the connection path connecting an output of the gated transmission circuit to the further circuits, the node being connected to the connection path for feeding the stored information to the further circuits, the connection path running through neither the first nor the second inverter.