JPH0253965B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip-flop circuit using MIS type transistors, and particularly to a high-speed, low-power consumption bistable flip-flop circuit.

Bistable flip-flops are memory ICs or LSIs.
It is used not only as a basic unit for configuring memory cells, but also as a constituent element of registers or latch circuits that temporarily store data in logic circuits. For this reason, the characteristics generally required of bistable flip-flops (hereinafter simply referred to as flip-flops) include high speed, low power consumption, and small occupied area. Conventionally, this type of circuit has been realized by cross-coupling the input and output of an inverter circuit consisting of two single-conductivity channel MIS transistors (Fig. 1), but this configuration always involves one or the other. The inverter consumes current, and this current needs to be increased to achieve high speed. Therefore, in this type of flip-flop, high speed and low power consumption are contradictory conditions. In this respect, the CMOS type flip-flop shown in FIG. 2 does not statically consume power, so it can satisfy both high speed and low power consumption. However, since CMOS type circuits use a mixture of p-channel and n-channel transistors, the manufacturing process becomes complicated. Another disadvantage is that it occupies a large area because it requires special isolation between elements.

To explain this point in more detail, the conventional flip-flop shown in FIG.
Consists of MIS transistors 31 to 34, power supply 3
Two inverters each consisting of transistors 31, 32 and 33, 34 connected in series between transistors 5 and 36 are cross-coupled. In the figure, E/D is shown as an example.
type circuit, thus transistors 31,
The transistors 33 are depletion type and are always on, and the transistors 32 and 34 are enhancement type and turn on or off depending on whether the gate voltage is above or below a certain positive value. As a result of the cross-coupling of these two inverters, this flip-flop will, for example, turn on transistor 32 and turn off transistor 34, producing a low level at output 37 and a high level at output 38. The disadvantage of this type of flip-flop is that even in a static state, the DC current path of transistors 31 and 32 (transistor 3
4 is on the opposite side), so power is always consumed. Moreover, this current value is closely related to the operation settings of the transistors, and in order to speed up the operation of the flip-flop, it is necessary to lower the resistance of the load depletion transistors 31 and 33. On the other hand, this increases the power consumption. invite

FIG. 2 is an example of a conventional flip-flop using a CMOS circuit, with transistors 41,
43 is p-channel MIS type FET, transistor 4
2 and 44 are n-channel MIS type FETs. One of the two stable states of this circuit is when transistor 42 is on, transistor 43 is also on, and transistors 41 and 44 are off. Therefore, statically there is no direct current path, power consumption is only to compensate for some leakage current, and in principle it does not exist. For this reason, flip-flops using CMOS circuits do not statically consume power even if the resistance of the load transistor is reduced in order to increase speed, so the time average of power consumption is extremely small.
However, as mentioned above, since the CMOS circuit includes MIS transistors of two conductivity type channels, p-channel and n-channel, there are many problems in the manufacturing process.

The present invention improves these drawbacks of conventional flip-flops, dramatically reduces the static power consumption of flip-flops composed of only single-conductivity type MIS transistors, and satisfies both high speed and low power consumption. It is equipped with two single-conductivity channel MIS type transistors, and connects the gate of a depletion type transistor similar to an enhancement type transistor connected to the positive terminal of the power supply to the positive input terminal and the negative terminal of the power supply. Four transistor pairs are connected in parallel between the positive and negative terminals of the power supply, with the gate of the enhancement type transistor to be connected as the negative input terminal, and the series connection point of these transistors as the output terminal, and the negative input terminal of the first transistor pair. , the positive input terminal of the second transistor pair, the output terminal of the fourth transistor pair, and the first
the positive input terminal of the transistor pair, the negative input terminal of the second transistor pair, the output terminal of the third transistor pair, and the output terminal of the first transistor pair, the positive input terminal of the third transistor pair, and the fourth The negative input terminal of the transistor pair, the output terminal of the second transistor pair, the negative input terminal of the third transistor pair, and the positive input terminal of the fourth transistor pair are connected, respectively. This will be explained in detail below with reference to the illustrated embodiments.

FIG. 3 is a circuit diagram showing one embodiment of the present invention.
In this example, a flip-flop circuit is composed of n-channel MIS type transistors 1 to 8 of single conductivity type. Transistors 1, 3, 5, and 7 are connected in series with transistors 2, 4, 6, and 8, respectively, to form transistor pairs _T1 to _T4 . Each of the transistor pairs T ₁ to _{T 4} operates as an inverter, and is connected in parallel between the positive terminal 9 and the negative terminal 10 of the power supply. Transistor 1, 3, 5, 7
Each gate of transistors T ₁ to _{T 4} is a positive input terminal (a terminal that produces an H output at an H input), and each gate of transistors 2, 4, 6, and 8 is their negative input terminal (a terminal that produces an H output at an H input). (terminal that produces L output)
It is. And the series connection point of each transistor pair T ₁ to _{T 4} , for example, for T ₁ , transistor 1,
The series connection point p of 2 is an output terminal. These transistor pairs T ₁ to _{T 4} connect the output terminals of the first transistor pair T ₁ to transistors 5, 8 by line 11.
and the output terminal of the fourth transistor pair T ₄ is connected by line 14 to each gate of transistors 3 and 2.
and connect the output terminal of the second transistor pair T ₂ by line 12 to each gate of transistor 6,
7 and further connect the output terminal of the third transistor pair T ₃ by a line 13 to each gate of transistors 4,
Connect to each gate of 1.

The flip-flop circuit constructed as described above is bistable, and in one stable state, transistors 2, 3, 6, and 7 are on and transistors 1, 4, 5, and 8 are off. As is clear from Fig. 3, this happens because line 14 is H and line 1 is
If 1 is low, transistors 2 and 3 are on and transistors 5 and 8 are off, so line 12 is high and transistors 6 and 7 are on, and line 13 is low and transistors 4 and 1 are off. In the other stable state, transistors 1 to 8 are all reversed. That is, if line 11 is high and line 14 is low, transistors 5 and 8 are on and transistors 3 and 2 are off, so line 13 is high and transistors 4 and 1 are on, and line 12 is low and transistors 6 and 7 are on. is turned off.

The transition operation between these stable states is performed in the same way as a normal flip-flop, but the operation is dynamic. That is, a large current flows during the transition, but the current is limited to an extremely small amount after the transition.
The small current flow after this transition is to ensure stable operation, and for this purpose, transistors 1, 3, 5, and 7 are made to be depletion type, albeit slightly, that is, even if the voltage between the gate and source is zero, Allow a drain current on the order of μA to flow.
Transistors 2, 4, 6, and 8 are of the enhancement type. If the transistors 1, 3, 5, and 7 are also of the enhancement type, the advantage of zero current after transition can be obtained as in the CMOS flip-flop shown in FIG. 2, but in this case, the following problem occurs in this circuit. That is, for example, considering that transistor 1 is on and transistor ₂ is off, the output of these transistor pair T1 is H, but if transistor 1 is an enhancement type, this H level output will vary from Vcc to Vth of transistor 1. Therefore, even if this is applied to the gate of transistor 5 of transistor pair _T3 , its source voltage will be at H level when transistor 6 is off (this is also Vcc
-Vth), so the gate of transistor 5,
There is no potential difference between the sources, so transistor 5
cannot remain on (because it is an enhancement type). If the transistor 5 is not on, the gate voltage of the transistor 1 will not become H, so the transistor 1 cannot be maintained in the on state either. The same thing can be said about the transistor pair T ₂ and T ₄ , so it becomes impossible to constantly hold information. To avoid this, transistor 1,
3, 5, and 7 are of depletion type so that only a slight on-current flows. This eliminates the problem of Vth drop mentioned above. Also, if you do this, current will flow through the transistor pair where the enhancement type transistor is in the on state even in steady state, but the value is a leakage current (needless to say, the insulation resistance of the transistors and wiring is not infinite, so there is a leakage current) It is sufficient to compensate for this (if it cannot be compensated, of course there will be a drop in the H level), so a small value of 1 μA or less is sufficient for the large current at the time of transition (this is set to about 10 mA to increase speed). The current consumption during steady state can be much lower than that of the flip-flop shown in FIG. 1, and can approach that of the flip-flop shown in FIG.

In this flip-flop, the transistor pair
Two transistors 1 and 2 forming T ₁ to T ₄ ,
Since one of 3 and 4, 5 and 6, and 7 and 8 is always on and the other is off (incomplete off as described above for the depletion type), the static power consumed by this flip-flop is the depletion type. There is only a small current in the transmission transistor, which can be set to a very small amount as described above. Therefore, even if the dynamic current is increased and the speed is increased by reducing the resistance of the load transistor, the time-averaged power consumption will be negligible. That is, when using this circuit, a large current flows from the power supply only at the moment when the circuit transitions from on to off or from off to on. When using this flip-flop circuit, the lines 11 and 12, 13 and 14, which are in a complementary relationship,
Either one of the pairs 11 and 14 or 12 and 13 may be connected to the external input/output terminal, respectively.

FIG. 4 is an example of a plane pattern when the circuit diagram of FIG. 3 is made into an IC, where 15 shown with diagonal lines is the source and drain diffusion region of the transistors 1 to 8, and 16 is the diffusion region 15 and the aluminum power source. The contact holes 17 with the lines 9 and 10 are direct contact holes between the aforementioned lines 11 to 14 (which are also the gate electrodes of the transistors 1 to 8) made of polycrystalline silicon, for example, and the diffusion region 15; This is the series connection point of the pairs T ₁ to _{T 4} , that is, the output terminal.

FIG. 5 shows an application example in which the flip-flop shown in FIG. 3 is used as a main part of a static type memory cell, and the entire cell consists of 10 elements including transistors 19 and 20 for transfer gates. In the figure, 18 is a word line that controls transistors 19 and 20, and 21 and 22 are connected via transistors 19 and 20 to any combination of lines 11 to 14 in a flip-flop consisting of transistor pairs T ₁ to T ₄ . This is a bit line pair. Since this memory cell requires 10 transistors, it seems that the area is four elements larger than that of a normal six-transistor cell, but in reality, the area can be much smaller than that.

In other words, since each two transistors forming the transistor pair T ₁ to _{T 4} of the present invention work complementary to each other, if the substrate effect of the transistors is ignored, it is sufficient to arrange two transistors having essentially the same size. Therefore, it is sufficient to use transistors that can be manufactured with minimum dimensions in terms of process technology as each component. Therefore, the number of elements is doubled compared to the conventional flip-flop, but the occupied area is doubled.
It is less than twice that. For example, if we take the E/D type flip-flop shown in Figure 1 as an example, the minimum size that can be manufactured is
If it is 2 μm, the driver transistor 32,
34 has a gate length of 2 μm and a gate width of 15 μm, and load transistors 31 and 33 have a gate width of 2 μm.
Generally, transistors 1 to 1 are manufactured with dimensions of about 15 μm and gate length (unless they are manufactured in this way, stable operation cannot be expected).
Both the gate length and gate width of 8 are the minimum dimensions.
It can be set to 2 μm. Moreover, the ratio between the gate width and the gate length of the conventional load transistors 31 and 33 is 1/5 (2/15 in the above example, and the reciprocal β _R of this ratio is generally selected to be 3 to 20). ,
In the present invention, this can be reduced to 1/1, so it can be expected that the operating current will increase about five times and the switching speed will increase about five times. This has operating characteristics comparable to a CMOS flip-flop, but it is easy to manufacture because unlike CMOS, there is no need to form transistor pairs with opposite conductivity channels on the same substrate.

In the present invention, the point that one flip-flop is constructed with eight transistors will be further explained. When this flip-flop is used as a memory cell as shown in FIG.
1, 22 and transfer gates 19, 20, lines 11, 14 are set to H and L levels, and transistors 1 to 8 take on/off states as described above. Reading is performed by taking out H and L of these lines 11 and 14 through transfer gates 19 and 20 and bit lines 21 and 22.

When the flip-flop shown in FIG. 3 is operated independently, the operation is as follows. For some reason, when the power is turned on, transistor 7 is replaced by transistor 8.
If the current is more likely to flow, then wire 1
4 approaches the H side, transistors 3 and 2 become close to on, and the line 12 approaches the H side. This makes transistor 7 increasingly conductive. In other words, positive feedback is present, line 14 quickly goes high, transistors 3 and 2 turn on quickly, line 12 quickly goes high,
Transistor 7 turns on quickly. The same goes for the L side, and as line 14 goes high and transistor 2 turns on, line 11 approaches the L side more and more, turning off transistors 5 and 8 and helping line 14 rise to the H level. The same applies to other lines and transistors. When the power is turned on, if transistor 5 is in a state where current flows more easily than transistor 6, the above is reversed, and transistor 5 is rapidly turned on due to positive feedback in the path of line 13, transistor 1, and line 11, and line 13 becomes high. , line 14 becomes L, and so on.

The main focus of the present invention is that in FIG. 1, when the transistor 32 is on, a DC path 31-32 is created, and when the transistor 34 is on, a DC path 33-34 is created, and in either state, current flows and power consumption increases.
There is a way to prevent this. One way to reduce this current and hence power consumption is to turn off transistors 31 and 33 when transistors 32 and 34 are on, but this is not possible (if transistors 31 and 33 are enhancements, the output 37,
Unable to maintain H level of 38). In FIG. 3, by providing a buffer circuit and applying feedback, this is substantially made possible as described above. This buffer circuit consists of two pairs on the one hand, for example T ₁ and T ₂ , and two pairs on the other hand, T ₃ and T ₄ in this example. That is, the first
In the format shown in the figure, output 11 would be applied directly to each gate of transistors 1 and 4 in Figure 3, but
In the figure, this is added via transistor pair T ₃ ,
Similarly, in Figure 1, the output 12 is the transistor 3, 2
, but in FIG. 3 it is applied via transistor pair T ₄ . Therefore T ₃ ,
_T4 is the buffer of the feedback circuit of _T1 and _T2 .

The return in FIG. 3 can be expected to be faster than that in FIG. This is because, in Fig. 1, the output of one inverter stage is fed back only to the drive transistor (32 or 34), whereas in Fig. 3, for example, in transistor pair _T4 , the feedback of the output 14 is This is because it is conducted to transistor 7 via T ₂ and also to transistor 8 via pair T ₁ . In this way, in FIG. 3, it is possible to not only reduce power consumption but also increase speed due to positive feedback.

Further, FIG. 3 is more complicated than FIG. 1, and there is a concern about signal transmission delays due to increased wiring length, but since the transistors are smaller and this offsets, delays are not a particular problem as a whole.

As described above, according to the present invention, the drawbacks of the conventional circuits can be solved at once, and a bistable flip-flop circuit that is high speed, low in power consumption, and easy to manufacture can be realized.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing different examples of conventional flip-flops, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a circuit diagram showing the flip-flop circuit of FIG. FIG. 5 is a circuit diagram showing an application example in which the flip-flop circuit of the present invention is used as a main part of a static type memory cell. In the figure, 1, 3, 5, and 7 are depression type
MIS type transistors 2, 4, 6, and 8 are enhancement type MIS type transistors, and _T1 to _T4 are first to fourth transistor pairs.

Claims (1)

[Claims] 1 Single conductivity channel MIS transistor 2
The gate of the depletion type transistor connected to the positive side terminal of the power supply is the positive input terminal, the gate of the enhancement type transistor connected to the negative side terminal of the power supply is the negative input terminal, and these transistors are connected in series. Four transistor pairs whose output terminals are the connection points are connected in parallel between the positive and negative terminals of the power supply, and the negative input terminal of the first transistor pair, the positive input terminal of the second transistor pair, and the output terminal of the fourth transistor pair are connected in parallel between the positive and negative terminals of the power supply. output terminal, and the positive input terminal of the first transistor pair, the negative input terminal of the second transistor pair, and the third
and the output terminal of the first transistor pair and the positive input terminal of the third transistor pair and the negative input terminal of the fourth transistor pair, and the output terminal of the second transistor pair and the third transistor pair. A flip-flop circuit characterized in that a negative input terminal of a transistor pair and a positive input terminal of a fourth transistor pair are respectively connected.