JP2631335B2 - Logic circuit - Google Patents

Logic circuit

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Publication number
JP2631335B2
JP2631335B2 JP4337898A JP33789892A JP2631335B2 JP 2631335 B2 JP2631335 B2 JP 2631335B2 JP 4337898 A JP4337898 A JP 4337898A JP 33789892 A JP33789892 A JP 33789892A JP 2631335 B2 JP2631335 B2 JP 2631335B2
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Japan
Prior art keywords
power supply
logic circuit
supply line
threshold
low threshold
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP4337898A
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Japanese (ja)
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JPH0629834A (en
Inventor
順三 山田
康之 松谷
伸一郎 武藤
隆国 道関
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日本電信電話株式会社
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Priority to JP3-311007 priority Critical
Priority to JP31100791 priority
Priority to JP3-323382 priority
Priority to JP32338291 priority
Priority to JP3-324512 priority
Priority to JP32451291 priority
Priority to JP4-14537 priority
Priority to JP4017537A priority patent/JPH05218850A/en
Priority to JP4-17537 priority
Priority to JP4337898A priority patent/JP2631335B2/en
Application filed by 日本電信電話株式会社 filed Critical 日本電信電話株式会社
Publication of JPH0629834A publication Critical patent/JPH0629834A/en
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Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit used for a latch circuit which can operate at a low voltage such as a power supply voltage of 1 V or less.

[0002]

2. Description of the Related Art A conventional logic circuit of this type is generally constituted by a CMOS type logic block circuit, and FIG. 12 shows an example thereof. In this example, inverter INV1, NAND gate NAND1,.
Each logic element such as NV2 is connected to power supply lines VDD and VSS via switching transistors M1, M2... M3 and switching transistors M4, M5.

Under such a configuration, a high-level control signal CSB is applied to the switching transistors M1, M2,... M3, and the switching transistors M4, M5,.
Supply the low-level control signal CS to M6 to control the operation of each logic element.

[0004]

However, since the switching transistor used in such a configuration is configured as a transistor having a single threshold voltage, the following problems occur.

For example, when the power supply voltage of this logic circuit is reduced from 5 V to 1 V assuming dry battery operation, when the operation is performed (CS = H level, CSB = L level), each transistor is turned off. Since the threshold voltage and the power supply voltage are close to each other, there is a problem that the mutual conductance of each transistor becomes extremely small and the delay time of each logic circuit element becomes long.

When the threshold voltage of each transistor constituting the logic circuit is reduced, the leakage current increases during non-operation (CS = L level, CSB = H level), and the life of the battery becomes extremely short. . Further, since the control transistor is turned off, there is a problem that stored information is destroyed.

The present invention has been made in view of such a situation, and enables high-speed operation even when the power supply voltage is reduced, and reduces power consumption during non-operation.

[0008]

In order to solve such a problem, a first invention corresponds to FIG. 1 and has one of the power supply terminals (PL) of a low threshold logic circuit (20). A first pseudo power supply line (PL) to be connected and a high threshold first control transistor (TS1) arranged between the first pseudo power supply line and the first power supply line. 1 power supply circuit, a second pseudo power supply line (QL2) connected to the remaining power supply circuit (PL2) of the low threshold logic circuit, and a connection between the second pseudo power supply line and the second power supply line. And / or a second power supply circuit composed of a high threshold second control transistor (TS2).

A second invention corresponds to FIG. 4, and in the first invention, a circuit is provided between the first pseudo power supply line and the first power supply line.
A capacitor is connected between and / or between the second pseudo power supply line and the second power supply line.

[0010] A third invention corresponds to FIG.
Or the second invention, the low threshold logic circuit is constituted by a plurality of stages, each stage being between the first power supply line and the first pseudo power supply line, or between the second power supply line and the second pseudo power supply line.
And high-threshold field-effect transistors alternately between the power supply lines.

A fourth invention corresponds to FIGS. 1, 6, and 7, and includes another logic circuit (30) at a stage subsequent to the circuit of the first invention or the second invention.

A fifth invention corresponds to FIG. 10, and includes a plurality of logic circuit blocks formed on an integrated circuit substrate,
A control circuit block, wherein each of the logic circuit blocks is supplied with power from first and second pseudo power supply lines, and the control circuit block is supplied from the first and second power supply lines via a high-threshold field effect transistor. Power is supplied.

[0013]

Since the low threshold transistor is supplied with power via the high threshold transistor, no current flows when the high threshold transistor is off.

[0014]

FIG. 1 shows one embodiment of a logic circuit according to the present invention.
And a low threshold logic circuit 20 for generating an inverted clock signal CKB, and a high threshold logic circuit driven by these clocks.

In FIG. 1, a control circuit 10 includes a control signal C for turning on and off a control transistor described later.
S and CSB are transmitted, and the control signal CSB is a signal obtained by inverting the control signal CS.

The field effect type MOS control transistors are represented by symbols Ts1 and Ts2, and the p-channel type transistor TS1 is connected to a power supply line PL supplied with a power supply voltage VDD.
1 and the pseudo power supply line QL1 are turned on / off, and the n-channel transistor TS2 is connected to the grounded power supply line PL2.
And a function of turning on / off the connection with the pseudo power supply line QL2.

In this embodiment, the low threshold circuit 20 composed of a low threshold CMOS device is used to generate an inverted clock signal CKB from the clock signal CK.
The inverters INV1 and INV2 are configured. For example, the inverter INV1 has two low-threshold MOS transistors T21 and T, whose output electrodes are connected in cascade and whose input electrodes are connected in common.
The transistor T21 uses a p-channel type and the transistor T22 uses an n-channel type.

One output electrode of the transistor T21 is connected to the pseudo power supply line QL1, and one output electrode of the transistor T22 is connected to the pseudo power supply line QL2. Further, the inverter INV2 is also provided as an input to the inverter INV2.
1 except that the inverter INV1
This is the same configuration as that of FIG.

In the present invention, a low threshold circuit is
Are connected to the common pseudo power supply lines QL1 and QL2. And the pseudo power line Q
L1 is a power supply line PL via an output electrode of the transistor Ts1.
1 (for example, the potential of VDD) and the pseudo power supply line QL
2 is connected to a power supply line (for example, a ground potential) via an output electrode of the transistor TS2.

The configuration of this low threshold circuit is merely an example, and it can be assembled into various configurations using logic elements such as an AND gate, an OR gate, and a NAND gate in consideration of the application or other factors. Therefore,
This threshold circuit 20 is not limited to the circuit of this embodiment. Control signals CSB and CS are supplied to input electrodes of the transistors TS1 and TS2, respectively.

The high threshold logic circuit 30 composed of a high threshold CMOS device is composed of a latch circuit having two transfer gates LC1 and LC2 and three inverters INV3, INV4 and INV5. In this latch circuit, the supply of power is controlled via two high threshold MOS field effect transistors TS5 and TS6.

In this case, the transistor TS5 is of a p-channel type, and the transistor TS6 is of an n-channel type. The transfer gate LC1 is composed of two field-effect MOS transistors T31 and T32 having a low threshold voltage, the output electrodes of these transistors being commonly connected, and one being a terminal D to which data is input. And the other is connected to the input side of the inverter INV3.

The input electrode of the transistor T31 is
A clock CK is supplied, and an inverted clock (CK bar) CKB is supplied to an input electrode of the transistor T32. Transfer gate LC2 is also transfer gate L
The configuration is the same as that of C1. One of the output electrodes is connected to the output side of the transfer gate LC1, and the other output electrode is connected to the input side of the inverter INV3.

Inverters INV3, INV4, INV5
Has the same configuration as the inverter INV1, and each transistor constituting the inverter INV3 is constituted by a low-threshold MOS transistor.
The transistors of the inverters INV4 and INV5 are constituted by high-threshold transistors. Each transistor constituting the transfer gate LC2 may be either a low threshold or a high threshold type transistor.

Next, one of the output electrodes of the inverter INV3 is connected to the power supply line PL1 via a high-threshold transistor TS5, and the other output of the inverter INV3 is connected via a high-threshold transistor TS6. It is connected to power supply line PL2. The control signal CSB is supplied to the input electrode of the transistor TS5, and the control signal CSB is supplied to the input electrode of the transistor TS6.
Is supplied.

The inverter INV4 is connected to the inverter IN
V3 is connected in parallel with the inverter INV3. The difference between the inverter INV3 and the inverter INV3 is that the output electrodes of the transistors connected in series are directly connected to the power supply lines PL1 and P1 without passing through transistors such as the transistors TS5 and TS6.
L2. And each inverter INV3
And the output side of INV4 are commonly connected, and are configured to be sent to the subsequent stage as the output of this latch circuit.

In this latch circuit, another inverter INV5 is connected between the output side of these inverters INV3 and INV4 and one of the output electrodes of the transfer gate LC2. This inverter I
NV5 is constituted by two high-threshold transistors, and is directly connected to power supply lines PL1 and PL2 similarly to the above-described inverter INV4.

In such a configuration, the state when the control signals CS and CSB are transmitted from the control circuit 10 will be specifically described. The low-level selection control signal CSB and the selection control signal CS are supplied to predetermined electrodes. Then, the high-threshold control transistors TS1 and TS2 are turned on, and the pseudo power supply lines QL1 and Q2 are turned on.
A potential appears at L2.

As a result, each logic element constituting the low threshold circuit 20 is in a state where the power supply voltage is applied, and performs a logic operation according to the clock CK and the clock CKB. At this time, since each of the logic elements of the low threshold circuit 20 has a small threshold, high-speed operation is possible even if the power supply voltage is reduced.

Next, when the control signals CS and CSB are not selected, that is, when these signals are not supplied to the transistors TS1 and TS2 and these transistors are off, the pseudo power supply line Q
No power supply voltage appears at L1 and QL2, and no power supply voltage is applied to the low threshold circuit 20.

In other words, the low threshold circuit 20 is inactive. At this time, since the control transistors TS1 and TS2 have a high threshold, even if the low threshold circuit 20 connected downstream of the control transistors TS1 and TS2 is a low threshold logic element, the power consumption during non-operation does not increase. Thereby, the operation delay time of this logic circuit can be suppressed.

Next, the low threshold circuit 20
The operation of the latch circuit driven by the latch will be described. First, the data supplied to the input terminal D is captured at the timing of the clock signals CK and CKB supplied to the transfer gate LC1, and the data is supplied to the inverters INV3 and INV4.
Sent to The inverter INV3 takes in the output of the transfer gate LC1 supplied when the power supply voltage is supplied by the control signals CSB and CS sent from the control circuit 10.

The outputs of the inverters INV3 and INV4 are sent to the subsequent stage as the output of the latch circuit, and are also sent to the inverter INV5. The output of the inverter INV5 is sent to the transfer gate LC2. The transfer gate LC2 outputs this output to the inverter IN at the timing of the clock signals CK and CKB.
An operation of sending the signal to the input side of V3 and latching the received signal is performed.

Here, when the high-level control signal CS and the low-level control signal CSB are transmitted, the transistors TS6 and TS5 become conductive, and the inverter INV
3, this part operates as a master part of a high-speed D flip-flop by the operation of the transistors constituting INV4 and INV5 and the transistors of the transfer gates LC1 and LC2 described above.

Next, when the control signals CS and CSB are not selected, the transistors TS6 and TS5 are in a non-conductive state, and the CMOS inverter INV3 constituted by the low threshold transistors is in a non-conductive state. . However, since the inverters INV4 and INV5 constituted by high-threshold transistors connected in parallel with the inverter INV3 and the transfer gate LC2 hold data, the data in the latch circuit is not destroyed.

Further, since this latch circuit is connected to power supply lines PL1 and PL2 via high-threshold transistors TS6 and TS5, power consumption during non-operation does not increase.

FIG. 2 is a characteristic diagram showing the effects of the present invention and the conventional logic circuit. In the figure, the horizontal axis represents the power supply voltage VDD, and the vertical axis represents the delay time tpd. The characteristic a shows the relationship between the delay time and the power supply voltage when using the logic circuit as shown in FIG. 1, and the characteristic b shows the relationship between the delay time and the power supply voltage when using the logic circuit according to the present invention. I have. It can be seen that when the power supply voltage is 1 V, the use of the logic circuit of the present invention can reduce the delay time by 50% compared to the conventional logic circuit without increasing power consumption during non-operation.

As described above, the use of the logic circuit of the present invention makes it possible to use a transistor having a small threshold voltage, thereby increasing the speed even when the power supply voltage is reduced. Can be brought into a non-conducting state, so that there is an effect that power consumption can be reduced.

FIG. 3 further shows the frequency characteristics of the logic circuit of the present invention, in particular, the latch circuit at the subsequent stage. The vertical axis indicates the maximum toggle which is the maximum frequency of the clock signal (CK) for operating the latch circuit normally. The horizontal axis indicates the power supply voltage VDD. In this figure, a characteristic P shows a case where the circuit of the present invention is used, and a characteristic Q shows a case where a conventional circuit is used.

In FIG. 3, when the power supply voltage is 1 V, the maximum toggle frequency of the circuit of the present invention is 500 MHz, while that of the conventional circuit is 100 MHz. It can be seen that the maximum toggle frequency of the D flip-flop circuit can be increased five times without increasing the power consumption during operation.

FIG. 4 shows another embodiment of the present invention. Since most of the configuration is the same as that of FIG. 1, only the portions necessary for the description of this embodiment are shown. That is, in this embodiment, the capacitors C1 and C2 are connected between the pseudo power supply line QL1 and the power supply line PL1, and between the pseudo power supply line QL2 and the power supply line PL2, whereby the pseudo power supply line and the power supply of the low threshold logic circuit 20 are connected. Power supply fluctuations at the connection portions N2 and N1 with the line are suppressed.

By increasing the capacitance, the delay time of the operation by this circuit is reduced, and the operation can be performed at a higher speed than in the embodiment of FIG. In this case, the capacitor C1
And C2 are, for example, transistors TS1
And between the drain of the transistor TS2 and the substrate. In this case, the capacity can be increased by increasing the thickness of the pseudo power supply line, so that a special capacity increasing process is not required.

FIG. 5 shows another embodiment of the present invention, particularly showing a modification of the latch circuit. In this figure, the function of each part is the same as that of FIG. 1 and the layout is modified, so that the same reference numerals as in FIG. 1 are used. That is, in FIG. 5, a series body of the inverter INV3 and the control transistors TS5 and TS6 is connected to the transfer gate LC
1 is arranged in the preceding stage.

With this configuration, the operation of taking in the signal can be divided, but the same operation as in FIG. 1 can be performed. Also in FIG. 1, the transfer gate LC1
Of the transistor TS5 and the inverter INV of FIG.
3. In some cases, a series body of transistors TS6 is provided,
For such a configuration, the configuration of FIG. 5 can reduce the delay time by one inverter.

FIG. 6 shows another embodiment of the present invention, and particularly shows a modification of the latch circuit of FIG. In this example, the series body of the control transistor TS5 and the transistor TS6 is omitted. Even with such a configuration, the high threshold logic circuit 30 can operate as a latch circuit in the same manner as in FIGS.

FIGS. 7 and 8 show another embodiment of the present invention, particularly showing a case where the present invention is applied to a memory device. In this example, of the logic circuit group in which the CMOS selection logic circuits composed of MOSFETs having a small threshold voltage are cascaded, the logic circuit at the subsequent stage is connected to one of the pseudo power supply lines (QL1 in this example), and The logic circuit and the subsequent stage are connected to a different pseudo power supply line (QL2 in this example) so as to suppress the floating of the output potential.

FIG. 7 shows NAND gates NAND1 to NAN.
A select logic circuit constituted by Dn and inverters INV21 to INV2n is shown, and NAND gates NAND1 to NANDn receiving two inputs connect one end of a power supply terminal to power supply line PL1, and NAND gates NAND1 to NANDN
The other end of the power supply terminal of ANDn is connected to a pseudo power supply line QL2, and this pseudo power supply line QL2 is connected to a control transistor TS2A.
To the power line PL2.

The NAND gate used here is constituted by a low threshold CMOS transistor, and as shown in the figure, a p-channel MOS transistor T61 and a transistor T62 connected in parallel, and a series connection on the source side of these transistors. N-channel MOS transistor T63 and transistor T
The gate electrodes of the transistor T62 and the transistor T63 are commonly connected to one of the input terminals I1.
The 64 gate electrodes are connected to another input terminal I2.

The inverters INV21 to INV21
2n has the same configuration as the inverter shown in FIG. 1, and is composed of two series-connected low threshold transistors T65 and T66, and one of the output electrodes of the transistor T65 is connected to the pseudo power supply line Q.
L1 and the pseudo power supply line QL1 is connected to a power supply line PL1 (in this example, V1 via a common control transistor TS1A).
DD). One of the output electrodes of the transistor T66 is directly connected to the power supply line PL2 (ground in this example) without passing through the pseudo power supply line.

Then, the NAND gates NAND1 to NAN
Dn are supplied with two inputs, respectively, and the output of each NAND gate is connected to the corresponding inverter INV21-INV at the subsequent stage.
It is connected to the input side of V2n. The outputs of these inverters INV21 to INV2n are connected to corresponding cells of the subsequent high threshold memory cell array 70 as word lines WL1 to WLn.

The memory cell array 70 is composed of cells arranged in an n × m matrix, and each cell is connected between power supply lines PL1 and PL2 as shown in FIG.
There is a series of n-channel and p-channel high threshold CMOS transistors T71 and T72 and a series of transistors T73 and T74 arranged in series.

The transistors T71 and T
72, a connection point between the transistors T73 and T74, and an n-channel high-threshold transistor T disposed between the bit line pair BL and BL bar.
75 and a transistor T76, and a transistor T71
And the connection point of the transistor T72 and the transistor T73.
And a gate electrode of the transistor T74 and one of the output electrodes of the transistor T75 are connected in common, and a connection point between the transistors T73 and T74;
The gate electrodes of the transistors T71 and T72 and one of the output electrodes of the transistor T76 are commonly connected.

Another output electrode of the transistor T76 is connected to the bit line BL and the multiplexer MUX, and another output electrode of the transistor T75 is also connected to the bit line BLB (BL bar) and the multiplexer MUX. Word line WL is connected to transistors T76 and T7.
5 gate electrodes.

When a high-level signal is applied to the word line WL, the potential at the connection point between the transistor T71 and the transistor T72 and the potential at the connection point between the transistor T73 and the transistor T74 are taken out as signals, and this input is input by the multiplexer MUX. Is reduced to 1 (ell), and the reduced 1 (ell) multiplexer outputs D0 to Dl are sent to the readout circuit 80 at the subsequent stage.

The read circuit 80 also has a two-stage configuration similarly to the above-described selection logic circuit 60, and has one of the power supply terminals of the inverters INV31 to INV31 to which the multiplexer outputs D0 to Dl of the memory cell array 70 are supplied. First, after being connected to the pseudo power supply line QL1, it is connected to the power supply line PL1 (VDD in this example) via the control transistor TS1B, and the inverters INV31 to INV31 are connected.
Is connected to another power supply terminal PL2 (ground in this example).

The inverters INV31-INV31
Inverters INV41-INV receiving the output of (L)
One of the power supply terminals 4l is connected to the pseudo power supply line QL2, and then to the power supply line PL2 (ground in this example) via the control transistor TS2B, and the inverter INV
Another power supply terminal PL1 of 41 to INV41 (L)
(In this example, VDD).

The selection logic circuit 60 having such a configuration
The operation when the operation is not selected will be described. In this case, NAND gates NAND1 to NANDn at the preceding stage of the selection logic circuit 60
Since the control signal applied to the control transistor TS2A for controlling the potential of the transistor TS is low, the transistor TS2A is off. Then, the input terminals I1 and I2 of the NAND gate are at a low potential because they are not selected, and the transistors T61 and T62 are turned on.
L2 is at a high potential of VDD.

At this time, in a subsequent inverter circuit, for example, inverter INV21, control transistor T
Since the control signal CSB applied to S1A is at a high potential,
The control transistor TS1A is turned off. At this time, since the transistor T66 is in the ON state, the output of the inverter becomes low potential. As a result, as in the above-described example, high-speed operation when the operation of the logic circuit is selected and low power consumption during the non-operation can be achieved.

In this embodiment, the control transistor on the NAND gate side is arranged on the low potential side and the control transistor on the inverter side is arranged on the high potential side. Of course, the control transistor on the side may be arranged on the low potential side. In addition, it is easy for those skilled in the art to configure the selected logic circuit using logic circuit elements other than the logic circuit elements used here.

The number of stages of the logic circuit is not limited to two, and it can be easily analogized that a configuration in which the number of stages is further increased can be adopted. When the number of stages is increased, the logic circuit of the preceding stage is different from the succeeding stage (inverse polarity).
High threshold M only between the power supply and the logic circuit
The polarity (high potential or low potential) of the power supply into which the high threshold MOS transistor is inserted may be determined so that the OSFETs are connected in series.

The read circuit 80 also has a two-stage configuration similar to the above-described selective read circuit. The stage before the output of the multiplexer MUX is supplied is an inverter INV3 composed of low threshold transistors.
The power supply is controlled by the presence or absence of the control signal CSB supplied to the high threshold control transistor TS1B from 1 to INV31 (ell).

These inverters INV31 to INV3
Inverter INV41 arranged on the output side of l
~ INV41 (L) via the pseudo power supply line QL2 is supplied with a high-threshold control transistor TS2.
B is controlled by the presence / absence of a control signal CSB supplied to the logic circuit B. With such a configuration, as in the above-described example, high-speed operation when the operation of the logic circuit is selected and low power consumption during the non-operation are reduced. Can be planned

FIG. 9 shows still another embodiment of the present invention.
In particular, the case where the present invention is applied to a memory device is shown.
In this example, the logic block 100 includes a plurality of cascaded CMOS inverters INV50, and the power supply of these inverters INV50 is a pseudo power supply line QL1.
And QL2 at nodes N1 and N2.

These pseudo power supply lines are connected to control transistors T
Power supply line PL via S1 and transistor TS2
1 and PL2. Since the function of each unit described above is the same as that of the above-described embodiment, it is indicated by the same symbol. FIG. 10 shows an example in which a logic circuit having such a basic configuration is used for a memory device.

FIG. 10 shows a layout of a standard cell memory device. This memory device includes standard cells SL1 to SL (n + 1), and one logical block 100 corresponds to each standard cell. Accordingly, the standard cells 1 to n are a logic circuit group including the logic circuit blocks 1001 to 100n, and the standard cell (n + 1) corresponds to the control transistor block 110 (corresponding to the transistors TS1 and TS2 in FIG. 1). .

In this example, the control transistor block 1
Reference numeral 10 is arranged adjacent to the right side of the logic circuit group. Also, in FIG.
The threshold layers are not included in the diffusion layers 120 and 121 in the channel MOS transistor and the p-channel MOS transistor.

In this embodiment, the threshold control mask is used for the high threshold, but it is needless to say that the threshold control mask may be used for the low threshold. Each standard cell is connected to power supply lines x1 and x2 (corresponding to PL1 and PL2 in the previous embodiments) and pseudo power supply lines y1 and y2 (corresponding to QL1 and QL2 in the previous embodiments) fixed to the substrate, respectively. The wiring in the standard cell is a polysilicon wiring used for the gate of the transistor.

The logic circuit group includes pseudo power supply lines y1 and y2
Then, power is supplied from the pseudo power supply line having a large wiring width via the power supply lines x1 and x2. Further, the substrate potential of the transistors constituting each logical release is determined by the power supply lines PL1 and P1.
It is applied from L2. Standard cell (n + 1)
Control block comprises a threshold control mask 125
For each of the control transistors TS1 and TS2.

These control transistors TS1 and TS2
Applies a voltage to the pseudo power supply lines y1 and y2 via the power supply lines x1 and x2, similarly to the logic circuit group.

In such a configuration, when control signals CS and CSB are selected, control transistors TS1 and TS2 are turned on, and pseudo power supply lines y1 and y1 are turned on.
2 is supplied with a power supply voltage. At this time, the threshold voltage of the transistors constituting the inverter block INV50 of the logic circuit group is lower than that of the control transistor, and the source capacitance of each transistor is added to the pseudo power supply lines y1 and y2, so that the parasitic capacitance is large. The voltage drop in this portion is small, and the inverter, that is, the logic circuit group can be operated at high speed.

When the control signals CS and CSB are not selected, the control transistor is turned off,
No power supply voltage is supplied to the pseudo power supply lines y1 and y2, and the inverter 1NV50 constituting the logic circuit group is in a non-operation state. At this time, the control transistors TS1 and Ts1
Since the threshold voltage of S2 is set higher than the internal transistors constituting the inverter circuit, the current flowing when the control transistors TS1 and TS2 are in a non-conductive state is very small, and the power consumption during non-operation increases. There is no.

In the layout of the standard cell of this embodiment, only the control transistor needs to be arranged at the end of the logic circuit group. Therefore, as the circuit scale becomes larger, the occupied area is reduced as compared with the conventional standard cell system. it can.

Although the control transistor block is arranged at the right end of the logic circuit block group in this embodiment, it may be arranged at another place, for example, at the left end, upper part or lower part.

FIG. 11 is a characteristic diagram showing the effect of the embodiment of FIG. 10, and the vertical axis shows the occupied area of the logic circuit block.
The horizontal axis indicates the number of standard cells. In the figure, a characteristic e is an occupied area by the conventional circuit configuration, and a characteristic f is an occupied area by the circuit configuration of the present invention.
Here, the standard area is standardized by the occupied area when the conventional standard cell is realized by ten cells. As shown in this characteristic, it can be seen that the occupied area can be reduced to about 1/2 as compared with the conventional type.

[0075]

As described above, according to the present invention, power is supplied to the logic circuit using the low threshold transistor through the high threshold transistor, so that the threshold can be identified by the high threshold transistor. Therefore, it is not necessary to lower the threshold value of the low threshold transistor, and the delay time of the logic circuit can be reduced. When the high threshold transistor is turned off, no current flows through the low threshold transistor, so that the leakage current is reduced. Therefore, there is an effect that it is possible to operate at a low voltage of about 1 V.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an embodiment of a logic circuit according to the present invention.

FIG. 2 is a characteristic diagram showing power supply voltage-delay time characteristics of the embodiment of the present invention shown in FIG. 1 and a conventional device.

FIG. 3 is a characteristic diagram showing a power supply voltage-maximum toggle frequency characteristic of the embodiment of the present invention of FIG. 1 and a conventional one.

FIG. 4 is a system diagram showing a modification of the present invention.

FIG. 5 is a system diagram showing a modified example of the present invention.

FIG. 6 is a system diagram showing still another embodiment of the present invention.

FIG. 7 is a system diagram showing still another embodiment of the present invention.

FIG. 8 is a circuit diagram showing a specific example of the memory cell of FIG. 7;

FIG. 9 is a system diagram showing still another embodiment of the present invention.

FIG. 10 is a diagram showing an embodiment in which the configuration shown in FIG. 10 is applied to an actual memory cell structure.

FIG. 11 is a characteristic diagram showing characteristics of the embodiment of FIG. 11 and the number of standard cells versus the occupied area of a block of a logic circuit;

FIG. 12 is a system diagram showing an example of a conventional logic circuit.

[Explanation of symbols]

 Reference Signs List 10 control circuit 20 low threshold logic circuit 30 high threshold logic circuit 100 logic circuit group 110 control circuit block PL1, PL2 power supply line QL1, QL2 pseudo power supply line CK, CKB clock signal CS, CSB control signal LC1, LC2 analog switch MUX multiplexer SL Standard cell

Continuation of the front page (72) Inventor Shinichiro Muto 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-62-208715 (JP, A) JP-A-55-166329 JP-A-53-23555 (JP, A) JP-A-58-70333 (JP, A) JP-A-63-42219 (JP, A) JP-A-55-53925 (JP, A) 2-82716, Kaihei (JP, A) JP50-24817 (JP, B1)

Claims (5)

(57) [Claims]
1. A low-threshold logic circuit including a logic circuit element including a plurality of low-threshold field-effect transistors, and first and second power lines serving as a power supply source for the low-threshold logic circuit. A power supply circuit for supplying power to the low threshold logic circuit, wherein the power supply circuit is connected to one of the power terminals of the low threshold logic circuit. And a first power supply circuit comprising a high threshold first control transistor disposed between the first pseudo power line and the first power line; and a remainder of the low threshold logic circuit. Pseudo power supply line connected to the power supply circuit of the first embodiment, and a high threshold second control connected between the second pseudo power supply line and the second power supply line. Logic circuit, characterized in that they are composed of both or one of the second power supply circuit constituted by a transistor.
2. The method according to claim 1, wherein a capacitor is connected between the first pseudo power supply line and the first power supply line and / or between the second pseudo power supply line and the second power supply line. Logic circuit to be characterized.
3. The low threshold logic circuit according to claim 1, wherein the low threshold logic circuit includes a plurality of stages, and the first stage includes a logic circuit element including a plurality of low threshold field effect transistors. A first low threshold logic circuit, first and second power supply line pairs for supplying power to the first low threshold logic circuit,
A first pseudo power supply line connected to one of the power supply terminals of the low threshold logic circuit of FIG.
Of a high threshold placed between the power line
A second power line is connected to the remaining power terminal of the first low threshold circuit, and a second stage following the first stage has a plurality of low threshold field effect A second low threshold logic circuit including a logic circuit element composed of a transistor, a second pseudo power supply line connected to one of power supply terminals of the second low threshold logic circuit, and a second pseudo power supply A first control transistor with a high threshold disposed between the first power supply line and a second power supply line, and the remaining power supply terminal of the second low threshold circuit is connected to the first power supply line. A logic circuit characterized by:
4. A low-threshold logic circuit including a logic circuit element including a plurality of low-threshold field-effect transistors, and first and second power supply lines for supplying power to the low-threshold logic circuit. A first pseudo power supply line connected to one of the power supply terminals of the low threshold logic circuit; and a high threshold power supply disposed between the first pseudo power supply line and the first power supply line. A second pseudo power supply line connected to the first control transistor and the remaining power supply terminal of the low threshold logic circuit; and a high pseudo power supply line disposed between the second pseudo power supply line and the second power supply line. A threshold second control transistor, and another logic circuit whose operation is controlled by the output of the low threshold logic circuit, wherein the power supply terminal of the other logic circuit is , A logic circuit connected to the second power supply.
5. A semiconductor device comprising: a plurality of logic circuit blocks formed on an integrated circuit substrate; and a control circuit block, wherein each of the logic circuit blocks includes a logic circuit element including a plurality of low threshold field effect transistors. A low threshold logic circuit, a first and second power supply line pair for supplying power to the low threshold logic circuit, and a first pseudo power supply connected to one of the power supply terminals of the low threshold logic circuit A second pseudo power supply line connected to a remaining power supply terminal of the low threshold logic circuit, wherein the control circuit block is disposed between the first pseudo power supply line and the first power supply line. High-threshold first field-effect control transistor, a second high-threshold control transistor disposed between the second pseudo power supply line and the second power supply line. It includes a field effect control transistor, logic circuit, characterized in that it is arranged at the end of the logic circuit blocks.
JP4337898A 1991-11-26 1992-11-26 Logic circuit Expired - Lifetime JP2631335B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP3-311007 1991-11-26
JP31100791 1991-11-26
JP3-323382 1991-12-06
JP32338291 1991-12-06
JP3-324512 1991-12-09
JP32451291 1991-12-09
JP4-14537 1992-01-30
JP4-17537 1992-02-03
JP4017537A JPH05218850A (en) 1992-02-03 1992-02-03 Logic circuit
JP4337898A JP2631335B2 (en) 1991-11-26 1992-11-26 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4337898A JP2631335B2 (en) 1991-11-26 1992-11-26 Logic circuit

Publications (2)

Publication Number Publication Date
JPH0629834A JPH0629834A (en) 1994-02-04
JP2631335B2 true JP2631335B2 (en) 1997-07-16

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Application Number Title Priority Date Filing Date
JP4337898A Expired - Lifetime JP2631335B2 (en) 1991-11-26 1992-11-26 Logic circuit

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Country Link
JP (1) JP2631335B2 (en)

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