JP2005268695A - Semiconductor integrated circuit and its designing device, design method, and design program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of increasing a design efficiency with a function for shutting off power supply to a circuit cell, and to provide its design device, method, and program. <P>SOLUTION: A power switching cell 20 for shutting off the power supply from power line groups PL1 to branch line groups BL2 is arranged at a branch point between a plurality of power line groups PL1 arranged in a vertically striped form at intervals of not more than predetermined maximum interval Xmax, and a plurality of branch line groups BL2 branching from the power line groups PL1 and arranged in the vertically striped form in the range from the branch source power line groups PL1 to the adjacent branch line groups BL2. A circuit cell 10 receiving the power supply from the branch line groups BL2 is arranged along the branch line groups BL2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit having a function of cutting off power supply to unused circuit cells, a design apparatus, a design method, and a design program.

  In order to cope with low power consumption and miniaturization of processing dimensions, the power supply voltage of a semiconductor integrated circuit is decreasing year by year. When the signal amplitude is reduced due to a decrease in the power supply voltage, the threshold voltage of the transistor is relatively increased with respect to the signal amplitude, so that the on-current of the transistor is reduced and the delay is increased. Therefore, it is necessary to reduce the threshold voltage of the transistor according to the power supply voltage.

  However, if the threshold voltage of the transistor decreases, the leakage current in the off state increases. Therefore, the power consumption during standby operation, which has not been regarded as a problem in the past, is very large compared to the active operation, and the low power consumption of the circuit It becomes a big factor that obstructs.

  As a technique for preventing such an increase in leakage current, a circuit technique called MTCMOS (multi-threshold complementary metal oxide semiconductor) has attracted attention. In MTCMOS, a high threshold voltage transistor is generally inserted into the power supply line for each circuit block that performs a specific function. When the circuit block becomes unused, the transistor switch is turned off, and the leakage current flowing through the transistors in the circuit block is cut off. As a result, useless leakage current flowing in unused circuit blocks can be greatly reduced.

FIG. 10 is a diagram illustrating an example of a circuit to which MTCMOS is applied.
The circuit cells 1 and 2 are connected between the power supply line VDD and the ground line VSS, and are always supplied with power. On the other hand, the circuit cells 3 and 4 are connected between the power supply line VDD and the virtual ground line VSSA, and the power is supplied to the virtual cell line VSSA and the ground line VSS. Only when connected by a threshold voltage transistor 5.

  The high threshold voltage transistor 5 is controlled to be turned on and off in accordance with a control signal Sc from a circuit block (not shown). When the circuit cells 3 and 4 are not used, the control signal Sc is set to a low level, and the high threshold voltage transistor 5 is turned off. Thereby, the virtual ground line VSSA and the ground line VSS are disconnected, and the leakage current of the circuit cells 3 and 4 is cut off.

  By the way, in the design of a semiconductor integrated circuit incorporating such MTCMOS technology (hereinafter referred to as an MTCMOS type semiconductor integrated circuit), in general, the layout of the circuit cells in each circuit block having a specific function is determined. The design is automatically performed by a CAD device, and then a transistor switch is manually arranged on the power supply line outside the circuit block.

The main reason why the layout design must be done manually is that there is no fixed relationship between the layout of the transistor switch and its effect on circuit operation.
That is, in the conventional MTCMOS type semiconductor integrated circuit, since transistor switches are arranged later on the outside of the circuit block whose layout has already been determined, how the transistor switch layout affects the operation of the circuit block Different for each design object. Therefore, it is difficult to find a unified design method for determining an appropriate transistor switch layout in consideration of the influence on the operation of the circuit block, and it is difficult to realize an automatic layout design.

For example, if the power supply voltage drop occurs due to the on-resistance of the transistor switch or the resistance of the power supply wiring, the signal amplitude becomes relatively small with respect to the threshold voltage of the transistor, which increases the signal delay and causes a timing violation. It becomes easy.
In the conventional MTCMOS type semiconductor integrated circuit, the power supply wiring pattern inside the circuit block varies depending on the design object, so how the signal delay of each circuit cell is affected by the insertion position of the transistor switch. Different for each design object.

  For this reason, it is difficult to determine an appropriate insertion position of the transistor switch by a unified method. Usually, detailed simulation of the power supply voltage drop and timing of each circuit cell is repeated, and the requested timing is not violated. Whether the transistor switch is inserted is determined by the designer's judgment.

  As described above, the conventional MTSMOS type semiconductor integrated circuit does not have a fixed relationship between the layout of the transistor switch and the influence on the circuit operation, and therefore cannot be designed by a unified method. There is a disadvantage that it is difficult to improve efficiency.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor integrated circuit capable of improving design efficiency while having a function of cutting off power supply to a circuit cell, and a design apparatus thereof. It is to provide a design method and a design program.

  According to a first aspect of the present invention, there is provided a semiconductor integrated circuit having a plurality of circuit cells and a plurality of power switch cells, each of which interrupts power supply to at least one of the circuit cells. And a plurality of branches arranged in a horizontal stripe in a range from the branching power supply line group to the adjacent power supply line group. Line group. The power switch cell is disposed at a branch point between the power line group and the branch line group, and interrupts power supply from the power line group to the branch line group. The circuit cell is arranged along the branch line group and receives power supply from the branch line group.

According to the first aspect of the present invention, the plurality of power supply line groups arranged in the form of vertical stripes at intervals equal to or smaller than the predetermined maximum interval, the power supply line group, and the adjacent power supply line from the branch source power line group The power switch cell for cutting off the power supply from the power line group to the branch line group is arranged at a branch point with a plurality of branch line groups arranged in a horizontal stripe pattern in the range up to the group. The circuit cells that receive power supply from the branch line group are arranged along the branch line group.
For this reason, the upper limit of the length of the branch line group connecting the power switch cell and the circuit cell to be shut off is defined by the maximum interval.

  Preferably, the maximum interval is set such that a signal delay of the circuit cell when the interval between the vertical stripes is equal to or less than the maximum interval and the circuit cells are densely arranged between adjacent power line groups is within a predetermined range. Set to get interval.

Further, the power switch cell may have a driving capability corresponding to the number of circuit cells that cut off power supply.
For example, the power switch cell may include a transistor parallel circuit in which a number of switching transistors corresponding to the number of circuit cells that cut off power supply are connected in parallel.

  According to a second aspect of the present invention, there is provided a semiconductor integrated circuit design apparatus for designing a semiconductor integrated circuit having a plurality of circuit cells and a plurality of power switch cells, each of which interrupts power supply to at least one of the circuit cells. A plurality of power supply line groups are arranged in vertical stripes at intervals equal to or less than a predetermined maximum interval, and a plurality of branch line groups branching from the power supply line group are connected to power supply lines adjacent to the branching power supply line group. In the range up to the group, arranged in a horizontal stripe, the power switch cell that cuts off the power supply from the power line group to the branch line group, arranged at the branch point of the power line group and the branch line group, And a layout unit that arranges the circuit cells that receive power supply from the branch line group along the branch line group.

  According to a third aspect of the present invention, there is provided a semiconductor integrated circuit design method for designing a semiconductor integrated circuit having a plurality of circuit cells and a plurality of power switch cells, each of which interrupts power supply to at least one of the circuit cells. A plurality of power supply line groups are arranged in vertical stripes at intervals equal to or less than a predetermined maximum interval, and a plurality of branch line groups branching from the power supply line group are connected to power supply lines adjacent to the branching power supply line group. In the range up to the group, arranged in a horizontal stripe, the power switch cell that cuts off the power supply from the power line group to the branch line group, arranged at the branch point of the power line group and the branch line group, A layout step of arranging the circuit cells that receive power supply from the branch line group along the branch line group;

  According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit for causing a computer to execute a design of a semiconductor integrated circuit having a plurality of circuit cells and a plurality of power switch cells each blocking power supply to at least one of the circuit cells. A circuit design program, wherein a plurality of power supply line groups are arranged in a vertical stripe shape at intervals equal to or less than a predetermined maximum interval, and a plurality of branch line groups branched from the power supply line group are The power switch cell, which is arranged in a horizontal stripe pattern in the range to the adjacent power line group and cuts off power supply from the power line group to the branch line group, is a branch point between the power line group and the branch line group. And a layout processing step of arranging the circuit cells that receive power supply from the branch line group along the branch line group.

  According to the second to fourth aspects of the invention, the plurality of power supply line groups are arranged in vertical stripes at intervals equal to or less than a predetermined maximum interval, and the plurality of branch line groups branched from the power supply line group are Are arranged in a horizontal stripe pattern in the range from the power supply line group to the adjacent power supply line group. The power switch cell that cuts off power supply from the power line group to the branch line group is disposed at a branch point between the power line group and the branch line group, and receives power from the branch line group. The circuit cell is arranged along the branch line group.

  According to the present invention, since the layout of the power switch cell can be determined so that the signal delay of the circuit cell is within a predetermined range in a fixed arrangement structure, design automation can be easily realized.

  Hereinafter, three embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram showing an example of the configuration of a semiconductor integrated circuit according to the first embodiment of the present invention. In the figure, wiring related to the power source and circuit cells connected to the wiring are schematically illustrated.

  1 includes a plurality of power supply line groups PL1, a plurality of power supply line groups PL2, a plurality of branch line groups BL1 and BL2, a plurality of circuit cells 10, a plurality of power switch cells 20, The circuit block 30 and a plurality of power input cells 41 and 42 are provided.

The power supply line group PL1 is an embodiment of the power supply line group of the present invention.
The branch line group BL2 is an embodiment of the branch line group of the present invention.
The circuit cell 10 is an embodiment of the circuit cell of the present invention.
The power switch cell 20 is an embodiment of the power switch cell of the present invention.

The power supply line group PL1 is arranged in a vertical stripe pattern, and the power supply line group PL2 is arranged in a horizontal stripe pattern. In the example of FIG.
The vertically striped power line group PL1 and the laterally striped power line group PL2 intersect with each other to form a checkered power line pattern.

  The power supply line groups PL1 and PL2 have power supply lines VDD and VSS, respectively, and the power supply lines VDD and the power supply lines VSS are connected to each other at the intersections of the above-described grid stripe power supply line patterns.

In this grid-like power line pattern, power input cells 41 and 42 are connected to the power line groups PL1 and PL2 in the four outer frames, respectively. The power supply line VSS is connected to the power supply input cell 41, and the power supply line VDD is connected to the power supply input cell 42.
A power supply voltage is supplied to the power supply lines VSS and VDD from the outside of the semiconductor integrated circuit via the power input cells 41 and 42.

  The branch line groups BL1 and BL2 are wiring groups that branch from the power supply line group PL1, and are arranged in horizontal stripes in a range from the branch power supply line group to the adjacent power supply line group. In the example of FIG. 1, they are arranged extending in a direction orthogonal to the power supply line group PL1.

  A circuit cell 10 which is a basic unit of a circuit in a semiconductor integrated circuit is arranged along the branch line group BL1 or BL2, and receives power supply from these branch line groups.

A plurality of such branch line groups are branched from one power supply line group PL1, and a plurality of circuit cells 10 are connected to each branch line group.
The circuit cell 10 included in the semiconductor integrated circuit is basically supplied with power from such a branch line group. However, a circuit that does not need to shut off the power supply line due to continuous operation or the like includes a circuit that receives power supply directly from the power supply line group without passing through the branch line group, such as the circuit block 30 shown in FIG. It is.

The branch line group BL1 has two branch lines (VDDA and VSSA). The branch line VDDA is connected to the power supply line VDD, and the branch line VSSA is connected to the power supply line VSS.
On the other hand, the branch line group BL2 also has two branch lines (VDDB and VSSB). The branch line VDDB is connected to the power supply line VDD, and the branch line VSSB is connected to the power supply line VSS.
The difference between the branch line groups BL1 and BL2 is whether or not the power switch cell 20 is inserted. That is, among these, the power switch cell 20 is inserted on the branch line group BL2. In the example of FIG. 1, a power switch cell 20 is disposed at a branch point between the power line group and the branch line group.

The power switch cell 20 cuts off the supply of power to the circuit cells 10 connected to the branch line group BL2 by cutting off the power supply from the power line group PL1 to the branch line group BL2.
For example, the power switch cell 20 includes a switching transistor, and cuts at least one branch line of the branch line group BL2 in accordance with an input control signal.

  In the case of an MTCMOS type semiconductor integrated circuit, a high threshold voltage MOS transistor is used as the switching transistor. For example, assuming that the power supply line VDD has a positive potential with respect to the power supply line VSS, an n-type MOS transistor having a high threshold voltage is used as a switching transistor when the branch line VSSB connected to the power supply line VSS is cut. When the branch line VDDB connected to the power line VDD is cut, a p-type MOS transistor having a high threshold voltage is used.

FIG. 2 is a diagram for explaining the maximum interval Xmax of the power supply line group PL1 arranged in a vertical stripe shape. 1 and 2 indicate the same components.
As shown in the figure, in the semiconductor integrated circuit according to the present embodiment, the interval between the power supply line groups PL1 arranged in a vertical stripe is set to be equal to or less than a predetermined maximum interval Xmax.

  The maximum interval Xmax is, for example, the signal delay of the circuit cell 10 when the circuit cells 10 are densely arranged between the adjacent power supply line groups PL1 with the vertical stripe interval of the power supply line group PL1 as the maximum interval Xmax. The interval is set so as to be within a predetermined range. That is, the maximum interval Xmax of the vertical stripes of the power supply line group PL1 is set so that the signal delay of the circuit cell 10 falls within a previously assumed range.

The reason why the signal delay range of the circuit cell 10 can be estimated according to the maximum interval Xmax is that when the maximum interval Xmax is determined, the upper limit length of the branch line group BL2 is determined accordingly.
That is, when the upper limit length of the branch line BL2 is determined, the resistance of the branch line group BL2 is determined accordingly, and the maximum number of circuit cells 10 connected to the branch line group BL2 is determined. When the maximum number of circuit cells 10 is determined, the upper limit of the total power supply current of the circuit cells 10 connected to one power switch cell 20 is determined accordingly.
When the resistance of the branch line group BL2 and the upper limit of the total power supply current of the circuit cell 10 are determined, the maximum value of the power supply voltage drop generated between the power switch cell 20 and the circuit cell 10 is determined accordingly. Depending on this maximum value, it is possible to estimate an approximate worst value of the signal delay of the circuit cell 10.
Further, the worst value of the signal delay of the circuit cell 10 can be estimated more accurately by adding the difference between the power supply voltage drops at the peripheral portion and the central portion of the checkered power supply pattern to the above-described maximum value. .

2 to 4 show examples in which the interval between the vertical stripes of the power line group PL1 is set to be equal to or less than the maximum interval Xmax.
For example, the overall width X1 of the circuit block that performs power shutdown is Xmax <X1 <2Xmax.
In this case, as shown in FIG. 3, two rows of power switch cells 20 are arranged at the maximum interval Xmax, and the remaining one column is arranged at an interval X2 narrower than the maximum interval Xmax.
Further, for example, the overall width X1 of the circuit block that performs power shutdown is 2Xmax <X1 <3Xmax.
In this case, as shown in FIG. 4, three rows of power switch cells 20 are arranged at the maximum interval Xmax, and the remaining one column is arranged at an interval X2 narrower than the maximum interval Xmax.

  In an actual arrangement, the circuit cells 10 do not necessarily have to be arranged without a gap, and may be arranged with a certain gap. However, even if the circuit cells 10 are arranged without gaps, if the interval between the columns of the power switch cells 20, that is, the interval between the adjacent power supply line groups PL <b> 2 is equal to or less than the predetermined maximum interval Xmax, The signal delay is within the range assumed in advance.

  2 and 3, the intervals of the columns of the power switch cells 20 are not uniform. However, for example, as illustrated in FIG. 5, it is possible to set all the columns to the equal interval X3 under the condition of the maximum interval Xmax or less. It is.

As described above, according to the semiconductor integrated circuit according to the present embodiment, the plurality of power supply line groups PL1 arranged in the form of vertical stripes at intervals equal to or less than the predetermined maximum interval Xmax and the power supply line group PL1 are branched. The power supply from the power supply line group PL1 to the branch line group BL2 is cut off at a branch point with a plurality of branch line groups BL2 arranged in a horizontal stripe pattern in the range from the original power supply line group PL1 to the adjacent power supply line group PL1. A power switch cell 20 is disposed. The circuit cells 10 that receive power supply from the branch line group BL2 are arranged along the branch line group 10.
Therefore, the upper limit of the length of the branch line group BL2 that connects the power switch cell 20 and the circuit cell 10 that is the power cutoff target is defined by the maximum interval Xmax. When the upper limit of the branch line group BL2 is defined, the upper limit of the power supply wiring resistance from the power switch cell 20 to the circuit cell 10 and the maximum number of circuit cells 10 that can be connected to one branch line group BL2 are determined. The maximum voltage drop from the power switch cell 20 to the circuit cell 10 is determined. From this maximum value, an approximate worst value of the signal delay of the circuit cell 10 can be estimated.
That is, the arrangement of the power switch cell 20 and the circuit cell 10 can be determined so that the signal delay of the circuit cell 10 falls within a previously assumed range under a certain arrangement structure.
In this way, the design procedure is clarified, so that design automation can be easily realized.

  Further, according to the semiconductor integrated circuit according to the present embodiment, since the arrangement structure is regular as shown in FIGS. 1 and 2, the processing procedure when the design is automated can be simplified.

Furthermore, according to the semiconductor integrated circuit according to the present embodiment, the power switch cells 20 are widely distributed and the power supply can be finely cut off for each relatively small number of circuit cells.
As a result, the power supply current flowing through the power switch cell 20 is reduced and the power supply voltage drop is reduced as compared with the conventional arrangement structure in which the power switch is provided outside the circuit block. Can alleviate the effect of the signal delay on the signal delay and can cope with further lowering of the power supply voltage.

  As shown in FIGS. 1 and 2, the power switch cell 20 is arranged so that at least a part of the power switch cell 20 is included in the lower layer region of the power line group PL1, thereby effectively making the lower layer region of the power line group PL1. Since it can be utilized, a wasteful increase in circuit area can be prevented and the arrangement density of the circuit cells 10 can be improved.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.

  The power switch cell desirably has as large a driving capability as possible in order to reduce the drop in the power supply voltage. However, if the power switch cell is made too large, disadvantages such as an increase in circuit area and leakage current are caused.

  Therefore, in the semiconductor integrated circuit according to the second embodiment, the driving capability of the power switch cell is set according to the number of circuit cells to be powered off. That is, as the number of circuit cells to be shut off is larger and the power source current is larger, the drive capability of the power switch cell 20 is set larger to suppress the power source voltage drop. Conversely, the smaller the number of circuit cells to be powered off and the smaller the power supply current, the lower the drive capability and the reduction of leakage current when the power switch is off.

  FIG. 6 is a diagram showing an example of the configuration of the power switch cells 20A and 20B in the semiconductor integrated circuit according to the second embodiment of the present invention. 1 and 6 indicate the same components. The overall configuration of the semiconductor integrated circuit according to this embodiment is the same as that shown in FIG.

In the example of FIG. 6, two types of power switch cells 20A and 20B having different driving capabilities are shown.
The power switch cell 20A conducts / cuts off the power line VSS and the branch line BSSB by a parallel circuit of three switch transistors.
The power switch cell 20B conducts / cuts off the power supply line VSS and the branch line BSSB by one switch transistor.
If the switching transistors of both transistors are all the same size, the power switch cell 20A has a driving capability three times that of the power switch cell 20B.

  In this way, by using power switch cells with different drive capacities according to the number of circuit cells to be shut off, the signal due to the drop in power supply voltage is compared to when the drive capacities of the switching transistors are set uniformly. The circuit area and leakage current can be reduced while suppressing the delay.

  In addition, as shown in FIG. 6, a plurality of switching transistors are formed in advance in the power switch cell, and the drive capability of the power switch cell can be selected according to the presence or absence of these parallel connection wirings. Therefore, even if a design change occurs after the manufacturing mask is created and the driving capability needs to be corrected, it is only necessary to correct the wiring pattern mask, and the cost can be reduced.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.

  The third embodiment relates to a semiconductor integrated circuit design apparatus according to the above-described embodiments.

FIG. 7 is a diagram showing an example of a hardware configuration of a semiconductor integrated circuit design apparatus according to the third embodiment of the present invention.
The integrated circuit design apparatus shown in FIG. 7 includes a computer 110, a program storage unit 120, a data storage unit 130, a display device 140, and an interface unit 150.

  The computer 110 reads out an integrated circuit design program stored in the program storage unit 120 and executes it, and executes processes described later related to the design of the integrated circuit.

  The program storage unit 120 stores an integrated circuit design program to be executed by the computer 110.

  The data storage unit 130 stores data used in the process of execution in the computer 110 and data of execution results. For example, circuit data to be processed by an integrated circuit design program such as a gate level netlist or a cell library is stored.

  The display unit 140 displays an image according to the control of the computer 110. For example, as the integrated circuit design program is executed, an image that prompts the user to input an instruction, an image of a simulation execution result, and the like are displayed.

  The interface unit 150 includes a device for inputting information from the user to the computer 110 such as a keyboard and a mouse. Also included are devices for inputting and outputting circuit data to be processed in the integrated circuit design device, such as an optical disk device and a network interface device.

FIG. 8 is a diagram illustrating an example of a functional configuration of a semiconductor integrated circuit design apparatus according to the third embodiment, illustrating a functional configuration realized by a semiconductor integrated circuit design program.
The semiconductor integrated circuit design apparatus shown in FIG. 8 includes a layout unit 210 and a switch drive capability determination unit 220.
The layout unit 210 is an embodiment of the layout means of the present invention.
The switch drive capability determining unit 220 is an embodiment of the switch drive capability determining means of the present invention.

  The layout unit 210 inputs data D1 (for example, a net list) of a circuit that performs layout, and in accordance with this description, the layout of the power supply wiring (power supply line groups PL1 and PL2, branch line groups BL1 and BL2) and the cell (power supply) The layout of the switch cell 20 and the circuit cell 10) is determined.

That is, layout unit 210 arranges power supply line groups PL1 and PL2 and branch line groups BL1 and BL2 as follows.
A plurality of power supply line groups PL1 are arranged in a vertical stripe pattern at intervals equal to or less than a predetermined maximum interval Xmax, and a plurality of power supply line groups PL2 are arranged in a horizontal stripe pattern in a direction orthogonal to the power supply line group PL1. A plurality of branch line groups BL1 and BL2 branched from the power supply line group PL1 are arranged in a horizontal stripe shape in a range from the branch power supply line group PL1 to the adjacent power supply line group PL1.

In addition, the layout unit 210 executes a placement and routing process for the power switch cell 20 and the circuit cell 10 (a process for determining a placement position of the cell and a routing path for the signal) so that the following condition is satisfied.
A power switch cell 20 that cuts off power supply from the power line group PL1 to the branch line group BL2 is arranged at a branch point between the power line group PL1 and the branch line group BL2. A circuit cell 10 that interrupts power supply by the power switch cell 20 (that is, a circuit cell 10 that receives power supply from the branch line group BL2) is disposed along the branch line group BL2. Circuit cells 10 that do not cut off power supply (that is, circuit cells 10 that receive power supply from the branch line group BL1) are arranged along the branch line group BL1.

  The layout unit 210 has a predetermined signal delay of the circuit cell 10 when the circuit cells 10 are densely arranged between two adjacent power supply line groups PL1 with the vertical stripe interval of the power supply line group PL1 set to the maximum interval Xmax. The maximum interval Xmax is set so as to fall within the range.

The switch drive capability determination unit 220 determines the drive capability of each power switch cell 20 according to the number of circuit cells 10 whose power supply is cut off by the power switch cell 20. That is, as the number of circuit cells 10 increases, the driving capability of the power switch cell 20 is set larger.
For example, as shown in FIG. 6, there are a plurality of types of power switch cells 20 with different drive capacities, and the switch drive capability determination unit 220 sets the type of each power switch cell 20 to the number of circuit cells 10 that shut off the power. Decide accordingly.

  Next, the operation of the semiconductor integrated circuit design apparatus having the above-described configuration will be described with reference to the flowchart of FIG.

Step ST10:
In accordance with the description of the given circuit data D1, the layout unit 210 performs power supply wiring layout and cell placement and routing as described below, for example.

First, layout unit 210 determines the arrangement region of power supply line groups PL1 and PL2 and branch line groups. At this time, the interval between the power line groups PL1 is set to be equal to or smaller than the maximum interval Xmax described above.
Note that the distinction between the branch line group BL1 and the branch line group BL2 is determined at the initial stage because it is determined when the arrangement of the power switch cells 20 is determined.

  Next, the layout unit 210 arranges the circuit cell 10 at a position along the branch line group so as to avoid the lower layer region of the power supply line group PL1, which is the arrangement region of the power switch cell 20, and sets the signal wiring path thereof. decide. At this time, the layout unit 210 is a circuit in which a plurality of circuit cells 10 commonly connected to one branch line are circuit cells that are all powered off by the common power switch cell 20, or are not all powered off. Place and route processing is performed so as to form a cell.

  When the circuit cell 10 connected to the branch line is determined, whether or not the power switch cell 20 is arranged at the starting point of the branch line group and the power line group PL1 (that is, the branch line group BL1 and the branch line group BL2) And the control signal for turning on / off the power switch cell 20 arranged at the branch point is determined. The layout unit 210 also determines the wiring path for the control signal of the power switch cell 20 in the same manner as the circuit cell 10.

Step ST20:
When the arrangement and wiring of the power switch cell 20 and the circuit cell 10 are determined, the switch drive capability determining unit 220 examines the number of circuit cells 10 connected to each power switch cell 20 via the branch line BL2, and this circuit cell. The drive capability of the power switch cell 20 is determined according to the number.

  As described above, according to the semiconductor integrated circuit design apparatus according to the present embodiment, the power supply wiring and cell layout design of the semiconductor integrated circuit according to the first and second embodiments and the drive capability of the power cell switch 20 are achieved. This determination can be performed by a computer. This makes it possible to automate the work that has conventionally been performed manually, thereby improving design efficiency.

  In addition, this invention is not limited only to embodiment mentioned above, A various variation is included.

  The semiconductor integrated circuit of the present invention and the semiconductor integrated circuit to be designed by the design apparatus of the present invention are not limited to the MTCMOS type semiconductor integrated circuit, but also to other various types of semiconductor integrated circuits. The present invention is applicable.

  In the embodiment described above, the processing of the semiconductor integrated circuit design apparatus is realized by a computer and a program. However, the present invention is not limited to this, and at least a part thereof can be realized by hardware.

1 is a diagram illustrating an example of a configuration of a semiconductor integrated circuit according to a first embodiment. It is a figure for demonstrating the largest space | interval of the power supply line group arrange | positioned at vertical stripe form. It is a 1st figure which shows an example of the layout of a power switch cell. It is a 2nd figure which shows an example of the layout of a power switch cell. It is a 3rd figure which shows an example of the layout of a power switch cell. 6 is a diagram illustrating a configuration example of two types of power switch cells having different driving capabilities in a semiconductor integrated circuit according to a second embodiment. FIG. It is a figure which shows an example of the hardware constitutions of the semiconductor integrated circuit design apparatus which concerns on 3rd Embodiment. It is a figure which shows an example of a functional structure of the semiconductor integrated circuit design apparatus which concerns on 3rd Embodiment. It is a figure which shows an example of the design flow in the semiconductor integrated circuit design apparatus shown to FIG. 7 and FIG. It is a figure which shows an example of the circuit to which MTCMOS is applied.

Explanation of symbols

  PL1, PL2 ... power line group, BL1, BL2 ... branch line group, 10 ... circuit cell, 20, 20A, 20B ... power switch cell, 30 ... circuit block, 41, 42 ... power input cell, 110 ... computer, 120 ... Program storage unit, 130 ... Data storage unit, 140 ... Display device, 150 ... Interface unit, 210 ... Layout unit, 220 ... Switch drive capability determination unit

Claims (11)

A semiconductor integrated circuit having a plurality of circuit cells and a plurality of power switch cells each blocking power supply to at least one circuit cell,
A plurality of power line groups arranged in vertical stripes at intervals equal to or less than a predetermined maximum interval;
A plurality of branch line groups that are branched from the power line group and arranged in a horizontal stripe shape in a range from the branch source power line group to the adjacent power line group;
Have
The power switch cell is disposed at a branch point between the power line group and the branch line group, and cuts off power supply from the power line group to the branch line group,
The circuit cell is disposed along the branch line group and receives power supply from the branch line group.
Semiconductor integrated circuit. The maximum interval is set to an interval that allows a signal delay of the circuit cells when the circuit cells are densely arranged between adjacent power supply line groups with the vertical stripe interval to be the maximum interval to be within a predetermined range. The
The semiconductor integrated circuit according to claim 1. The power switch cell has a driving capability according to the number of circuit cells that cut off power supply.
The semiconductor integrated circuit according to claim 1. The power switch cell has a transistor parallel circuit in which a number of switching transistors according to the number of circuit cells that cut off power supply are connected in parallel.
The semiconductor integrated circuit according to claim 3. A semiconductor integrated circuit design apparatus for designing a semiconductor integrated circuit having a plurality of circuit cells and a plurality of power switch cells each cutting off power supply to at least one circuit cell,
A plurality of power supply line groups are arranged in vertical stripes at intervals equal to or less than a predetermined maximum interval, and a plurality of branch line groups branching from the power supply line group are connected from the branch source power line group to the adjacent power supply line group. The power switch cell that is arranged in a horizontal stripe shape in the range and cuts off the power supply from the power line group to the branch line group is disposed at a branch point between the power line group and the branch line group, and the branch line A layout means for arranging the circuit cells that receive power supply from the group along the branch line group;
Semiconductor integrated circuit design equipment. The layout means sets the maximum stripe so that the signal delay of the circuit cells is within a predetermined range when the circuit cells are densely arranged between adjacent power supply line groups with the vertical stripe interval being equal to or less than the maximum interval. Set the interval,
The semiconductor integrated circuit design apparatus according to claim 5. A switch drive capability determining means for determining the drive capability of each power switch cell according to the number of circuit cells whose power supply is cut off by the power switch cell;
The semiconductor integrated circuit design apparatus according to claim 5. A semiconductor integrated circuit design method for designing a semiconductor integrated circuit having a plurality of circuit cells and a plurality of power switch cells each cutting off power supply to at least one of the circuit cells,
A plurality of power supply line groups are arranged in vertical stripes at intervals equal to or less than a predetermined maximum interval, and a plurality of branch line groups branching from the power supply line group are connected from the branch source power line group to the adjacent power supply line group. The power switch cell that is arranged in a horizontal stripe shape in the range and cuts off the power supply from the power line group to the branch line group is disposed at a branch point between the power line group and the branch line group, and the branch line A layout step of arranging the circuit cells that receive power supply from the group along the branch line group;
Semiconductor integrated circuit design method. A switch driving capability determining step of determining the driving capability of each power switch cell according to the number of circuit cells whose power supply is cut off by the power switch cell;
The semiconductor integrated circuit design method according to claim 8. A semiconductor integrated circuit design program for causing a computer to design a semiconductor integrated circuit having a plurality of circuit cells and a plurality of power switch cells that each cut off power supply to at least one of the circuit cells,
A plurality of power supply line groups are arranged in vertical stripes at intervals equal to or less than a predetermined maximum interval, and a plurality of branch line groups branching from the power supply line group are connected from the branch source power line group to the adjacent power supply line group. The power switch cell that is arranged in a horizontal stripe shape in the range and cuts off the power supply from the power line group to the branch line group is disposed at a branch point between the power line group and the branch line group, and the branch line A layout processing step of arranging the circuit cells that receive power supply from the group along the branch line group;
Semiconductor integrated circuit design program. A switch drive capability determination processing step for determining the drive capability of each power switch cell according to the number of circuit cells whose power supply is cut off by the power switch cell;
The semiconductor integrated circuit design program according to claim 10.

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