KR950002237A

KR950002237A - Input buffer of semiconductor integrated circuit with bias circuit

Info

Publication number: KR950002237A
Application number: KR1019930010144A
Authority: KR
Inventors: 김명재; 이규찬
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1993-06-05
Filing date: 1993-06-05
Publication date: 1995-01-04
Also published as: KR960003221B1

Abstract

본 발명은 반도체집적회로에서 특히 티티엘레벨의 외부신호를 입력하여 이를 씨모오스레벨의 내부신호로 정형하여 출력하는 입력버퍼에 관한 것으로, 본 발명에 의한 입력버퍼는, 풀엎경로상에 형성되는 피모오스 트랜지스터 및/또는 풀다운경로상에 형성되는 엔모오스트랜지스터의 각 스위칭동작을 제어하는 바이어스회로를 구비하는 입력버퍼를 개시하고 있다. 이로부터 본 발명에 의한 바이어스회로를 구비하는 입력버퍼를 통해, 입력신호 IN이 논리 “로우”로 인식될 수 있는 레벨중 최대값인 레벨 VILmax와 입력신호 IN이 논리 “하이”로 인식될 수 있는 레벨중 최소값인 레벨 즉 VIHmin을 용이하게 조정할 수 있게 된다. 따라서 입력버퍼의 트립점중 VIHmin과 VILmax의 변경을 위한 별도의 마스크를 구비할 필요가 없게 된다. 또한 이러한 특성을 통해 특히 다수개의 동작전압을 채용하는 고집적 반도체집적회로에서 동작전압의 변화에 따른 적절한 정형특성을 가지는 입력버퍼를 제공할 수 있게 된다. 또한 전원전압 변동에 따른 잡음에 대한 이득도 커지는 부가직인 효과를 얻을 수 있다.The present invention relates to an input buffer for inputting an external signal of a TTI level, in particular, in a semiconductor integrated circuit and shaping the signal as an internal signal of a CMOS level. The input buffer according to the present invention is formed on a pull path. An input buffer having a bias circuit for controlling each switching operation of a transistor and / or an enmo transistor formed on a pull-down path is disclosed. From this, through the input buffer including the bias circuit according to the present invention, the level VILmax, which is the maximum value among the levels at which the input signal IN can be recognized as a logic "low", and the input signal IN can be recognized as a logic "high". It is possible to easily adjust the level, VIHmin, which is the minimum value among the levels. Therefore, it is not necessary to have a separate mask for changing VIHmin and VILmax among the trip points of the input buffer. In addition, this characteristic makes it possible to provide an input buffer having an appropriate shaping characteristic according to a change in operating voltage, particularly in a highly integrated semiconductor integrated circuit employing a plurality of operating voltages. In addition, the gain of noise due to fluctuations in power supply voltage can be increased.

Description

Input buffer of semiconductor integrated circuit with bias circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 입력버퍼의 제1실시예를 보여주는 회로도, 제3도는 본 발명에 의한 입력버퍼에 구비되는 바이어스회로의 실시예를 보여주는 회로도, 제4도는 본 발명에 의한 입력버퍼의 제2실시예를 보여주는 회로도.2 is a circuit diagram showing a first embodiment of an input buffer according to the present invention, FIG. 3 is a circuit diagram showing an embodiment of a bias circuit provided in the input buffer according to the present invention, and FIG. 4 is a drawing of the input buffer according to the present invention. Circuit diagram showing an embodiment.

Claims

A semiconductor integrated circuit comprising: at least one pull transistor formed on a first current path for supplying a voltage of a first power supply to a predetermined output node in response to a first level input of an external signal, and a second of the external signal At least one pull-down transistor formed on a second current path for supplying a voltage of a second power source to the output node according to a level pressure, and a predetermined bias to a gate of a specific single pull-transistor transistor among the at least one pull-up transistor And a bias circuit for supplying a voltage to control the switching operation of the specific pull transistor.

The input buffer of claim 1, wherein the first power is a power supply voltage supplied from an outside of the same chip, and the second power is a ground voltage.

The input buffer of claim 2, wherein the bias circuit determines a trip level for an external signal of the single pull transistor.

4. The bias circuit of claim 3, wherein the bias circuit comprises a plurality of unit bias circuits having output terminals commonly connected to gates of the single pull transistor, and the selection operation of the plurality of unit bias circuits is provided in each unit bias circuit. An input buffer of a semiconductor integrated circuit, as determined by the cutting operation of the fuse.

A semiconductor integrated circuit comprising: at least one pull transistor formed on a first current path for supplying a voltage of a first power supply to a predetermined output node in response to a first level input of an external signal, and a second of the external signal At least one pull-down transistor formed on a second current path for supplying a voltage of a second power source to the output node according to a level input, and a predetermined bias to a gate of a specific single pull-down transistor of the at least one pull-down transistor; And a bias circuit for controlling a switching operation of the specific pull-down transistor by supplying a voltage to the input buffer of the semiconductor integrated circuit.

6. The input buffer of claim 5, wherein the first power is a power supply voltage supplied from an outside of the same chip, and the second power is a ground voltage.

7. The input buffer of claim 6, wherein the bias circuit determines a trip level for an external signal of the single pull-down transistor.

8. The method of claim 7, wherein the bias circuit comprises a plurality of unit bias circuits having output terminals commonly connected to gates of the single pull-down transistor, and the selection operation of the plurality of unit bias circuits is provided in each unit bias circuit. An input buffer of a semiconductor integrated circuit, as determined by the cutting operation of the fuse.

1. A semiconductor integrated circuit comprising: at least one pull junction transistor formed on a first current path for supplying a voltage of a first power supply to a predetermined output node according to a first level input of an external signal, and the at least one pull transistor A first bias circuit that controls a switching operation of the specific pull transistor by supplying a predetermined bias voltage to a gate of the specific single pull transistor, and a predetermined bias to the gate of the specific single pull down transistor of the at least one pull down transistor. And a second bias circuit for supplying a voltage to control the switching operation of the specific pull-down transistor.

10. The input circuit according to claim 9, wherein the first power is a power supply voltage supplied from the outside of the same chip, and the second power is a ground voltage.

The input buffer of claim 10, wherein the first bias circuit determines a trip level for an external signal of the single pull transistor.

12. The method of claim 11, wherein the first bias circuit comprises a plurality of unit first bias circuits having output terminals commonly connected to gates of the single pull transistor, and the selection operation of the plurality of unit first bias circuits is performed. An input buffer of a semiconductor integrated circuit, characterized in that determined by the cutting operation of the fuse provided in the unit first bias circuit.

11. The input buffer of claim 10, wherein the second bias circuit determines a trip level for an external signal of the single pull-down transistor.

The method of claim 13, wherein the second bias circuit comprises a plurality of unit second bias circuits having output terminals commonly connected to gates of the single pull-down transistor, and the selection operation of the plurality of unit second bias circuits is performed. The input buffer of the semiconductor integrated circuit, characterized in that determined by the cutting operation of the fuse provided in the unit second bias circuit.

※ Note: The disclosure is based on the initial application.