KR930008658B1 - Voltage level detecting circuit - Google Patents

Voltage level detecting circuit Download PDF

Info

Publication number
KR930008658B1
KR930008658B1 KR1019910000386A KR910000386A KR930008658B1 KR 930008658 B1 KR930008658 B1 KR 930008658B1 KR 1019910000386 A KR1019910000386 A KR 1019910000386A KR 910000386 A KR910000386 A KR 910000386A KR 930008658 B1 KR930008658 B1 KR 930008658B1
Authority
KR
South Korea
Prior art keywords
voltage
level
input signal
pmos transistor
logic
Prior art date
Application number
KR1019910000386A
Other languages
Korean (ko)
Other versions
KR920015728A (en
Inventor
배종욱
Original Assignee
금성일렉트론 주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사, 문정환 filed Critical 금성일렉트론 주식회사
Priority to KR1019910000386A priority Critical patent/KR930008658B1/en
Priority to JP4003080A priority patent/JPH0587841A/en
Priority to DE4200623A priority patent/DE4200623C2/en
Publication of KR920015728A publication Critical patent/KR920015728A/en
Application granted granted Critical
Publication of KR930008658B1 publication Critical patent/KR930008658B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
    • G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Power Sources (AREA)

Abstract

The circuit detects the voltage level of the input signal and outputs the logic signal. The circuit is suitable for the semiconductor circuit design by reducing the large amount of the power consumption. The circuit is composed of the reference level generating section (1) which generates the reference level (V1) according to the reference voltage (Vp), the comparing output section (2) which compares the input voltages (V1,Vs) and generates the logic output (V2), and the PMOS transistors (MP11,MP12) which provide the operating source (Vcc) to the generating sect. (1) and to the comparing output sect. (2).

Description

전압레벨 검출회로Voltage level detection circuit

제 1 도는 종래 전압레벨검출회로도.1 is a conventional voltage level detection circuit diagram.

제 2a 및 b 도는 제 1 도에 종래 전압레벨검출회로에 따른 각부 동작 전류파형 및 전압파형도.2A and 2B show the operating current waveforms and voltage waveforms of respective parts according to the conventional voltage level detection circuit in FIG.

제 3 도는 본 발명의 전압레벨검출회로도.3 is a voltage level detection circuit diagram of the present invention.

제 4a 및 b 도는 제 3 도 본 발명 전압레벨검출회로에 따른 각부 동작전류파형 및 전압파형도.4A and 4B are diagrams of operating current waveforms and voltage waveforms of respective parts of the voltage level detection circuit of the present invention.

제 5 도는 제 3 도 본 발명에 따른 회로와 제 1 도 종래회로의 일실시예에서 최대소모전류량을 보인 비교표.5 is a comparison table showing the maximum current consumption in one embodiment of the circuit according to the present invention and FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기준레벨발생뷰 2 : 비교출력부1: reference level occurrence view 2: comparison output unit

MN1, MN2: N형모스트랜지스터MN 1 , MN 2 : N-type MOS transistor

MP1, MP2, MP11, MP12: P형모스트렌지스터MP 1 , MP 2 , MP 11 , MP 12 : P-type transistor

VP : 기준전압 VS: 입력신호전압VP : Reference voltage VS: Input signal voltage

V1: 기준레벨 V2: 전압레벨검출논리출력V 1 : Reference level V 2 : Voltage level detection logic output

N1: 기준레벨발생노드 N2: 논리출력모드N 1 : reference level generating node N 2 : logic output mode

본 발명은 입력신호의 전압레벨을 검출하여 논리신호로 출력하는 회로에 관한 것으로, 특히 불필요한 전력소모를 크게 줄임으로써 반도체회로설계에 적당하도록 한 전압레벨검출회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting a voltage level of an input signal and outputting it as a logic signal. More particularly, the present invention relates to a voltage level detection circuit suitable for semiconductor circuit design by greatly reducing unnecessary power consumption.

종래의 전압레벨(LEVEL)검출회로는 제 1 도에 도시된 바와같이 N형모스(이하, NMOS라 칭함)트랜지스터(MN1) 및 P형모스(이하, PMOS라 칭함) 트랜지스터(MP1)로 구성되어 기준전압(VP)에 따라 기준레벨전압(V1)을 발생하는 기준레벨발생부(1)와, NMOS트랜지스터(MN2) 및 PMOS트랜지스터(MP2)로 구성되어 상기 기준레벨전압(V1)과 입력신호전압(VS)을 하는 비교출력부(2)로 구성되는데, 상기 기준레벨발생부(1)는 기준전압(VP)을 게이트에 인가받는 NMOS트랜지스터(MN1)의 소오스가 음전원(이하, VSS라 칭함)단자에 접속되고 그의 드레인은 기준레벨발생노드(N1)에 접속되며, 소오스에 양전원(이하 VCC라 칭함)을 인가받는 PMOS트랜지스터(MP1)의 게이트 및 드레인이 상기 기준레벨발생노드(N1)에 공통접속되어 구성되고,상기 비교출력부(2)는 상기 기분레벨발생부(1)의 기준레벨발생노드(N1)에 게이트가 접속되는 PMOS트랜지스터(MP2)의 소오스에 VCC를 인가받고 그의 드레인이 논리출력노드(N2)에 접속되며, 입력신호전압(VS)을 게이트에 인가받고 그의 소오스가 VSS단자에 접속된 NMOS트랜지스터(MN2)의 드레인이 상기 논리출력노드(N2)에 접속되고, 논리출력노드(N2)의 전압을 전압레벨검출출력(V2)으로 출력하도록 구성되었다.The conventional voltage level (LEVEL) detection circuit is composed of an N-type MOS (hereinafter referred to as NMOS) transistor MN 1 and a P-type MOS (hereinafter referred to as PMOS) transistor MP 1 as shown in FIG. And a reference level generator 1 for generating a reference level voltage V 1 according to the reference voltage V P , and an NMOS transistor MN 2 and a PMOS transistor MP 2 . V 1 ) and a comparison output unit 2 configured to perform an input signal voltage V S , wherein the reference level generator 1 is configured of the NMOS transistor MN 1 to which the reference voltage V P is applied to the gate. A PMOS transistor (MP 1 ) whose source is connected to a negative power supply (hereinafter referred to as V SS ) terminal and its drain is connected to a reference level generating node (N 1 ) and to which a positive power supply (hereinafter referred to as V CC ) is applied to the source. Are connected to the reference level generating node N 1 in common, and the comparison output unit 2 includes the mood level generating unit ( V CC is applied to the source of the PMOS transistor MP 2 whose gate is connected to the reference level generating node N 1 of 1 ), and its drain is connected to the logic output node N 2 , and the input signal voltage V S is applied. Is applied to the gate and the drain of the NMOS transistor (MN 2 ) whose source is connected to the V SS terminal is connected to the logic output node (N 2 ), and the voltage of the logic output node (N 2 ) is voltage level detection output. Configured to output (V 2 ).

여기서, VCC는 회로상의 동작전원전압중 높은전원이고, VSS는 낮은 전원으로 동작전원전압의 기준점이며, 기준전압(VP)은 출력논리값을 변화시키는 기준값이 되는 전압이고 입력신호전압(VS)은 회로에 입력되는 신호전압이며, 전압레벨출력(V2)은 입력신호전압(VS)값이 기준전압(VP)값 근처에 있을때 논리 "1"(하이레벨) 또는 논리 "0"(로우레벨)로 천이(트랜지션)하게 된다.Here, V CC is a high power supply of the operating power supply voltage on the circuit, V SS is a low power supply reference point of the operating power supply voltage, the reference voltage (V P ) is a voltage that is a reference value for changing the output logic value and the input signal voltage ( V S ) is the signal voltage input to the circuit, and the voltage level output (V 2 ) is the logic "1" (high level) or logic "when the value of the input signal voltage (V S ) is near the reference voltage (V P ) value. Transition is made to 0 "(low level).

이와같이 구성되는 종래 전압레벨검출회로의 동작 및 존래회로에 따른 문제점을 제 2a 및 b 도의 제 1 도의 전압레벨검출회로에 따른 각부전류파형 및 전압파형도를 참조해 설명하면 다음과 같다.Problems related to the operation and existing circuit of the conventional voltage level detection circuit configured as described above will be described with reference to the respective current waveforms and the voltage waveform diagrams according to the voltage level detection circuits of FIGS. 2A and 1B.

전압레벨검출회로의 동작전원전압인 VCC, VSS를 인가시킨 상태에서 기준전압(VP)을 NMOS트랜지스터(MN1)의 게이트에 인가하면, 기준레벨발생부(1)는 NMOS트랜지스터(MN1)와 PMOS트랜지스터(MP1)의 도통저항값에 의해 VCC와 VSS사이에 전압을 상기 도통저항비로 배분을 하여 NMOS트랜지스터(MN1)의 드레인측인 기준레벨발생노드(N1)의 전압(V1)으로 나타나며, 이 기준레벨전압(V1)은 비교출력부(2)의 PMOS트랜지스터(MP2)의 게이트바이어스전압이 된다.When the reference voltage V P is applied to the gate of the NMOS transistor MN 1 while the operating voltages V CC and V SS of the voltage level detection circuit are applied, the reference level generator 1 generates an NMOS transistor MN. 1 ) and the voltage between V CC and V SS are divided by the conduction resistance ratio according to the conduction resistance value of the PMOS transistor MP 1 , so that the reference level generating node N 1 on the drain side of the NMOS transistor MN 1 is distributed. appears as a voltage (V 1), the reference voltage level (V 1) is the gate bias voltage of the PMOS transistor (MP 2) of the comparison output unit (2).

이때, 비교출력부(2)에 입력신호전압(VS)이 NMOS트랜지스터(MN2)의 게이트에 인가되면, 제 2 도에 도시된 제 1 도에 따른 시뮬레이션(Simulation)결과를 보인 파형도에서와 같이 입력신호전압(VS)이 t1시점에 접근하여 통과하는 경우인 논리 "0"에서 논리 "1"로 천이하는 경우에, 입력신호전압(VS)이 기준전압(VP)보다 낮을 때에는 PMOS트랜지스터(MP2)와 NMOS트랜지스터(MN2)를 통하여 흐르는 전류[제 2a 도의 I2]가 거의 없고, 이에따라 전압레벨검출출력(V2)은 제 2b 도의 V2파형과 같이 논리 "1" 출력이 된다. 그러나 입력신호전압(VS)이 기준전압(VP)에 근접하는 순간 균형이 깨지면서 PMOS트랜지스터(MP2)와 NMOS트랜지스터(MN2)에는 급격히 전류(I2)가 흐르기 시작하고, 이에따라 전압레벨검출출력(V2)은 순간적으로 논리"0"로 천이된다.At this time, the comparison output unit (2) to the input signal voltage (V S), the NMOS transistor is applied to the gate of the (MN 2), the simulation according to the first shown in Figure 2 also (Simulation) in a waveform chart showing a result When the input signal voltage (V S ) transitions from logic "0", which is the case where the input signal voltage (V S ) approaches and passes through t 1 to logic "1", the input signal voltage (V S ) is greater than the reference voltage (V P ). When it is low, there is almost no current [I 2 in FIG. 2a] flowing through the PMOS transistor MP 2 and the NMOS transistor MN 2 , so that the voltage level detection output V 2 is similar to the waveform of V 2 in FIG. 2b. 1 "output. However, as soon as the input signal voltage V S approaches the reference voltage V P , the balance is broken and a current I 2 begins to flow rapidly through the PMOS transistor MP 2 and the NMOS transistor MN 2 . The detection output V 2 transitions to logic " 0 " instantaneously.

또한 입력신호전압(VS)이 기준전압(VP)보다 높을 때(t1에서 t2)에는 PMOS트랜지스터(MP2)와 NMOS트랜지스터(MN2)를 통하여 흐르는 전류(I2)는 PMOS트랜지스터(MP1)와 NMOS트랜지스터(MN1)를 통하여 흐르는 기준전류[제 2a 도의 I1]보다 많은 전류가 흐르게 되어 전압레벨검출출력(V2)는 논리 "0"이 나타난다. 이후 입력신호전압(VS)이 기준전압(VP)에 근접하는 시점(t2)에 NMOS트랜지스터(MN2)는 턴오프상태가 되면서 전류(I2)가 차단되어 전압레벨검출력(V2)은 순간적으로 논리 "1"로 천이된다.Also, when the input signal voltage V S is higher than the reference voltage V P (t 1 to t 2 ), the current I 2 flowing through the PMOS transistor MP 2 and the NMOS transistor MN 2 is the PMOS transistor. More current flows than the reference current [I 1 in FIG. 2a] flowing through the MP 1 and the NMOS transistor MN 1 so that the voltage level detection output V 2 has a logic “0”. Since the input signal voltage (V S) NMOS transistor at the time (t 2) that is close to the reference voltage (V P) (MN 2) is a current (I 2) is cut off as a off-state voltage level geomchulryeok (V 2 ) Instantaneously transitions to logic "1".

그러나, 이와같은 종래 전압레벨 검출회로에서는 제 2a 도에 도시된 바와같이 입력신호전압(VS)이 기준전압(VP)보다 큰 경우(t1에서 t2시점)에 PMOS트랜지스터(MP2)와 NMOS트랜지스터(MN2)가 도통상태로써, 그에따라 흐르는 전류(I2)는 기준전류(I1)보다 큰 전류가 계속 흐르게 되어 많은 전력소모가 있게된다.However, in such a conventional voltage level detection circuit, as shown in FIG. 2A, when the input signal voltage V S is greater than the reference voltage V P (time t 1 to t 2 ), the PMOS transistor MP 2 is used. And the NMOS transistor MN 2 are in a conductive state, so that the current I 2 flowing in the current continues to flow larger than the reference current I 1 , resulting in a lot of power consumption.

따라서, 본 발명의 목적은 전력소모가 큰 종래회로의 문제점을 감안하여, 입력신호전압이 기준전압보다 큰 경우인 즉, 출력논리가 하이레벨일때, 비교출력부에 흐르는 전류를 거의 흐르지 않도록 차단시켜 전력소모를 줄이도록 하는 전압레벨검출회로를 제공하기 위한 것이다.Accordingly, an object of the present invention is to consider a problem of a conventional circuit with a large power consumption, so that when the input signal voltage is higher than the reference voltage, that is, when the output logic is at a high level, the current flowing to the comparison output part is almost blocked. To provide a voltage level detection circuit to reduce power consumption.

이와같은 본 발명의 목적은 기준전압에 따라 기준레벨발생부의 동작전원을 공급하도록 PMOS트랜지스터를 연결하고, 입력신호전압에 따라 비교출력부의 동작전원을 공급하도록 PMOS 트랜지스터를 연결하여 달성시키는 것으로, 이를 첨부된 도면을 참조해 설명하면 다음과 같다.The object of the present invention is to achieve by connecting the PMOS transistor to supply the operating power of the reference level generator according to the reference voltage, and the PMOS transistor to supply the operating power of the comparison output unit according to the input signal voltage. A description with reference to the drawings as follows.

제 3 도는 본 발명에 따른 전압레벨검출회로도로서, 이에 도시된 바와같이 기준전압(VP)을 게이트에 인가받는 NMOS트랜지스터(MN1)의 소오스가 VSS단자에 접속되고, 그 NMOS트랜지스터(MN1)의 드레인이 기준레벨발생노드(N1)에 접속되며, PMOS트랜지스터(MP1)의 게이트와 드레인이 상기 기준레벨발생노드(N1)에 접속되어 그 기준레벨발생노드(N1)의 전압을 기준레벨전압(V1)으로 출력하는 기준레벨발생부(1)와, 그 기준레벨발생부(1)의 기준레벨발생노드(N1)에 게이트가 접속된 PMOS트랜지스터(MP2)의 드레인이 논리출력노드(N2)에 접속되고, 입력신호전압(VS)을 게이트에 인가받는 NMOS트랜지스터(MN2)의 소오스가 VSS단자에 접속되어 그 NMOS트랜지스터(MN2)의 드레인이 상기 논리출력노드(N2)에 접속되어 그 논리출력노드(N2)의 출력을 전압레벨검출출력(V2)으로 하는 비교출력부(2)로 구성된 전압레벨검출회로에 있어서, 상기 기준전압(VP)을 게이트에 인가받는 PMOS트랜지스터(MP11)의 소오스를 VCC단자에 접속하고, 그 PMOS트랜지스터(MP11)의 드레인을 상기 기준레벨발생부(1) PMOS트랜지스터(MP1)의 소오스에 접속하며, 상기 입력신호전압(VS)을 게이트에 인가받는 PMOS트랜지스터(MP12)의 소오스를 VCC단자에 접속하고, 그 PMOS트랜지스터(MP12)의 드레인을 상기 비교출력부(2) PMOS트랜지스터(MP2)의 소오스에 접속하여 기준전압(VP)및 입력신호전압(VS)에 따라 기준레벨발생부(1) 및 비교출력부(2)의 동작전원인 VCC가 공급되도록 구성한다.3 is a circuit diagram of a voltage level detection circuit according to the present invention, in which a source of an NMOS transistor MN 1 to which a reference voltage V P is applied to a gate is connected to a V SS terminal, and the NMOS transistor MN thereof. 1) is connected to the reference level generator node (N 1), the drain of the PMOS transistor (MP 1), the reference level generator node (N 1) and a gate and a drain of the connected to the reference level generator node (N 1) A reference level generator 1 for outputting a voltage as a reference level voltage V 1 , and a PMOS transistor MP 2 having a gate connected to the reference level generator node N 1 of the reference level generator 1 . The drain is connected to the logic output node (N 2 ), the source of the NMOS transistor (MN 2 ) to which the input signal voltage (V S ) is applied to the gate is connected to the V SS terminal, and the drain of the NMOS transistor (MN 2 ) is connected. the logic output node (N 2) is connected to the logic output node (N 2) output a voltage level detection of In the output (V 2) to a voltage level detection circuit configured to compare the output unit (2) which, connected to the source of the PMOS transistor (MP 11) receiving applying the reference voltage (V P) to the gate to the V CC terminal, of the PMOS transistor (MP 11) drain the reference level generator (1) PMOS transistors and connected to a source of (MP 1), the input signal voltage (V S) a PMOS transistor (MP 12) subject to the gate of The source is connected to the V CC terminal and the drain of the PMOS transistor MP 12 is connected to the source of the PMOS transistor MP 2 of the comparison output section 2 so that the reference voltage V P and the input signal voltage V S are connected. VCC, which is an operating power source of the reference level generator 1 and the comparison output unit 2, is supplied.

이와같이 구성되는 본 발명의 작용효과를 첨부한 제 4a 및 b 도의 제 3 도 본 발명에 따른 전압레벨 검출회로의 각부전류파형 및 전압파형도와, 제 5 도 본 발명과 종래의 전압레벨검출회로에서의 최대소모전류량을 비교한 일실시예를 보인 비교표를 참조해 설명하면 다음과 같다.4A and 3B with the effects of the present invention configured as described above, FIG. 3 shows the current waveforms and voltage waveforms of the respective parts of the voltage level detecting circuit according to the present invention, and FIG. 5 shows the present invention and the conventional voltage level detecting circuit. Referring to the comparison table showing an embodiment in which the maximum current consumption is compared as follows.

PMOS트랜지스터(MP11),(MP12)이 소오스와 NMOS트랜지스터(MN1),(MN2)의 소오스가 각기 VCC,VSS를 인가시킨 상태에서 기준전압(VP)을 기준레벨발생부(1)의 NMOS트랜지스터(MN1) 및 PMOS트랜지스터(MP11)의 게이트에 공통인가시키면, 그 기준전압(VP)의 크기에 따라 PMOS트랜지스터(MP11,MP1) 및 NMOS트랜지스터(MN1)의 도통량이 결정되면서, 그에따른 저항값에 의해 VCC및 VSS사이의 전압이 그 저향비에 따라 분압되어 PMOS트랜지스터(MP1) 및 NMOS트랜지스터(MN1)의 드레인 접속점인 기준레벨노드(N1)에 제 4a 도의 I1전류파형 및 제 4b 도의 V1전압파형과 같이 기준레벨출력이 나타난다.The reference level generator generates the reference voltage V P while the sources of the PMOS transistors MP 11 and MP 12 apply V CC and V SS to the sources and the sources of the NMOS transistors MN 1 and MN 2 , respectively. If it is common to the gates of the NMOS transistor MN 1 and the PMOS transistor MP 11 of ( 1 ), the PMOS transistors MP 11 and MP 1 and the NMOS transistor MN 1 depending on the magnitude of the reference voltage V P. ), The voltage between V CC and V SS is divided by the resistance ratio according to the resistance value, and the reference level node (DN) of the drain connection point of the PMOS transistor MP 1 and the NMOS transistor MN 1 is divided. N 1 ) shows the reference level output like the I 1 current waveform of FIG. 4A and the V 1 voltage waveform of FIG. 4B.

즉, 기준레벨노드(N1)의 전압(V1)은 기준전압(VP)에 의해 결정되어 일정값으로 균형을 유지하면서 비교출력부(2)의 PMOS트랜지스터(MP2)게이트에 인가된다. 이에따라 그 PMOS트랜지스터(MP2)는 일정턴온량이 결정되어 PMOS트랜지스터(MP12)를 통해 인가되는 VCC를 비교출력노드(N-)에 전달한다.That is, the voltage V 1 of the reference level node N 1 is determined by the reference voltage V P and is applied to the PMOS transistor MP 2 gate of the comparison output unit 2 while maintaining the balance at a constant value. . Accordingly, the PMOS transistor MP 2 determines a constant turn-on amount and transfers V CC applied through the PMOS transistor MP 12 to the comparison output node N − .

이때, 전압레벨검출을 위한 입력신호전압(VS)를 제 4b 도에 도시한 VS전압파형과 같은 신호전압으로 비교출력부(2)의 NMOS트랜지스터(MP12)및 NMOS트랜지스터(MN2)의 턴온량이 반비례적으로 결정되는데, 제 4b 도에 도시된 바와같이 입력신호전압(VS)이 기준전압(VP)에 근접할때 즉, t0에서 t1시점으로 근접할때 PMOS트랜지스터(MP12)는 턴온상태이고 NMOS트랜지스터(MN2)는 턴오프상태로써 비교출력부(2)의 논리출력노드(N2)에는 논리 "1"의 전압이 나타나고, 입력신호전압(VS)이 기준전압(VP)과 같아지는 시점(t1)에서 비교출력부(2)의 전류(I2)는 제 4a 도에 도시한 I2전류파형과 같이 급격한 상승을 보이며, 이후(t1시점이후)입력신호전압(VS)이 기준전압(VP)보다 커지면, 논리출력노드(N2)에는 논리레벨"0"이 나타난다.At this time, NMOS transistor (MP 12) of the comparison output unit (2) into a signal voltage, such as a V S voltage waveform showing the input signal voltage (V S) for a voltage level detector of claim 4b road and the NMOS transistor (MN 2) The turn-on amount of is inversely determined. As shown in FIG. 4B, when the input signal voltage V S approaches the reference voltage V P , that is, from the time point t 0 to t 1 , the PMOS transistor (MP 12 ) is turned on and the NMOS transistor (MN 2 ) is turned off. The logic output node (N 2 ) of the comparison output section ( 2 ) shows a logic "1" voltage and the input signal voltage (V S ). At the time point t 1 equal to the reference voltage V P , the current I 2 of the comparison output section 2 shows a sharp rise as shown in the I 2 current waveform shown in FIG. 4a, and then (t 1). When the input signal voltage V S becomes larger than the reference voltage V P , the logic level “0” appears in the logic output node N 2 .

즉, 입력신호전압(VS)이 기준전압(VP)보다 커지면 NMOS트랜지스터(MN1)가 턴온되고 PMOS트랜지스터(MP12)가 턴오프되면서, 전류(I2)는 t1시점이후 급격히 떨어져서 흐르지 않게되고, 논리출력노드(N2)는 턴온된 NMOS트랜지스터(MN2)를 통해 VSS측에 바이패스되므로 확실히 논리레벨 "0"가 나타난다.That is, when the input signal voltage V S is greater than the reference voltage V P , the NMOS transistor MN 1 is turned on and the PMOS transistor MP 12 is turned off, and the current I 2 is sharply dropped after t 1. Since the logic output node N 2 is bypassed to the V SS side through the turned-on NMOS transistor MN 2 , the logic level “0” is clearly shown.

따라서, 기준레벨발생부(1)는 기준전압(VP)는 기준전압(VP)을 NMOS트랜지스터(MN1)의 게이트와 PMOS트랜지스터(MP11)의 게이트에 공통인가받아 제어되므로 씨모스(CMOS)회로와 유사하게 동작하여 제 5도의 최대치 전류량 비교표에서 비교되는 바와같이 기준레벨발생부(1)에 흐르는 전류(I1)는 본 발명에 따른 회로(제 3 도)에서 종래의 회로(제 1 도)에서 보다 기준전압(VP)이 1V,2V,3V로 증가될수록 전류소모량은 작아진다.Thus, the reference level generator (1) is a reference voltage (V P) is said because a common application accepts control the gate of a gate and a PMOS transistor (MP 11) of the reference voltage (V P) NMOS transistor (MN 1) Moss ( The current I 1 flowing through the reference level generator 1 is similar to that of the conventional circuit (FIG. 3) according to the present invention. The current consumption decreases as the reference voltage V P increases to 1V, 2V, and 3V.

또한, 비교출력부(2)는 입력신호전압(VS)을 NMOS트랜지스터(MN2)의 게이트와 PMOS트랜지스터(MP12)의 게이트에 공통인가 받아 제어되어 VCC와 VSS사이에 흐르는 전류(I2)량을 제어하므로, 입력신호전압(VS)이 기준전압(VP)에 근접하는 시점(t1,t2)에서만 PMOS트랜지스터(MP12),(MP2) 및 NMOS트랜지스터(MN2)가 도통상태로 전류(I2)가 흐르고, PMOS트랜지스터(MP12) 및 NMOS트랜지스터(MN2)의 문턱(Thresold) 전압(VTHL)보다 크거나 작은 입력신호전압(VS)이 인가될때는 PMOS트랜지스터(MP12) 또는 NMOS트랜지스터(MN2)가 턴오프되어 전류(I2)루프가 차단되므로, 제 5 도의 비교표에서 보는 바와같이 입력신호전압(VS)이 기준전압(VP)과 같은 전압인 문턱전압(VTHL)일때의 최대전류는 본 발명에 다른 I2전류가 종래회로에서 I2전류보다 휠씬 적게 흐르게 되고, 본 발명에서는 입력신호전압(VS)이 기준전압(VP)보다 큰 경우(t1에서t2)에 제 4a 도의 I2전류파형과 같이 PMOS트랜지스터(MP12)가 턴오프되어 VCC를 차단하므로 전류(I2)가 흐르지 않게된다. 이에따라 제 1 도의 종래회로와 제 3 도의 본 발명에 따른 회로의 전류(I1),(I2)소모량을 비교하면 본 발명에 따른 회로에서의 전력소모량이 월등히 줄어들게 된다.In addition, the comparison output unit 2 is controlled by receiving the input signal voltage V S in common with the gate of the NMOS transistor MN 2 and the gate of the PMOS transistor MP 12 to control the current flowing between V CC and V SS. I 2) so controls the amount, the input signal voltage (V S) the reference voltage (V P) Close-up time (t 1, for the t 2) only on the PMOS transistor (MP 12), (MP 2 ) and an NMOS transistor (MN 2 ) When the current I 2 is in a conducting state and an input signal voltage V S greater than or less than the threshold voltage VTHL of the PMOS transistor MP 12 and the NMOS transistor MN 2 is applied. Since PMOS transistor (MP 12 ) or NMOS transistor (MN 2 ) is turned off to cut off the current (I 2 ) loop, as shown in the comparison table of FIG. 5, the input signal voltage (V S ) is the reference voltage (V P ) the same voltage, the maximum current of the threshold voltage (VTHL) when flow is much less than the current I 2 in the prior art is another current I 2 in the inventive circuit, this to When the input signal voltage V S is greater than the reference voltage V P (t 1 to t 2 ), the PMOS transistor MP 12 is turned off as shown in the I 2 current waveform of FIG. 4a to block V CC . Therefore, the current I 2 does not flow. Accordingly, when the currents I 1 and I 2 of the conventional circuit of FIG. 1 and the circuit of FIG. 3 are compared, the power consumption in the circuit according to the present invention is greatly reduced.

이상에서 설명한 바와같이 본 발명은 입력신호레벨을 기준레벨에 비교하여 논리신호로 출력할때 동작전류흐름도를 제어하여 전류흐름량을 최소화시킴으로써 불필요한 전력소모를 줄여 반도체 칩회로설계등에 유용한 효과가 있다.As described above, the present invention has a useful effect in designing semiconductor chip circuits by reducing the power consumption by minimizing the amount of current flow by controlling the operation current flow rate when outputting the input signal level to the reference level as a logic signal.

Claims (1)

기준전압(VP)에 따라 기준레벨(V1)을 발생하는 기준레벨발생부(1)와, 그 기준레벨(V1)과 입력신호전압(VS)을 비교하여 논리출력(V2)을 하는 비교출력부(2)로 구성되는 전압레벨검출회로에 있어서, 상기 기준전압(VP)에 따라 기준레벨발생부(1)에 동작전원(VCC)을 공급하도록 PMOS트랜지스터(MP11)를 연결하고, 상기 입력신호전압(VS)에 따라 상기 비교출력부(2)에 동작전원(VCC)을 공급하도록 PMOS트랜지스터(MP12)를 연결하여 구성하는 것을 특징으로 하는 전압레벨검출회로.The reference level generator 1 generating the reference level V 1 according to the reference voltage V P , and the logic level V 2 by comparing the reference level V 1 with the input signal voltage V S. In the voltage level detecting circuit comprising the comparison output section 2, the PMOS transistor MP 11 is supplied to supply the operating power supply V CC to the reference level generating section 1 according to the reference voltage V P. the connection and the voltage level detection, characterized in that for configuration by connecting a PMOS transistor (MP 12) to supply an operating power supply (V CC) to the comparison output unit (2) according to the input signal voltage (V S) circuit .
KR1019910000386A 1991-01-12 1991-01-12 Voltage level detecting circuit KR930008658B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019910000386A KR930008658B1 (en) 1991-01-12 1991-01-12 Voltage level detecting circuit
JP4003080A JPH0587841A (en) 1991-01-12 1992-01-10 Voltage level detector
DE4200623A DE4200623C2 (en) 1991-01-12 1992-01-13 Voltage level detector circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000386A KR930008658B1 (en) 1991-01-12 1991-01-12 Voltage level detecting circuit

Publications (2)

Publication Number Publication Date
KR920015728A KR920015728A (en) 1992-08-27
KR930008658B1 true KR930008658B1 (en) 1993-09-11

Family

ID=19309687

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000386A KR930008658B1 (en) 1991-01-12 1991-01-12 Voltage level detecting circuit

Country Status (3)

Country Link
JP (1) JPH0587841A (en)
KR (1) KR930008658B1 (en)
DE (1) DE4200623C2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100475896B1 (en) * 1997-12-12 2005-07-18 주식회사 하이닉스반도체 High Voltage Regulation Circuit
FR2822956B1 (en) * 2001-04-02 2003-06-06 St Microelectronics Sa POWER DETECTION DEVICE

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4453094A (en) * 1982-06-30 1984-06-05 General Electric Company Threshold amplifier for IC fabrication using CMOS technology
JP2514988B2 (en) * 1987-11-17 1996-07-10 株式会社東芝 Sense amplifier circuit
JP2695891B2 (en) * 1989-01-19 1998-01-14 沖電気工業株式会社 Comparator circuit

Also Published As

Publication number Publication date
JPH0587841A (en) 1993-04-06
DE4200623A1 (en) 1992-09-10
KR920015728A (en) 1992-08-27
DE4200623C2 (en) 1996-11-28

Similar Documents

Publication Publication Date Title
KR930009148B1 (en) Source voltage control circuit
KR100301368B1 (en) Power On Reset Circuit
KR940003809B1 (en) Ttl to cmos input buffer
US4820937A (en) TTL/CMOS compatible input buffer
US4752703A (en) Current source polarity switching circuit
US5640122A (en) Circuit for providing a bias voltage compensated for p-channel transistor variations
KR19980701483A (en) CMOS POWER ON RESET CIRCUIT
US5668483A (en) CMOS buffer having stable threshold voltage
KR20010049227A (en) Level adjustment circuit and data output circuit thereof
US4677321A (en) TTL compatible input buffer
US5027053A (en) Low power VCC /2 generator
KR100218078B1 (en) Substrate electric potential generation circuit
JPH04351791A (en) Data input buffer for semiconductor memory device
US4004158A (en) Keyed comparator
EP0503803B1 (en) Switching circuit
US4786825A (en) CMOS Schmitt trigger circuit using ratioed currents to establish switching thresholds
US6046617A (en) CMOS level detection circuit with hysteresis having disable/enable function and method
EP0511856A1 (en) Reference generator
KR20000068510A (en) Output stage with slewing control means
KR930008658B1 (en) Voltage level detecting circuit
US5408145A (en) Low power consumption and high speed NOR gate integrated circuit
EP0651311A2 (en) Self-exciting constant current circuit
KR20040062646A (en) Output driver comprising an improved control circuit
JPH05129922A (en) Semiconductor integrated circuit device
US20060145749A1 (en) Bias circuit having reduced power-up delay

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050824

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee