JPH04104509A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction for power-on by connecting the output of an inverter, where first P-channel and N-channel MOS transistors TRs are complementarily connected, to an output stage and inputting a control signal from the external to a second P-channel MOSTR connected between a supply voltage terminal on a higher order side and the first P--channel MOS TR. CONSTITUTION:A P-channel MOS TR P5 is provided between a P-channel MOS TR P1 constituting a CMOS type inverter 2 and a low voltage supply terminal 12 on the higher order side in an output circuit. A resistance R2 is connected between the gate of the P-channel MOS TR P5 and the low voltage supply terminal 12, and the gate of this MOS TR is connected to a control terminal 5, and the control signal is inputted to this terminal. The input terminal of the CMOS type inverter 2 is connected to a data input terminal 6, and data from an in-circuit in the preceding stage is directly inputted to the data input terminal 6 without passing an OR gate. Thus, the malfunction of data transfer is prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an output circuit, and in particular, a circuit that drives a display element such as a liquid crystal or a fluorescent display tube, or converts a signal level to transfer data. The present invention relates to a circuit configuration of an output circuit for

[Conventional technology]

Generally, this type of output circuit is characterized by the use of multiple types of power supply voltages.

A circuit diagram of an example of a conventional output circuit is shown in FIG.

This output circuit consists of a two-man OR gate 1, a CMOS type inverter 2 consisting of a P-channel MOS transistor P and an N-channel MOS transistor N1, and an open-train connected N-channel MOS transistor N2.

A resistor R1 connected to the drain of the N-channel MOS transistor N2 in the output stage represents a load connected to the outside of this output circuit.

In this output circuit, OR gate 1 and inverter 2 are
The high-voltage side power supply voltage operates at a low voltage of, for example, 5 cm, while the resistor R1 as an external load connected to the output terminal 3 is connected to the high-voltage power supply terminal 4 of, for example, 10 cm or higher. There is.

Note that the value of the high voltage power supply to which the resistor R1 is connected differs depending on the type of load.

In an output circuit with the circuit configuration as above.

A control signal is input from the outside to a control terminal 5, which is one of the two input terminals of the OR gate 1.

This control signal controls whether or not to operate the output circuit; when the control signal is at a low level, the output circuit operates, and when the control signal is at a high level, the output circuit does not operate.

A data input terminal 6, which is the other input terminal of the OR gate 1, receives data from an internal circuit (not shown) at the previous stage.

When the control signal is at a low level, this data is input to the inverter 2 through the OR gate 1;
through the output stage N-channel MOS transistor N2
drive.

Next, FIG. 5 shows a circuit diagram of another example of the conventional output circuit.

This output circuit includes a level shift circuit for converting the signal level of data from the previous internal circuit and transferring the data to the outside.

This output circuit includes a two-man OR gate 1, three inverters 7, 8, a level shift circuit 10, a P-channel MOS transistor array 2, and an N-channel MO
It consists of an output stage 11 in which S transistors N3 are connected in series.

The level shift circuit 10 includes P-channel MOS transistors P3 and P4 and N-channel MOS transistors N4 and N5 connected in a flip-flop configuration.

This output circuit includes an OR gate 1 and an inverter 7.
8 and 9 operate with a low power supply voltage on the high side, and the level shift circuit 10 and output stage 11 are connected to the high voltage power supply terminal 4.

Whether this output circuit operates or not is controlled by a control signal input to the control terminal 5 of the OR gate 1.

Data from the internal circuit of the previous stage is input to the data input terminal 6 of the OR gate 1, and is input to the gate of the P-channel MOS transistor array 2 of the output stage 11 via the level shift circuit 10. and 9 to the gate of the N-channel MOS transistor N3 of the output stage 11 to drive the output stage 11.

[Problem to be solved by the invention]

As explained above, this type of output circuit uses a plurality of power supply voltages.

In relation to the above, in conventional output circuits of this type,
Malfunctions may occur when the power is turned on.

The explanation will be given below.

In conventional output circuits, there are two
Consider the case where two high-level power supplies are turned on.

In this case, if you turn on the low-voltage power supply first and the high-voltage power supply later, the circuit connected to the low-voltage power supply (in Figure 4, the OR
Gate 1 and CMOS type inverter 2, O in FIG.
After the logical state of R gate 1 and inverters 7, 8 and 9) is determined, the circuit connected to high voltage power supply terminal 4 (
In Figure 4, the output stage N-channel MOS transistor N
2 In FIG. 5, the level shift circuit 10 and the output stage 11) are in operation.

Therefore, if the control signal is set to high level before turning on the power, the output P
Channel MOS transistor and N-channel MOS
Since the potential of the gates of the transistors is fixed, these MOS transistors remain off even if the high voltage power supply is turned on thereafter.

That is, the output circuit is reliably controlled by the control signal and does not malfunction.

However, if the order of turning on the high-level power supply is reversed from the above,
If you turn on the high voltage power supply first and then the low voltage power supply,
Before the logic state of the circuit connected to the low voltage power supply is determined, the power supply voltage is applied to the circuit connected to the high voltage power supply.

In this case, since a voltage is applied between the drain and source of the MOS transistor in the output stage before the gate potential is determined, the output may turn on regardless of the logic state of the control signal.

That is, even if the output stage is previously set to the OFF state by an external control signal, the output may be transiently turned ON when the power is turned on.

The duration of such a malfunction state depends on the operating speed of the OR gate 1 and the inverters 7.8 and 9 connected to the low voltage power supply.

In the case of FIG. 5, it also depends on the operating state of the level shift circuit 10.

This level shift circuit 10 has a slow operating speed and has a flip-flop type circuit configuration, so it has the function of holding data.

Therefore, especially in the output circuit shown in FIG. 5, it is important to prevent the above-mentioned malfunction from occurring.

[Means to solve the problem]

The output circuit of the present invention has a gate of an N-channel MOS transistor in the output stage,
The output of an inverter in which a first P-channel MOS transistor and an N-channel MOS transistor are connected complementary to each other is connected, and a second P-channel MOS transistor is connected between the high-potential side power supply voltage terminal and the first P-channel MOS transistor.
A circuit in which the transistor is connected so that an external control signal is input to the gate of the second P-channel MOS transistor, and a gate of the P-channel MOS transistor in the output stage.
The output of an inverter in which a first N-channel MOS transistor and a P-channel MOS transistor are connected complementary to each other is connected, and a second N-channel MOS transistor is connected between the low-potential side power supply voltage terminal and the first N-channel MOS transistor.
Connect the S transistor to the second N-channel MOS
The present invention is characterized by having at least one circuit connected to the gate of the transistor so that an external control signal is input thereto.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing the circuit configuration of a first embodiment of the present invention.

In this embodiment, compared to the conventional output circuit shown in FIG.
P-channel MO constituting CMOS type inverter 2
A P-channel MOS transistor P5 is provided between the S transistor P1 and the low-voltage power supply terminal 12 of the high-potential side power supply.

A resistor R2 is connected between the gate of this P-channel MOS transistor P5 and the low voltage power supply terminal 12, and the gate of this MOS transistor is connected to the control terminal 5, to which a control signal is input.

In addition, the input terminal of the CMOS type inverter 2 is connected to the data input terminal 6, and the data from the internal circuit of the previous stage is input to O
The data is directly input to this data input terminal 6 without going through the R gate.

This embodiment operates as follows.

First, when the control signal is set to low level, P
Since the channel MOS transistor P is in the on state, it operates in the same way as a conventional output circuit, and the N-channel MOS transistor N2 at the output stage operates according to data from the internal circuit.

On the other hand, when the control terminal 5 is open or the control signal is set to high level, the P-channel MOS transistor P is always in the off state, and the N-channel MOS transistor P in the output stage
OS transistor N2 does not operate.

In this state, the path from the gate of the output stage N-channel MOS transistor N2 to the low voltage power supply terminal 12 is P
It is cut off by channel MOS transistor P5.

Therefore, when the high-voltage power supply is turned on, the gate potential of the N-channel MOS transistor N2 in the output stage does not become high level, and the output does not turn on even transiently.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram showing the circuit configuration of a second embodiment of the present invention.

In this embodiment, the output stage is constructed by connecting a P-channel MOS transistor P with an open drain.

Therefore, in this embodiment, unlike the first embodiment shown in FIG. or connected.

The high-level power supplies are commonly connected to the high-voltage power supply terminal 4.

A resistor R3 is connected between the gate of the N-channel MOS transistor N6 and the low-voltage power supply terminal 12 on the lower side, and the gate voltage of this MOS transistor is as follows.
It is controlled by a control signal input to the control terminal 5.

In this embodiment, when the control signal is set to a high level, the N-channel MOS transistor N6 is in an on state, so that the operation is similar to that of a conventional output circuit.

When the control terminal 5 is open or the control signal is set to low level, the N-channel MOS transistor N6
Since it is in the off state, the output does not turn on even transiently when the higher power supply voltage is turned on, as in the first embodiment.

Furthermore, a third embodiment of the present invention will be described.

FIG. 3 is a circuit diagram showing the circuit configuration of a third embodiment of the present invention.

This embodiment corresponds to the conventional output circuit shown in FIG.
N-channel MOS transistor N4 on the path connected to the gate of P-channel MOS transistor P2 of No. 1
An N-channel MOS transistor N6 is connected between the ground terminal 14 and the ground terminal 14.

And this N-channel MOS transistor N6
A resistor R3 is connected between the gate of and the ground terminal 14,
Further, the gate potential of this transistor is controlled by a control signal input to the control terminal 5.

Further, data from the internal circuit at the previous stage is input directly to the data input terminal 6 without going through an OR gate.

The operation of this embodiment will be explained below.

When the control signal at the control terminal 5 is set to a high level, the N-channel MOS transistor N6 is in the on state, so this embodiment operates in the same way as the conventional output circuit shown in FIG.

On the other hand, when the control signal 5 is open or set to a low level, the N-channel MOS transistor N6 is always in an off state.

Therefore, the gate potential of the P-channel MOS transistor P2 of the output stage 11 is the same as that of the P-channel MOS transistor P2 of the level shift circuit 10 connected to this gate.
Even if N-channel MOS transistor N3 is on, or even if N-channel MOS transistor N4 is on, it never becomes the ground potential.

That is, in this case, the P channel MO of the output stage 11
The S transistor P2 is always in an off state, and does not turn on even transiently when the high voltage power supply is turned on.

Furthermore, in this embodiment, the N-channel MOS of the output stage 11
If the inverter 9 connected to the gate of the transistor N has a circuit configuration as shown in the first embodiment shown in FIG. There are two things you can do to prevent it from turning on.

In the third embodiment described above, the case was described in which the output level of the output stage 11 was level-shifted to the higher side.
It is clear that the present invention is not limited to this, and can also be applied to a case where the level is shifted to a lower level.

Furthermore, the present invention can be applied to a circuit that uses a larger number of power supplies and shifts the output level both to the higher and lower sides.

In addition, the above-mentioned 1. In the second and third embodiments,
A MOS transistor (P-channel MOS transistor P5 in Fig. 1, P-channel MOS transistor P5,
In Figs. 2 and 3, a resistor (first
Although R2 in the figure and R3 in FIGS. 2 and 3 are connected, as is clear from the above explanation, the effects of the present invention are not impaired even if the above-mentioned resistor is not provided.

By providing the above-mentioned resistors R2 and R8, even if the control terminal 5 becomes open, P
Channel MOS transistor P5 and N channel M
Since the gate of the OS transistor N6 is biased to be in the off state, more reliable operation can be expected than in the case where there is no resistor.

〔Effect of the invention〕

As explained above, according to the present invention, the MO of the output stage is reliably maintained not only when the power is on but also when the power is turned on.
The S transistor can be controlled.

Therefore, it is possible to prevent the MOS transistor in the output stage from turning on transiently, so if the present invention is applied to an output circuit such as a display element, it is possible to prevent erroneous lighting, and also to prevent data transfer. If used in output circuits such as, it will have a great effect on preventing malfunctions in data transfer.

In addition, even in an output circuit with multiple power supplies including a level shift circuit, malfunctions due to inappropriate power-on order can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a circuit configuration of a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a circuit configuration of a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing a circuit configuration of a second embodiment of the present invention. A circuit diagram showing the circuit configuration of the third embodiment, FIG. 4 is a circuit diagram showing the circuit configuration of an example of the conventional output circuit, and FIG. 5 shows the circuit configuration of another example of the conventional output circuit. It is a circuit diagram. 1-OR gate, 2.7, 8.9-...inverter, 3
...Output terminal, 4...High voltage power supply terminal, 5...Control terminal, 6...Data input terminal, 10...Level shift circuit, 11...Output stage, 12...Low voltage power supply terminal,
13...Low side low voltage power supply terminal, 14...Grounding terminal.

Claims (1)

[Claims] 1. The output of an inverter in which a first P-channel MOS transistor and an N-channel MOS transistor are connected complementary to each other is connected to the gate of an N-channel MOS transistor in the output stage, and the output is connected to a high-potential side power supply voltage terminal. A second P-channel MOS transistor is connected between the first P-channel MOS transistor and the second P-channel MOS transistor.
Connect the OS transistor and connect the second P-channel MOS
A circuit connected so that an external control signal is input to the gate of the transistor, and a circuit connected to the gate of the P-channel MOS transistor in the output stage.
The output of an inverter in which a first N-channel MOS transistor and a P-channel MOS transistor are connected complementary to each other is connected, and the low-potential side power supply voltage terminal and the first N-channel MOS transistor are connected to each other.
A second N-channel MOS transistor is connected between the OS transistor and the second N-channel MOS transistor, and the second N-channel MOS transistor has at least one circuit connected so that an external control signal is input to its gate. An output circuit featuring: 2. The output circuit according to claim 1, wherein a resistor is connected between the gate of the second P-channel MOS transistor and the high-potential side power supply voltage terminal, and the output circuit is connected to the second N-channel MOS transistor.
An output circuit characterized in that a resistor is connected between the gate of the transistor and the low potential side power supply voltage terminal.