JP3086977B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device comprising a CMOS transistor and a bipolar transistor.

[0002]

2. Description of the Related Art Conventionally, an ECL circuit composed of bipolar transistors, a BiCMOS circuit composed of a combination of a PMOS transistor and an NMOS transistor and a bipolar transistor, and a CMOS composed of a PMOS transistor and an NMOS transistor have been used as a logic gate circuit.
A circuit is used. Each of these logic gate circuits is applied in accordance with its performance such as high speed, low power consumption, and high integration.

On the other hand, recently, with the miniaturization of semiconductor elements, a demand for a reduction in power supply voltage supplied to an integrated circuit on which the miniaturized semiconductor elements are mounted is rapidly increasing. Focusing on this low power supply voltage, a CMOS circuit is more excellent in low-voltage operation than a circuit composed of bipolar transistors.

FIG. 5 shows an inverter circuit using a CMOS circuit. In the figure, the CMOS inverter circuit is configured so that a pair of PMOS transistor 63 and NMOS transistor 64 are connected in series to perform a complementary operation.

[0005]

SUMMARY OF THE INVENTION The above-mentioned conventional CMO
The logic gate circuit using the S circuit is superior in low power supply voltage and low power consumption, but has a PMOS transistor and an NM.
Since the OS transistor is inferior to the bipolar transistor in current driving capability, the load dependence of the gate delay time increases, and the speed of the gate delay time remains a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has as its object to provide a logic gate circuit in which the gate delay time is less dependent on an output load while ensuring a low power supply voltage. Things.

[0007]

A semiconductor integrated circuit device according to the present invention has a first CMOS logic gate and an input terminal connected to an input terminal of the first CMOS logic gate. A second CMOS logic gate which performs the same logic operation as the gate, and an input terminal of which is connected to the second CMOS logic gate.
Connected to an output terminal of a logic gate, the output terminal of which is connected to the first terminal.
And a differentiating circuit connected to the output terminal of the CMOS logic gate.

Further, the semiconductor integrated circuit device of the present invention comprises a first CMOS inverter circuit comprising a pair of a PMOS transistor and an NMOS transistor;
A second CMOS inverter circuit having the input terminal connected to the input terminal of the OS inverter circuit and performing the same logical operation as the first CMOS inverter circuit, and the input terminal connected to the output terminal of the second CMOS inverter circuit; A differential circuit connected to the output terminal of the first CMOS inverter circuit and connected to the output terminal of the first CMOS inverter circuit.

Further, according to the semiconductor integrated circuit device of the present invention, a pair of PMOs whose input terminals are connected to input terminals of the circuit device are provided.
A first transistor composed of an S transistor and an NMOS transistor
And an NPN bipolar transistor having a collector connected to a source of a PMOS transistor, a base connected to a drain of the PMOS transistor, and an emitter connected to an output terminal of the circuit device, respectively, which constitute the first CMOS inverter circuit. , The train is the N
An NMOS transistor having a gate connected to the input terminal of the first CMOS inverter circuit, a source connected to the ground terminal, and an input terminal connected to the input terminal of the first CMOS inverter circuit. A second CMOS inverter circuit connected and performing the same logical operation as the first CMOS inverter circuit;
A differential circuit having an input terminal connected to an output terminal of the second CMOS inverter circuit and an output terminal connected to the output terminal.

Further, according to the semiconductor integrated circuit device of the present invention, a pair of PMOs whose input terminals are connected to input terminals of the circuit device are provided.
A first transistor composed of an S transistor and an NMOS transistor
And a first NPN having a collector connected to a source of a PMOS transistor constituting the first CMOS inverter circuit, a base connected to a drain of the PMOS transistor, and an emitter connected to an output terminal of the circuit device. A bipolar transistor, a second NPN transistor having a collector connected to the emitter of the first NPN transistor and an emitter connected to the ground terminal;
An NMOS transistor having a drain connected to the emitter of the first NPN bipolar transistor, a gate connected to the input terminal of the first CMOS inverter circuit, and a source connected to the base of the second NPN transistor; An element for extracting a base charge of the second NPN transistor connected between the base and the emitter of the NPN transistor; and an input terminal of the first CMOS inverter circuit having an input terminal connected to the input terminal of the first CMOS inverter circuit. A second CMOS inverter circuit performing the same logical operation; and a differentiating circuit having an input terminal connected to an output terminal of the second CMOS inverter circuit and an output terminal connected to the output terminal. Features.

Further, in the semiconductor integrated circuit device according to the present invention, a pair of PMOs whose input terminals are connected to input terminals of the circuit device are provided.
A first transistor composed of an S transistor and an NMOS transistor
And a first NPN having a collector connected to a source of a PMOS transistor constituting the first CMOS inverter circuit, a base connected to a drain of the PMOS transistor, and an emitter connected to an output terminal of the circuit device. A bipolar transistor, a first NMOS having a drain connected to the emitter of the NPN bipolar transistor, a gate connected to the input terminal of the first CMOS inverter circuit, and a source connected to the ground terminal, respectively.
A transistor, a second CMOS inverter circuit having an input terminal connected to an input terminal of the first CMOS inverter circuit and performing the same logical operation as the first CMOS inverter circuit, and a second CMOS inverter circuit. A collector is provided at the source of the PMOS transistor to be constructed,
A second NPN bipolar transistor having a base connected to the drain of the OS transistor; a drain connected to the emitter of the second NPN bipolar transistor; a gate connected to the input terminal of the second CMOS inverter circuit; Terminals connected to the second
And a differentiating circuit whose input terminal is connected to the emitter of the second NPN bipolar transistor and whose output terminal is connected to the output terminal.

Further, according to the semiconductor integrated circuit device of the present invention, a pair of PMOs whose input terminals are connected to input terminals of the circuit device are provided.
CM consisting of S transistor and NMOS transistor
An OS inverter circuit, an NPN bipolar transistor having a collector connected to a source of a PMOS transistor constituting the CMOS inverter circuit, a base connected to a drain of the PMOS transistor, and an emitter connected to an output terminal of the circuit device, and a drain connected to the output terminal of the circuit device. An NMOS transistor is connected to the emitter of the NPN bipolar transistor, the gate is connected to the input terminal of the CMOS inverter circuit, and the source is connected to the ground terminal. The input terminal is connected to the base of the NPN transistor, and the output terminal is connected to the NPN transistor. A differentiating circuit connected to the output terminal.

Further, according to the semiconductor integrated circuit device of the present invention, a pair of PMOs whose input terminals are connected to input terminals of the circuit device are provided.
CM consisting of S transistor and NMOS transistor
A first N-channel transistor is connected to a source of a PMOS transistor constituting the OS inverter circuit and the CMOS inverter circuit, a collector is connected to a source of the PMOS transistor, a base is connected to a drain of the PMOS transistor, and an emitter is connected to an output terminal of the circuit device.
A PN bipolar transistor and a collector connected to the first N
A second NPN bipolar transistor having an emitter connected to the ground terminal, a drain connected to the emitter of the first NPN bipolar transistor, a gate connected to the input terminal of the CMOS inverter circuit, and a source connected to the emitter of the PN bipolar transistor; An NMOS transistor connected to the base of the second NPN transistor, a base charge extracting element of the second NPN transistor connected between the base and the emitter of the second NPN transistor, and the first NPN transistor; A differential circuit having an input terminal connected to the base of the bipolar transistor and an output terminal connected to the output terminal.

Further, according to the semiconductor integrated circuit device of the present invention, there is provided a first CMOS inverter circuit comprising a pair of a PMOS transistor and an NMOS transistor;
A second CMOS inverter circuit having an input terminal connected to the output terminal of the OS inverter circuit and performing the same logical operation as the first CMOS inverter circuit, and an input terminal connected to the input terminal of the first CMOS inverter circuit; A differential circuit connected to the output terminal of the second CMOS inverter circuit and connected to the output terminal of the second CMOS inverter circuit.

Further, in the semiconductor integrated circuit device according to the present invention, the differentiating circuit is constituted by a reactance element and an impedance element.

Further, in the semiconductor integrated circuit device according to the present invention, the impedance element is a resistor.

Further, in the semiconductor integrated circuit device according to the present invention, the impedance element is a MOS transistor.

[0018]

The semiconductor integrated circuit device having the above-described structure is, for example, shown in FIG.
At the inverter output of the first CMOS circuit 11,
Further, a pulse signal generated at the time of input transition is superimposed in the differentiating circuit 10 to speed up the gate delay time. That is, the PMOS transistor 4 and N
In the first CMOS inverter circuit 11 composed of the MOS transistor 5, when the potential at the input terminal 1 changes to the low level, the PMOS transistor 4 is turned on, and the potential at the output terminal 2 changes from the low level to the power supply terminal 3. The state transits to the high level which is the power supply voltage. At the same time, the low-level input signal input from the input terminal 1 by the second CMOS circuit 12 composed of the PMOS transistor 6 and the NMOS transistor 7 performing the same operation as the first CMOS inverter circuit 11 The inverted signal is input to a differentiating circuit 10 including a capacitor 8 and a resistor 9.

In the differentiating circuit 10, a positive pulse is generated, and the positive pulse is applied to the output terminal 2 and charged. As a result, the differentiating circuit 10 is connected to the inverted output of the first CMOS inverter circuit 11.
Of the first CMOS circuit 11 is superimposed.
The OS transistor 4 is turned on, and operates to accelerate the rise of the voltage level of the output terminal 2 to the high level.

When the potential at the input terminal 1 changes to the high level, the NMOS transistor 5 of the first CMOS inverter circuit 11 turns on, and the potential at the output terminal 2 drops to the ground potential and goes to the low level. At the same time, the high-level input signal is inverted to low level in the second CMOS inverter circuit 12, and this inverted signal causes a negative pulse to be generated in the differentiating circuit 10, and the negative pulse is applied and discharged to the output terminal 2. . As a result, this inverter circuit becomes the NM of the first CMOS inverter circuit 11.
The OS transistor 5 is turned on, and operates so that the potential at the output terminal 2 is accelerated to fall to the low level.

The differentiating circuit 10 having the function of increasing the current driving capability generates a rapidly rising and falling differential pulse, and the pulse width of the differential pulse is determined by the constant of the capacitor 8 and the resistor 9. It can be adjusted by numerical values. First CMOS circuit 11 is BiCM
Even with a circuit system such as an OS circuit or a BiNMOS circuit,
If the second CMOS circuit 12 is configured to take the same logic as the first CMOS circuit 11, the same effect can be obtained.

Therefore, the first CMOS circuit is provided by the differentiating circuit 10.
It is possible to obtain a semiconductor integrated circuit device in which the gate drive time is less dependent on the output load by compensating for the current driving capability of the circuit 11.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of an inverter circuit to which the present invention is applied. In FIG. 1, 1 is an input terminal, 2 is an output terminal, 3 is a power supply terminal, 4 is a PMOS transistor having a source connected to the power supply terminal 3, a gate connected to the input terminal 1, and a drain connected to the output terminal 2, respectively. The NMOS transistor 6 has a drain connected to the output terminal 2, a gate connected to the input terminal 1, and a source connected to the ground terminal. Reference numeral 6 denotes a source connected to the power supply terminal 3, a gate connected to the input terminal 1, and a drain connected to the input of the differentiating circuit 10. The PMOS transistor 7 is connected to the input side of the differentiating circuit 10, the gate is connected to the input terminal 1, and the source is connected to the ground terminal.

A differentiating circuit 10 comprising a capacitance 8 as a reactance element and a resistor 9 as an impedance element.
Has its output side connected to the output terminal 2 of the circuit device. That is, the PMOS transistor 4 and the NMOS transistor 5 constitute a first CMOS inverter circuit 11 which operates complementarily, and this CMOS inverter circuit 11
Invert the signal input from the input terminal 1 of the circuit device,
Output to output terminal 2. Also, the PMOS transistor 6
And a second CMO comprising an NMOS transistor 7
The output side of the S inverter circuit 12 is connected in series to the differentiating circuit 10, and these series circuits are composed of a PMOS transistor 4 and an NMOS transistor 5.
The input and output terminals of the inverter circuit 11 are connected in parallel.

In the above configuration, when the potential at the input terminal 1 changes to a low level, the CMOS inverter circuit 1
1 is turned on, and the output terminal 2
Is charged, and the potential at the output terminal 2 rises to a high level. At the same time, the CMOS inverter circuit 12 performs the same logical operation as the CMOS inverter circuit 11, and the PMOS transistor 6 is turned on.
Its output changes to high level. The differentiating circuit 10 generates a positive differential pulse in accordance with the state transition of the output signal of the CMOS inverter circuit 12, the positive differential pulse is superimposed on the output signal at the output terminal 2, and the charging of the output terminal load is accelerated.

On the other hand, when the potential at the input terminal 1 changes to the high level side, the NM of the CMOS inverter circuit 11
The OS transistor 5 is turned on, the charge charged in the parasitic capacitance at the output terminal 2 is discharged, and the potential at the output terminal 2 is pushed down to a low level. At the same time, the CMOS inverter circuit 12 performs the same logical operation.
The NMOS transistor 7 turns on, and its output changes to low level. The differentiating circuit 10 generates a negative differentiated pulse in accordance with the state transition of the output signal of the CMOS inverter circuit 12, the negative differentiated pulse is superimposed on the output signal at the output terminal 2, and the discharge of the output terminal load is accelerated.

If all the logical operations are to be operated at a low power supply voltage of 1 V or 1.5 V, a PMOS transistor 4 is required for a logic circuit composed of bipolar transistors.
And a CMOS circuit comprising the NMOS transistor 5 is superior. However, since the CMOS circuit composed of the PMOS transistor 4 and the NMOS transistor 5 has a lower current driving capability than the bipolar transistor, the load dependence of the delay time of the output signal is strong.
This leads to a reduction in signal propagation speed. Therefore, in this embodiment, the CMOS inverter circuit 11 composed of the PMOS transistor 4 and the NMOS transistor 5 is further connected to the CMOS inverter circuit 12 connected in parallel to the input / output terminals thereof in order to increase the driving capability while maintaining the low voltage operability. And a series circuit of a differential circuit 10 and a positive signal generated at the output terminal of the differential circuit 10 when the state of the input signal at the input terminal 1 changes.
The driving capability is improved by superimposing the negative pulse on the output signal at the output terminal 2.

FIG. 2 shows the configuration of another embodiment of the inverter circuit to which the present invention is applied. In the figure, elements having the same numbers as the elements in FIG. 1 have the same functions and the same operations as those in FIG. The present embodiment differs from the embodiment shown in FIG. 1 in the configuration of the same inverter circuit, but the PMOS transistor 24 and the NMOS transistor corresponding to the first CMOS inverter circuit 11 in FIG.
CMOS inverter circuit 2 including S transistor 25
6 at the output stage, the collector is at the power supply terminal 3, and the base is CM
An NPN bipolar transistor 20 having an emitter connected to the output terminal 22 is provided on the output side of the OS inverter circuit 25.
And the drain is the output terminal 22 and the gate is the input terminal 21
And the NMOS whose source is connected to the ground terminal, respectively.
BiNMOS constructed by adding transistor 23
This is a point-type inverter circuit. This BiNMOS type inverter circuit performs an inverter operation in which the potential of the output terminal 22 becomes high level when the NPN bipolar transistor 20 is turned on, and the potential of the output terminal 22 becomes low level when the NMOS transistor 23 is turned on.

The effect of improving the driving capability of the differentiating circuit 10 by the positive and negative differential pulses can be obtained in the same manner as in the above embodiment.

FIG. 3 shows the configuration of another embodiment of the inverter circuit to which the present invention is applied. In the figure, the elements having the same numbers as those in FIG. 1 are the elements having the same functions and the same operations as the elements in FIG. The present embodiment differs from the embodiment shown in FIG. 1 in the configuration of the same inverter circuit, but has a PM equivalent to the CMOS inverter circuit 11 in FIG.
An output stage of a CMOS inverter circuit 38 including an OS transistor 36 and an NMOS transistor 37 includes:
An NPN bipolar transistor 30 having an emitter connected to the output terminal 32, an NPN bipolar transistor 33 having a collector connected to the output terminal 32, a base connected to the source of the NMOS transistor 34, and an emitter connected to the ground terminal, respectively. 33 formed by adding an element 35 for extracting the base charge of
This is an iCMOS type inverter circuit.

Also in this embodiment, the effect of improving the driving ability by the positive and negative differential pulses of the differentiating circuit 10 can be obtained similarly.

FIG. 4 shows the configuration of an embodiment of a two-input NAND gate circuit to which the present invention is applied. In FIG.
Elements denoted by the same reference numerals have the same functions and the same operations as those elements in FIG. In the figure, an input terminal 41, an input terminal 42, an output terminal 52, a source is connected to the power supply terminal 3, a gate is connected to the input terminal 42, a drain is connected to the output terminal 52, and a PMOS transistor 44 is connected to the source. The PMOS transistor 43 is connected to the power supply terminal 3, the gate is connected to the input terminal 41, and the drain is connected to the output terminal 52. The drain is connected to the output terminal 52, the gate is connected to the input terminal 41, and the source is connected to the drain of the NMOS transistor 46. NM connected respectively
The OS transistor 45 and the NMOS transistor 46 whose gate is connected to the input terminal 42 and whose source is connected to the ground terminal respectively constitute a CMOS type two-input NAND gate circuit 53.

In the above configuration, when the potentials at the input terminals 41 and 42 simultaneously go to the high level, the NMOS transistors 45 and 46 are turned on, the potential at the output terminal 52 goes to the low level, and any of the input terminals 41 and 42 When the potential of one of the input terminals is low, NMO
The S transistor 43 or the NMOS transistor 44 is turned on, and the potential at the output terminal 52 becomes high level. The two-input NAND gate circuit 54 connected in series to the differentiating circuit 10 is configured to perform the same logical operation as the two-input NAND gate circuit 53.

With the above-described circuit configuration, the effect of improving the driving ability by the positive and negative differential pulses of the differentiating circuit 10 can be similarly obtained.

FIG. 6 shows the configuration of another embodiment of the present invention.
In the figure, a differentiating circuit 10 uses an NMOS transistor 79 as an impedance element, and connects the gate of the NMOS transistor 79 to the power supply terminal 3 and connects the source to the ground terminal to use the resistance of the NMOS transistor 79 during the ON operation. Even if a resistor is used, the same effect can be obtained.

FIG. 7 shows another embodiment of the present invention. In the figure, a differentiating circuit 10 is a PMO as an impedance element.
The same effect as in the case where a resistance element is used can be obtained by using the resistance of the PMOS transistor 89 during the ON operation by connecting the gate to the ground terminal and connecting the drain to the ground terminal using the S transistor 89. .

FIG. 8 shows the configuration of another embodiment of the inverter circuit to which the present invention is applied. This embodiment has a configuration in which a circuit portion corresponding to the CMOS inverter circuit 27 that performs the same logic operation as the CMOS inverter circuit 26 in the inverter circuit shown in FIG. 2 is omitted. In other words, in the embodiment shown in FIG. 2, in order to secure the high speed of signal propagation, the pulse voltage is applied to the main logic circuit (in FIG. 2, the CMOS inverter circuit 26, the NPN bipolar transistor 20, and the NM in FIG. 2).
It comprises an OS transistor 23. ) Is superposed on the output signal. Since this pulse voltage is an accelerating voltage, it must be a positive pulse when the output signal of the main logic circuit is at a high level and a negative pulse when the output signal is at a low level. That is, in the differentiating circuit, a positive pulse is output for a positive change on the input side and a negative pulse is output for a negative change, so that the input signal to the differentiating circuit must be the same logical signal as the output signal of the main logic circuit. Therefore, in the embodiment shown in FIG. 2, a circuit having the same logic as the main logic circuit and a minimum configuration is added. However, in a main logic circuit having a circuit configuration such as a BiNMOS circuit or a BiCMOS circuit,
A portion having the same logic as this output signal exists inside.
This is the base of the NPN bipolar transistor 20 in FIG. Therefore, by adopting a configuration in which an input signal is supplied from the base of the NPN bipolar transistor constituting the output stage in the main logic circuit to the differentiation circuit, a logic circuit connected in series before the differentiation circuit can be omitted.

The present embodiment is characterized in that the logic circuit which performs the same logic operation as the main logic circuit is omitted.

In FIG. 8, reference numeral 100 denotes an input terminal, 101 denotes an output terminal, and 108 denotes a CMOS inverter circuit including a pair of a PMOS transistor 104 and an NMOS transistor 105 whose input terminals are connected to the input terminal 100.
Reference numeral 6 denotes a transistor N connected to the collector of the PMOS transistor 104, the base connected to the drain of the PMOS transistor 104, and the emitter connected to the output terminal 101.
PN bipolar transistor, 107 has NP drain
The gate is CM at the emitter of the N bipolar transistor.
An NMOS transistor 10 having a source connected to the ground terminal and an input terminal of the OS inverter circuit, each of which comprises a capacitor 8 and a resistor 9, has an input terminal connected to the base of an NPN bipolar transistor 106, and an output terminal connected to an output terminal 101. Is a differentiating circuit connected to.

In the above configuration, when the potential at the input terminal 100 changes to low level, the PMOS transistor 104 forming the CMOS inverter circuit 108 is turned on, and the power supply voltage is applied from the power supply terminal 3 to the base of the NPN bipolar transistor 106. You. As a result, N
The PN bipolar transistor 106 is turned on, and the potential at the output terminal 101 becomes high level. At the same time, the output signal of the CMOS inverter circuit 108 is input to the differentiating circuit 10, which generates a positive pulse, and the positive pulse is superimposed on the output signal at the output terminal 101.

On the other hand, when the potential at the input terminal 100 changes to the high level, the NMOS transistor 105 forming the CMOS inverter circuit 108 is turned on,
The base potential of the PN bipolar transistor 106 is set to low level, the NMOS transistor 107 is also turned on, and the potential at the output terminal 101 is set to low level. At the same time, the differentiating circuit 10 receives a signal from the base of the NPN bipolar transistor 106 which changes to a low level, generates a negative pulse, and this negative pulse is superimposed on the output signal output to the output terminal 101, and the negative signal is transmitted. Speed up.

In this embodiment, the input signal of the differentiating circuit 10 is
Since it is configured to receive directly from the output of the CMOS inverter circuit 108 constituting the main logic circuit, the same logic operation as that of the main logic circuit connected in series to the differentiating circuit 10 as an input unit as in the above embodiment is performed. Therefore, it is not necessary to provide a logic circuit to perform the operation, and the circuit can be omitted.

Next, the configuration of another embodiment of the inverter circuit to which the present invention is applied is shown in FIG. In the figure, elements having the same numbers as those in FIG. 8 are elements having the same functions and the same operations as those in FIG. This embodiment has a configuration in which the CMOS inverter circuit 39 is omitted from the embodiment shown in FIG. The difference from the embodiment shown in FIG. 8 in the configuration is that instead of the NMOS transistor 107 that operates the potential at the output terminal of the circuit device to a low level, an N
A PN bipolar transistor 128, an NMOS transistor 127, and a resistor 129 for extracting the base charge of the NPN bipolar transistor 128 are provided, and the collector of the NPN bipolar transistor 128 is connected to the output terminal 121.
, The emitter is connected to the ground terminal, the drain of the NMOS transistor 127 is connected to the output terminal 121, and the source is set to NP.
Base and resistor 12 of N bipolar transistor 128
9, the gate is connected to the input terminal 120, and the other end of the resistor 129 is connected to the ground terminal.

In the above configuration, when the potential at the input terminal 120 goes high, the NMOS transistor 127 turns on and the NPN bipolar transistor 1
The base potential at 28 goes high. As a result, NP
The N bipolar transistor 128 is turned on, and the potential at the output terminal 121 becomes low level.

This embodiment is different from the embodiment shown in FIG. 8 in that the main logic circuit is changed from a BiNMOS circuit to a BiCMOS circuit, and an input signal to the differentiating circuit 10 can be extracted from the main logic circuit portion. And differentiation circuit 1
There is no need to provide a logic circuit that performs the same logic operation as the main logic circuit connected in series as an input unit at 0, and the effect of being able to omit the circuit is the same as in the previous embodiment.

FIG. 10 shows another embodiment of the present invention. FIG.
Reference numeral 0 indicates a configuration of a two-input NAND gate circuit, which is a two-input NAND gate circuit having a BiNMOS configuration. In the figure, 130 and 131 are input terminals,
132 is an output terminal, 133 and 134 are PMOS transistors whose gates are connected to the input terminals 130 and 131, whose sources are connected in common and which is connected to the power supply terminal 3, and whose drain is connected to the base of the NPN bipolar transistor 137. 135 is a PMOS transistor 1
An NMOS transistor 33 has a drain connected to the input terminal 130 and a drain 136
The gate of the transistor 135 is connected to the input terminal 13.
1. NMOS whose source is connected to the ground terminal, respectively
The transistor 137 has an NPN bipolar transistor having a collector connected to the power supply terminal 3, a base connected to the drain of the NMOS transistor 135, an emitter connected to the output terminal 132, and a transistor 138 having a drain connected to the output terminal 132 and a gate connected to the input terminal 130. The NMOS transistor 139 has a drain connected to the NMOS transistor 1
An NMOS transistor 38 has a source connected to the input terminal 131, a gate connected to the input terminal 131, and a source connected to the ground terminal.

The NPN bipolar transistor 137
A differentiating circuit 10 including a capacitor 8 and a resistor 9 is connected between the output terminal 132 and the base.

The level of the output signal at the output terminal 132 of the main logic circuit constituting the two-input NAND gate circuit is
It goes low only when both the levels of the input signals at the input terminals 130 and 131 go high, and goes high when any other input signal is input. The point where the same logic signal as the output signal of the main logic circuit is obtained is the base point of the NPN bipolar transistor 137, and the input signal to the differentiating circuit 10 can be extracted from the inside of the main logic circuit as in the previous embodiment. , Connected in series as an input to the differentiating circuit 10,
There is no need to provide a logic circuit that performs the same logical operation as the main logic circuit, and the effect that the circuit can be omitted is the same as in the above embodiment.

FIG. 11 shows another embodiment of the present invention. FIG.
1 shows the configuration of a two-input NAND gate circuit, which is a two-input NAND gate circuit having a BiCMOS configuration. In the figure, 140 and 141 are input terminals, 142 is an output terminal, 143 and 144 are sources commonly connected and connected to the power supply terminal 3, gates are input terminals 140 and 141, and drains are bases of NPN bipolar transistor 147. The connected PMOS transistor 145 has a drain connected to the drain of the PMOS transistor 143 and a gate connected to the input terminal 140.
The OS transistor 146 has a drain connected to the source of the NMOS transistor 145, a gate connected to the input terminal 141,
The source is an NMOS transistor connected to the ground terminal.

Reference numeral 147 denotes an NPN bipolar transistor having a collector connected to the power supply terminal 3, a base connected to the drain of the NMOS transistor 145, and an emitter connected to the output terminal 142, respectively.
42, an NPN bipolar transistor having a base connected to the source of the NMOS transistor 150 and one end of the resistor 151, and an emitter connected to the ground terminal, respectively.
A resistor 151 for extracting a base charge is connected between the base and the emitter of the PN bipolar transistor 148.

Further, NPN bipolar transistor 147
And the resistor 9 between the output terminal 142 and the base of the
Is connected.

In the above configuration, the potential at the output terminal 142 of the main logic circuit forming the two-input NAND gate circuit goes low only when both the potentials at the input terminals 140 and 141 are high, and the other signals are at low level. When input, it becomes high level. Where the same logic signal as the output signal of the main logic circuit is obtained is NP
This is the base point of the N bipolar transistor 147, and the input signal to the differentiating circuit 10 can be extracted from the main logic circuit portion, which is no different from the above embodiment.
There is no need to provide a logic circuit that performs the same logic operation as the main logic circuit, which is connected in series as an input to 0, and the effect of omitting the circuit is the same as in the above embodiment.

FIG. 12 shows another embodiment of the present invention. FIG.
2 shows the configuration of a non-inverter gate.
In the figure, reference numeral 160 denotes an input terminal, and 161 denotes an output terminal. A pair of PMOS transistor 163 and NMOS transistor 164 are connected in series between the power supply terminal 3 and the ground terminal.
63 and the NMOS transistor 164, the first CM
The OS inverter circuit 165 is configured.

The first CMOS inverter circuit 165
Of the first CMOS inverter circuit 165
The input terminal of the second CMOS inverter circuit 168 which performs the same logical operation as that of the first embodiment is connected. This second CMOS
The inverter circuit 168 includes a PMOS transistor 166 and an NMOS transistor 167, and the output terminal is connected to the output terminal 161.

Further, between the input terminal 160 and the output terminal 161, a differentiating circuit 10 comprising a capacitor 8 and a resistor 9 is connected.

In the above configuration, the potential at the output terminal 161 of the main logic circuit as the buffer gate is
When the potential at 0 is at a high level, the level is high, and when the potential at the input terminal 160 is at a low level, the level is low. Therefore, the input side of the differentiating circuit 10 can be directly connected to the input terminal 160, and there is no need to provide a logic circuit that performs the same logical operation as the main logic circuit, and the effect that the circuit can be omitted is the same as in the above embodiment. .

Next, another embodiment of the present invention is shown in FIG.
FIG. 13 shows a configuration of a non-inverter gate, which is a non-inverter gate having a CMOS circuit configuration.

In the figure, 170 is an input terminal, 171 is an output terminal, 175 is an NMOS transistor 173 and P
This is a CMOS circuit composed of MOS transistors 174. A differentiating circuit 10 including a capacitor 8 and a resistor 9 is connected between the input terminal 170 and the output terminal 171.
The present embodiment is a buffer gate having a CMOS circuit configuration.

In the above configuration, the output terminal 1 of the main logic circuit
The potential at 71 is high when the potential at the input terminal 170 is high, and is low when the potential at the input terminal 170 is low. Therefore,
The input side of the differentiating circuit 10 can be directly connected to the input terminal 170, and there is no need to provide a logic circuit that performs the same logic operation as the main logic circuit, and the effect that the circuit can be omitted is the same as in the above embodiment.

FIG. 14 shows another embodiment of the present invention. FIG.
4 shows a configuration of a non-inverter gate,
This is a BiCMOS non-inverter gate. In the figure, 180 is an input terminal, 181 is an output terminal, 183 is a PNP transistor whose emitter is connected to the power supply terminal 3, whose collector is connected to the output terminal 181, 184 is whose collector is connected to the output terminal 181, and whose emitter is connected to the ground terminal. An NPN transistor 191 is a base charge extracting resistor connected between the base and the emitter of the NPN transistor 94, and 185 is a power source terminal 3
And a PMOS having a gate connected to the input terminal 180 and a drain connected to the base of the PNP transistor 183, respectively.
A transistor 186 is an NMOS transistor having a drain connected to the drain of the PMOS transistor 185 and a gate connected to the input terminal 180.
The OS transistor 186 is an NMOS transistor having a source connected to the gate thereof, an output side of the inverter 190, and a source connected to the ground terminal.

Reference numeral 188 denotes a PMOS transistor having a source connected to the power supply terminal 3 and a gate connected to the output side of the inverter 190.
A PMOS transistor has a drain connected to the input terminal 180, a gate connected to the input terminal 180, and a drain connected to the base of the NPN transistor 184. Reference numeral 190 denotes an inverter.

Further, between the input terminal 180 and the output terminal 181, a differentiating circuit 10 comprising a capacitor 8 and a resistor 9 is connected.

In the above configuration, when the potential at the input terminal 180 is at a high level, the NMOS transistor 186
Is turned on, and the drain potential of the NMOS transistor 186 becomes low level. As a result, the PNP transistor 183 turns on, and the potential at the output terminal 181 becomes high level. At the same time, the high-level signal is inverted by the inverter 190 and output to the gate of the NMOS transistor 187. As a result, the operating point of the transistor 183 moves from the saturation region to the active region,
The NP transistor 183 is prevented from becoming saturated.

When the potential at the input terminal 180 is at a low level, the PMOS transistor 189 turns on, and the power supply voltage is supplied from the power supply terminal 3 to the base of the NPN transistor 184. As a result, the NPN transistor 184 turns on, and the potential at the output terminal 181 becomes low level. At the same time, the low-level signal is inverted by the inverter 190, the inverted high-level signal is output to the gate of the PMOS transistor 188, and the PMOS transistor 188 is turned off.
The NPN transistor 184 is prevented from becoming saturated.

In this embodiment, the PNP transistor 183 and the NPN transistor 184 on the output side are transiently saturated to operate at full amplitude to pursue low voltage operation.

As described above, the potential at the output terminal 181 of the main logic circuit, which is a buffer gate, goes high when the potential at the input terminal 180 is high, and goes low when the potential at the input terminal 180 is low. Therefore, the input side of the differentiating circuit 10 can be directly connected to the input terminal 180, and there is no need to provide a logic circuit that performs the same logic operation as the main logic circuit, and the effect that the circuit can be omitted is the same as in the above embodiment. .

Next, an application example of the present invention will be described with reference to FIGS. FIG. 15 shows a general configuration of a data processing device.
, A central processing unit (hereinafter, referred to as a CPU) 201, a memory 202 for storing data input to the CPU 201 or data output from the CPU, a memory controller 203, and an I / O processor 204. ing. In this data processing device, for example, taking the CPU 201 as an example, high-speed responsiveness of each element of the integrated circuit device constituting the CPU 201 is required in order to perform calculations at high speed.

On the other hand, if the CPU 201 is divided into a plurality of LSI chips, the signal propagation delay time between the LSIs increases, and the system performance does not increase. Further L
When the size of the SI chip increases, the power consumption increases, so that low power consumption is also required. Accordingly, FIGS.
When the semiconductor integrated circuit device (logic circuit) according to the present invention described with reference to FIGS. 8 to 14 is applied to a data processing device such as a processor, the semiconductor integrated circuit device (logic circuit) can be constituted by a logic circuit capable of low power supply voltage operation and high-speed operation. A high-performance system can be constructed.

FIG. 16 shows a specific configuration of the CPU 201 in FIG. The CPU 201 is a memory control unit 2
10, a read only memory (ROM) 211, a control logic unit 212, and a calculation unit 213. Arithmetic unit 213
Is composed of an adder 214 and a register file 215.

The control logic unit 212 controls the arithmetic unit 213 and the memory control unit 210 for controlling the external memory according to the command read from the ROM 211.

Next, FIG. 17 shows the configuration of the control logic unit 212 in FIG. As shown in FIG.
0, the control logic unit 212 that controls the arithmetic unit 213 is configured by a logic gate circuit such as an inverter circuit and a two-input NAND gate circuit. A low power supply voltage operation is possible by configuring a path with a large load, which is a heavy load portion, and a long wiring line of the logic gate by a BiCMOS gate circuit and a lightly loaded portion by a CMOS circuit. In addition, a control logic unit that achieves high integration and low power consumption at high speed, and eventually a CPU can be realized.

[0072]

According to the present invention as described above,
Since the differential circuit to which the same logical signal as the output signal of the CMOS logic circuit is input is connected in parallel to the CMOS logic circuit, the gate delay time with respect to the output load is ensured while ensuring low power supply voltage. , A semiconductor integrated circuit device in which the dependence of the semiconductor integrated circuit is reduced can be realized. Further, according to the present invention, a differentiating circuit is added to the logic circuit in parallel, and the input of the differentiating circuit is drawn out from the main logic circuit, so that the load dependence of the signal propagation delay time can be reduced. As a result, high speed operation can be achieved, a logic circuit which performs the same logic operation as the main logic circuit can be omitted, the circuit scale can be reduced, and high integration and low power consumption can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of an inverter circuit to which the present invention is applied.

FIG. 2 is a circuit diagram showing a configuration of another embodiment of the inverter circuit to which the present invention is applied.

FIG. 3 is a circuit diagram showing a configuration of another embodiment of the inverter circuit to which the present invention is applied.

FIG. 4 is a circuit diagram showing a configuration of a two-input NAND gate circuit to which the present invention is applied;

FIG. 5 is a circuit diagram showing a configuration of a conventional inverter circuit.

FIG. 6 is a circuit diagram showing the configuration of another embodiment of the differentiating circuit constituting the semiconductor integrated circuit device according to the present invention.

FIG. 7 is a circuit diagram showing the configuration of still another embodiment of the differentiating circuit constituting the semiconductor integrated circuit device according to the present invention.

FIG. 8 is a circuit diagram showing a configuration of another embodiment of the inverter circuit to which the present invention is applied.

FIG. 9 is a circuit diagram showing a configuration of still another embodiment of the inverter circuit to which the present invention is applied.

FIG. 10 is a circuit diagram showing a configuration of another embodiment of a two-input NAND gate circuit to which the present invention is applied.

FIG. 11 is a circuit diagram showing a configuration of still another embodiment of a two-input NAND gate circuit to which the present invention is applied.

FIG. 12 is a circuit diagram showing a configuration of one embodiment of a non-inverter circuit to which the present invention is applied.

FIG. 13 is a circuit diagram showing a configuration of another embodiment of the non-inverter circuit to which the present invention is applied.

FIG. 14 is a circuit diagram showing a configuration of still another embodiment of the non-inverter circuit to which the present invention is applied.

FIG. 15 is a block diagram showing a configuration of a data processing device to which the semiconductor integrated circuit device according to the present invention is applied.

16 is a block diagram illustrating a configuration of a CPU in FIG.

FIG. 17 is an explanatory diagram illustrating a configuration example of a control logic unit in FIG. 16;

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 output terminal 3 power supply terminal 4 PMOS transistor 5 NMOS transistor 6 PMOS transistor 7 NMOS transistor 10 differentiating circuit 11 first CMOS inverter circuit 12 second CMOS inverter circuit 200 bus line 201 CPU 202 memory 203 memory controller 204 I / O processor 210 Memory control unit 211 ROM 212 Control logic unit 213 Operation unit

Continued on the front page (72) Inventor Hiroshi Kobayashi 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Laboratory (72) Inventor Masataka Minami 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. ) Surveyed field (Int.Cl. ⁷ , DB name) H03K 19/0948

Claims (11)

(57) [Claims] 1. A first CMOS logic gate having an input terminal connected to an input terminal of the first CMOS logic gate and performing the same logic operation as the first CMOS logic gate. A semiconductor having a gate and an input terminal connected to an output terminal of the second CMOS logic gate, and an output terminal connected to an output terminal of the first CMOS logic gate; Integrated circuit device. 2. A pair of PMOS transistor and NMO
A first CMOS inverter circuit including an S transistor; and a second CMOS inverter circuit having an input terminal connected to an input terminal of the first CMOS inverter circuit and performing the same logical operation as the first CMOS inverter circuit. And a differentiating circuit having an input terminal connected to an output terminal of the second CMOS inverter circuit and an output terminal connected to an output terminal of the first CMOS inverter circuit. Circuit device. 3. A first CMOS inverter circuit comprising a pair of a PMOS transistor and an NMOS transistor whose input terminals are connected to an input terminal of a circuit device, and a source of the PMOS transistor constituting the first CMOS inverter circuit. An NPN bipolar transistor having a collector connected to the drain of the PMOS transistor and a base connected to the output terminal of the circuit device, a train connected to the emitter of the NPN bipolar transistor, and a gate connected to the first CMOS inverter circuit. NMOs whose sources are connected to ground terminals at the input end, respectively
An S transistor, a second CMOS inverter circuit having an input terminal connected to an input terminal of the first CMOS inverter circuit and performing the same logical operation as the first CMOS inverter circuit, and the second CMOS inverter circuit And a differentiating circuit having an input terminal connected to the output terminal and an output terminal connected to the output terminal. 4. A first CMOS inverter circuit comprising a pair of a PMOS transistor and an NMOS transistor, the input terminals of which are connected to input terminals of a circuit device, and a source of a PMOS transistor constituting the first CMOS inverter circuit. A first NPN bipolar transistor having a collector connected to the drain of the PMOS transistor and a base connected to the output terminal of the circuit device, and a collector connected to the emitter of the first NPN transistor and an emitter connected to the ground terminal. A second NPN transistor to be connected; a drain connected to the emitter of the first NPN bipolar transistor; a gate connected to the input terminal of the first CMOS inverter circuit; and a source connected to the base of the second NPN transistor. NMOS transistor An element for extracting a base charge of the second NPN transistor connected between the base and the emitter of the second NPN transistor; and an input terminal connected to an input terminal of the first CMOS inverter circuit. A second CMOS inverter circuit performing the same logical operation as the CMOS inverter circuit of the first embodiment, and a differentiator circuit having an input terminal connected to an output terminal of the second CMOS inverter circuit and an output terminal connected to the output terminal. A semiconductor integrated circuit device comprising: 5. A first CMOS inverter circuit comprising a pair of a PMOS transistor and an NMOS transistor whose input terminal is connected to an input terminal of a circuit device, and a source of the PMOS transistor constituting the first CMOS inverter circuit. A first NPN bipolar transistor having a collector connected to a drain of the PMOS transistor and an emitter connected to an output terminal of the circuit device; a drain connected to an emitter of the NPN bipolar transistor, and a gate connected to the first CMOS. A first NMOS transistor having a source connected to the ground terminal and an input terminal connected to the input terminal of the inverter circuit, and an input terminal connected to the input terminal of the first CMOS inverter circuit, the same as the first CMOS inverter circuit; CMOS in which the logical operation of A second NPN bipolar transistor having a collector connected to a source of a PMOS transistor constituting the second CMOS inverter circuit and a base connected to a drain of the PMOS transistor; and a drain connected to the second NPN transistor. A second NMOS transistor having a gate connected to the emitter of the bipolar transistor, an input terminal of the second CMOS inverter circuit, and a source connected to the ground terminal; and an input terminal connected to the emitter of the second NPN bipolar transistor. And a differentiating circuit having an output terminal connected to the output terminal. 6. A CMOS inverter circuit comprising a pair of a PMOS transistor and an NMOS transistor whose input terminal is connected to an input terminal of a circuit device, a collector of a PMOS transistor constituting the CMOS inverter circuit being connected to the PMOS transistor, An NPN bipolar transistor having a base connected to the drain of the NPN bipolar transistor and an emitter connected to the output terminal of the circuit device; a drain connected to the emitter of the NPN bipolar transistor; a gate connected to the input terminal of the CMOS inverter circuit;
An NMOS transistor having a source connected to the ground terminal, and an input terminal connected to the base of the NPN transistor;
A semiconductor integrated circuit device having an output terminal connected to the output terminal. 7. A CMOS inverter circuit comprising a pair of a PMOS transistor and an NMOS transistor having an input terminal connected to an input terminal of a circuit device, a collector of a PMOS transistor constituting the CMOS inverter circuit, and a collector of the PMOS transistor. A first NPN bipolar transistor having a base connected to the drain thereof and an emitter connected to the output terminal of the circuit device, and a second NPN transistor having a collector connected to the emitter of the first NPN bipolar transistor and an emitter connected to the ground terminal. NP
An NMOS transistor having a drain connected to the emitter of the first NPN bipolar transistor, a gate connected to the input terminal of the CMOS inverter circuit, and a source connected to the base of the second NPN transistor; A base charge extracting element of the second NPN transistor connected between the base and the emitter of the second NPN transistor; an input terminal connected to the base of the first NPN bipolar transistor; A differential circuit connected to an output terminal. 8. A pair of a PMOS transistor and an NMO
A first CMOS inverter circuit including an S transistor; and a second CMOS inverter circuit having an input terminal connected to an output terminal of the first CMOS inverter circuit and performing the same logical operation as the first CMOS inverter circuit. And a differentiating circuit having an input terminal connected to an input terminal of the first CMOS inverter circuit and an output terminal connected to an output terminal of the second CMOS inverter circuit. Circuit device. 9. The semiconductor integrated circuit device according to claim 1, wherein said differentiating circuit comprises a reactance element and an impedance element. 10. The semiconductor integrated circuit device according to claim 9, wherein said impedance element is a resistor. 11. The semiconductor integrated circuit device according to claim 9, wherein said impedance element is a MOS transistor.