US20040105201A1

US20040105201A1 - Scheme for eliminating the channel unexpected turn-on during ESD zapping

Info

Publication number: US20040105201A1
Application number: US10/307,646
Authority: US
Inventors: Yi-Hsun Wu; Jian-Hsing Lee; Shui-Hung Chen
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2002-12-02
Filing date: 2002-12-02
Publication date: 2004-06-03
Also published as: TW200410394A; US7508639B2; TWI261908B; US20060114629A1

Abstract

This invention provides a circuit for eliminating unexpected transistor channel turn-on caused by electrostatic discharge, ESD, zapping. It provides circuits which detect ESD over-voltage conditions and which pull down the voltage to the sensitive logic devices in the input/output pre-driver circuitry during ESD zapping. There is an Input/Output control circuit which interfaces with the sense circuit, feedback circuit and with the input/output pad of the semiconductor chip to be protected from ESD damage. The purpose of this I/O circuit is to use the ESD sense circuit and an internal feedback node to pull down the voltage on the gates of the MOSFET devices most vulnerable to unexpected channel turn on during the during of the ESD over-voltage condition.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a circuit for eliminating unexpected transistor channel turn-on caused by electrostatic discharge, ESD, zapping

More particularly this invention relates to providing a circuit which detects ESD events and pulls down the output voltage of the pre-driver to zero volts when an ESD pulse enters a semiconductor integrated circuit.

2. Description of Related Art

FIG. 1 shows a block diagram of the prior art. A semiconductor input/output pad is shown 175. Node 155 is the node common to the I/O pad. This is the node which can pick up over-voltage which can damage FET devices. NMOS FET 142 is the most vulnerable device. The drain of NMOS FET 142 can be sitting at Vcc voltage in a normal steady state when the ESD event occurs. The ESD event of a voltage spike on the I/O pad would add an additional momentary voltage spike on top of the Vcc voltage already present at the drain of NMOS FET 142 in FIG. 1. In the prior art, devices such as 142 required special ESD implant levels to protect them from unexpected channel turn-on.

U.S. Pat. No. 5,847,575 (Galbi, et al.) “Method and Apparatus for Performing Switched Power Supply Drive in CMOS Pad Drivers” describes a driver circuit for limiting electrical noise on a quiescent signal. The signal is driven by the transition power supply network until the electrical signal reaches its quiescent voltage level.

U.S. Pat. No. 5,444,402 (McMahon, et al.) “Variable Strength Clock Signal Driver and Method of Manufacturing the Same” shows a clock driver circuit that accommodates either full or reduced drive strength of a generated clock signal. The clock driver circuit includes a package bonding option to select the desired strength of drive.

U.S. Pat. No. 5,751,173 (McMahon, et al.) “Variable Strength Clock Signal Driver and Method of Manufacturing the Same” is a continuation of the above U.S. Pat. No. 5,444,402.

BRIEF SUMMARY OF THE INVENTION

It is the objective of this invention to provide a circuit for eliminating the unexpected channel turn-on during electrostatic discharge, ESD, zapping.

It is further an objective of this invention to provide a circuit which pulls down the output voltage of an input/output pre-driver to zero volts during ESD zapping.

The objectives of this invention are achieved by a circuit which is made up of the following sections.

There is an electrostatic discharge ESD sensing circuit, which interfaces with the input/output, I/O circuitry, which is located at the chip I/O pad. The purpose of this ESD sensing circuit is to detect an ESD over voltage condition and to report it to the input/output control circuit of this invention. As can be seen in FIG. 3, if node E 1, the over-voltage sense node is high or floating, the output of the ESD sense circuit 367 goes low. This ESD sense circuit output 367 is also know as the internal feedback node. When this internal feedback node 367 goes low, the voltage on the gates of NMOS FETs 391 and 342 will be low. This low voltage 367 will insure that NMOS FET devices 391 and 342 will stay off during ESD zapping. Devices 391 and 342 will stay off even if the additional ESD noise effect of a negative pulse on Vss or ground 335 occurs.

There is a feedback circuit, which also interfaces with the input/output, I/O circuitry, which is located at the chip I/O pad. The purpose of this feedback circuit is to pull down the voltage at the gates of logic devices in the I/O circuitrry during ESD events to prevent unexpected channel turn-on. The FET gate at most risk is FET 342 in the I/O circuit in FIG. 3.

There is an Input/Output control circuit which interfaces with the sense circuit, feedback circuit and with the input/output pad of the semiconductor chip to be protected from ESD damage. The purpose of this I/O circuit is to use the ESD sense circuit and the feedback circuit to pull down the pre-driver

internal voltage

355 to zero volts during the ESD zapping time period. Internal pre-driver node 355 will remain low as long as devices 391 and 342 are held off by the low voltage on the internal feedback node 367. Also, there is a pull-down NMOS FET 331 which keeps the internal node 355 low when devices 391 and 342 are off in FIG. 3.

This invention provides protection when ESD voltage pulses occur on the

Vss pin

335. If Vss encounters a negative ESD pulse, the channel of input/output driver logic devices, 391, 342 could either burnout or turn-on. In addition, the I/O circuit controls the normal switching of the I/O pad's function from an input to an output 347 based on the state of the Output Enable, OE, signal 348 in FIG. 3.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a prior art conventional Input/Output circuit with a pre-driver. [0016]
FIG. 2 shows a circuit diagram which illustrates one embodiment of this invention. [0017]
FIG. 3 shows a circuit diagram of the main embodiment of this invention. [0018]

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 shows a conventional input/output circuit with a modified pre-driver. The diode string formed by [0019] devices 232 and 233 are used to detect an ESD over-voltage condition. If there is an ESD event on the chip, signal E1 231 will be high. This will cause node E2, the output of the 3-input NOR to be low which will cause NMOS FET 290 to be on and NMOS FET 286 to be off. This will result in node B, 271 going low. When node B, 271 goes low, node A will go high.
Therefore, in FIG. 2, during a detected ESD event, the internal feedback node A will guarantee that NMOS FETs [0020] 291 and 242 will remain off. This will insure that the channels of these sensitive NMOS FETs will not turn on during an ESD event.
FIG. 3 shows the main embodiment of this invention. It shows a circuit for eliminating the channel unexpected turn-ON during electrostatic discharge, ESD, zapping. The circuit is made up of an electrostatic discharge ESD sensing circuit, which interfaces with the input/output, I/O circuitry, which is located at the chip I/[0021] O pad 375, a feedback circuit, which interfaces with the ESD sensing circuit, and an input/output, I/O, circuit, which interfaces to an I/O pad and interfaces to an ESD sensing circuit. This sensing circuit detects a high voltage caused by ESD at an internal node E1 346. The sensing node E1 detects a high voltage ESD event by being charged up via ‘n’ serially connected NMOS devices 381, 382, 383. FIG. 3 shows ‘n’ serial connected to NMOS devices are connected between the power supply node Vcc and the internal node E1 346. The first NMOS FET SC_N1 381 of the ‘n’ serially connected NMOS FETS has its drain and gate connected to Vcc, the power supply voltage, and has its source are connected to a gate and drain of a next serially connected NMOS FET SC_N2 382. The second serially connected NMOS FET SC_N2 382 has its drain and gate connected to the source of the first serially connected NMOS FET and whose source is connected to the drain and gate of the nth serially connected NMOS FET. The nth serially connected NMOS FET has its drain and gate connected to the source of a last serially connected NMOS FET SC_N3 383 and whose source is connected to a node 353. The last serially connected NMOS FET SC_N3 383 has its drain and gate connected to the source of the previous serially connected NMOS FET SC_N2 382, and whose source is connected to internal node E1 346. The sensing circuit contains a PMOS FET SC_P1 386 whose source is connected to Vcc, whose gate is connected to ground and whose drain is connected to a source of a second PMOS FET SC_P2 387. Also, the sensing circuit contains a second PMOS FET SC_P2 387 whose source is connected to the drain of the first PMOS FET SC_P1 386, whose gate is connected to the node E1 346 and whose drain is connected to the node A 367. The sensing circuit contains a resistor, R 384, which is connected between the gate of the NMOS FET SC_N4 392 and the sources of NMOS FETs SC_N4 392 and SC_N5 393. Also, the sensing circuit contains NMOS FETS SC_N4 392 and SC_N5 393 whose sources are connected in common and to one side of the resistor R 384, whose drains are connected in common to a node A 367, the gate of the NMOS FET SC_N4 392 is connected to the node E1 346. The gate of the NMOS FET SC_N5 393 is connected to the gate of PMOS FET SC_P3 387. The sensing circuit contains a PMOS FET SC_P3 387 whose source is connected to Vcc, power supply voltage, whose drain is connected to a source of PMOS FET SC_P4 386 and whose gate is connected to the gate of the NMOS FET SC_N6 393.
FIG. 3 shows a feedback circuit pulls down the top gate voltage to zero volts during an ESD zapping event. The feedback circuit contains a [0022] PMOS FET LS_P1 395 whose source is connected to Vcc, whose drain is connected to the drain of an NMOS FET LS_N1 394, and whose gate is connected to the drain of a PMOS FET LS_P2 396. The feedback circuit contains a PMOS FET LS_P2 396 whose source is connected to the N-side of a PN diode 363, whose drain is connected to the gate of the PMOS FET LS_P1 395, and whose gate is connected to the drain of the PMOS FET LS_P1 395. The feedback shifting circuit contains an NMOS FET LS_N1 394 whose source is connected to ground; whose drain is connected to the drain of the PMOS FET LS_P1 395, and whose gate is connected to an output of a NOR gate 361. FIG. 3 shows NMOS FET LS_N2 397 whose source is connected to the P side of PN diode 2, 352 and to the N-side of PN diode 3, 351 whose drain is connected to the drain of the PMOS FET LS_P2 396 and whose gate is connected to the drain of NMOS FET LS_N3 398. The feedback circuit contains a NMOS FET LS_N3 398 whose source is connected to ground, whose drain is connected to the drain of PMOS FET LS_P3 399 and whose gate is connected to the NOR 361 output node. Also, the feedback circuit contains the PMOS FET LS_P3 399 whose drain is connected to the drain of the NMOS FET LS_N3 398, whose source is connected to a variable Vcc pull-down node and whose gate is connected to the output of the NOR 361. The feedback circuit contains a 2-input NOR 361 whose first input is an output signal 347 from a chip's logic core and whose second input is an output enable 348.
The I/O circuit is used to discharge an ESD voltage to ground and is used to drive outputs off the chip. The I/O circuit contains a [0023] PMOS FET IO_P1 310 whose source and gate are connected to Vcc 325 and whose drain is connected to an I/O pad 375. The I/O circuit contains an NMOS FET IO_N1 350 whose drain is connected to the drain of PMOS FET IO-P1 310, and whose gate is connected to the node A1 367, and whose source is connected to the drain of NMOS FET IO_N2 360. This I/O circuit contains an NMOS FET IO_N2 360 whose drain is connected to the source of the NMOS FET IO_N1 350, whose gate and source are connected to ground. The I/O circuit contains a PMOS FET IO_P2 320 whose source and gate are connected to Vcc, and whose drain is connected to the I/O pad 375. In addition, the I/O circuit contains an NMOS FET IO_N3 370 whose drain is connected to the drain of the PMOS FET IO_P2 320 device, whose source is connected to an NMOS FET IO_N4 380, and whose gate is connected to the internal node A1 367. Also, the IO circuit contains an NMOS FET IO_N4 380 whose drain is connected to the source of the NMOS FET IO_N3 370, and whose gate and source are connected to ground. The IO circuit contains a PMOS FET IO_P3 330 whose source is connected to Vcc, whose gate is connected to a gate of PMOS FET IO_P4 340, and whose drain is connected to the IO pad 375. The IO circuit contains an NMOS FET IO_N5 390 whose drain is connected to the drain of the PMOS FET IO_P4 340, source is connected to a drain of an NMOS FET IO_N6 391, and whose gate is connected to internal node A1 367. Also, the IO circuit contains an NMOS FET IO_N6 391 whose drain is connected to the sources of the NMOS FET IO_N5 390, whose gate is connected to the internal node A2 345 and whose source is connected to ground. In addition, the IO circuit contains a PMOS FET IO_P4 340 whose source is connected to Vcc, whose gate is connected to the gate of the PMOS FET IO_P3 330, and whose drain is connected to the drain of NMOS FET IO_N7 341. This IO circuit contains an NMOS FET IO_N7 341 whose drain is connected to the drain of the PMOS FET IO_P4 340, whose gate is connected to internal node A1 367 and whose source is connected to a drain of an NMOS FET IO_N8 342. The IO circuit contains an NMOS FET IO_N8 342 whose drain is connected to the source of the NMOS FET IO_N7 341, whose gate is connected to the internal node A2 345 and whose source is connected to ground.
The advantage of this invention is that the circuit prevents the FET device channels from unexpectedly turning on during electrostatic discharge events, such as during the time that there is an ESD over-voltage condition. The sense circuit detects the ESD condition and a feedback internal node turns off the gates of the MOSFET devices which are most vulnerable to unexpected channel turn on during the time period of the ESD event. This circuit avoids having to build all semiconductor chips with an expensive ESD implant layer which requires time and cost. [0024]
While this invention has been particularly shown and described with Reference to the preferred embodiments thereof, it will be understood by those Skilled in the art that various changes in form and details may be made without Departing from the spirit and scope of this invention.[0025]

Claims

What is claimed is:

1. A circuit for eliminating the channel unexpected turn-ON during electrostatic discharge, ESD, zapping, comprising:

an electrostatic discharge ESD sensing circuit, which interfaces with input/output, I/O circuitry, which is located at a chip I/O pad,

a feedback circuit, which interfaces with said ESD sensing circuit with an input/output, I/O, circuit, and

said input/output, I/O, circuit, which interfaces to an I/O pad and interfaces to said ESD sensing circuit.

2. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 1 wherein said ESD sensing circuit detects a high voltage caused by ESD at an internal sensing node.

3. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 1 wherein said sensing node detects a high voltage ESD event by being charged up via ‘n’ serially connected NMOS devices.

4. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 3 wherein said ‘n’ serial connected to NMOS devices are connected between the power supply node and said internal sensing node.

5. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 3 wherein said ‘n’ serially connected NMOS FETS have their drains and gates connected to the power supply voltage, and have their sources are connected to a gate and drain of a next serially connected NMOS FET.

6. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 5 wherein said second serially connected NMOS FET has its drain and gate connected to said source of said first serially connected NMOS FET and whose source is connected to the drain and gate of said nth serially connected NMOS FET.

7. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 3 wherein said nth serially connected NMOS FET has its drain and gate connected to said source of a last serially connected NMOS FET and whose source is connected to a second internal feedback node.

8. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 3 wherein said last serially connected NMOS FET has its drain and gate connected to said source of said previous serially connected NMOS FET, and whose source.

9. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 2 wherein said sensing circuit contains a discharge NMOS FET whose gate is connected to the source of said last serially connected NMOS FET device, whose drain is connected to an internal feedback node and whose source is connected to ground.

10. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 2 wherein said sensing circuit contains a second discharge NMOS FET whose gate is connected to the gate of a first PMOS FET source of said last serially connected NMOS FET device, whose drain is connected to an internal feedback node and whose source is connected to ground.

11. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 2 wherein said sensing circuit contains said first PMOS FET whose source is connected to said power supply, whose gate is connected to a gate of said second discharge NMOS FET, and whose drain is connected to a source of a second PMOS FET device.

12. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 2 wherein said sensing circuit contains said second PMOS FET whose source is connected to said drain of said first PMOS FET, whose gate is connected to said sensing node and whose drain is connected to said internal feedback node.

13. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 2 wherein said sensing circuit contains a resistor which is connected between the gate of said first discharge NMOS FET and ground.

14. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 2 wherein said sensing circuit contains said third PMOS FET whose source is connected to said power supply voltage, whose drain is connected to a drain of a third discharge NMOS FET and whose gate is connected to a drain of a fourth PMOS FET.

15. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 2 wherein said sensing circuit contains a said fourth PMOS FET whose drain is connected to a gate of said third PMOS FET, whose source is connected to said power supply voltage, and whose gate is connected to said drain of said third PMOS FET.

16. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 1 wherein said feedback circuit pulls down gate voltages of Input/output predriver devices to zero volts during an ESD zapping event.

17. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 16 where said feedback circuit contains a fourth PMOS FET whose source is connected to said power supply, whose drain is connected to the drain of a fourth NMOS FET, and whose gate is connected to the gate of a fifth discharge NMOS FET.

18. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 16 wherein said feedback circuit contains said fourth NMOS FET whose source is connected to the P side of a first PN diode and to the N-side of a second PN diode whose drain is connected to the drain of said fourth PMOS FET and whose gate is connected to the drain of said fifth discharge NMOS FET.

19. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 16 wherein said feedback circuit contains said fifth NMOS FET whose source is connected to ground; whose drain is connected to the drain of said fifth PMOS FET, and whose gate is connected to an output of a NOR gate.

20. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 16 wherein said feedback circuit contains a 2-input NOR whose first input is an output signal from a chip's logic core and whose second input is an output enable.

21. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 1 wherein said I/O circuit is used to discharge an ESD voltage to ground and is used to drive outputs off the chip.

22. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 21 wherein said I/O circuit contains a first IO PMOS FET whose source and gate are connected to Vcc and whose drain is connected to an I/O pad.

23. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 21 wherein said I/O circuit contains a first IO NMOS FET whose drain is connected to said drain of said first IO PMOS FET, whose gate and source are connected to ground.

24. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 21 wherein said I/O circuit contains a second IO PMOS FET whose source and gate are connected to said power supply voltage, and whose drain is connected to said I/O pad.

25. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 21 wherein said IO circuit contains said second IO NMOS FET whose drain is connected to said drain of said second IO PMOS FET, and whose gate and source are connected to ground.

26. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 21 wherein said IO circuit contains said third IO PMOS FET whose source is connected to said power supply voltage, whose gate is connected to a gate of a fourth IO PMOS FET, and whose drain is connected to said IO pad.

27. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 21 wherein said IO circuit contains a fourth IO NMOS FET whose drain is connected to said IO pad, source is connected to ground, and whose gate is connected to said internal feedback node.

28. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 21 wherein said IO circuit contains a third IO NMOS FET whose drain is connected to said drain of said third IO PMOS FET, whose gate is connected to said internal feedback node and whose source is connected to ground.

29. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 21 wherein said IO circuit contains said fourth PMOS FET whose source is connected to said power supply voltage, whose gate is connected to said gate of said third IO PMOS FET, and whose drain is connected to the drain of said fourth IO NMOS FET.

30. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 21 wherein said IO circuit contains a fifth IO NMOS FET whose drain is connected to one side of an IO resistor and whose gate and source are connected to ground.

31. The circuit for eliminating the channel unexpected turn-ON during ESD zapping of claim 21 wherein said IO circuit contains said IO resistor whose one side is connected to said drain of said fifth IO NMOS FET and whose other side is connected to said drain of said fourth IO NMOS FET.

32. A method for eliminating the channel unexpected turn-ON during electrostatic discharge, ESD, zapping, comprising the steps of:

providing an electrostatic discharge ESD sensing circuit, which interfaces with input/output, I/O circuitry, which is located at a chip I/O pad,

providing a feedback circuit, which interfaces with said ESD sensing circuit and an input/output, I/O, circuit, and

providing said input/output, I/O, circuit, which interfaces to an I/O pad and interfaces to said ESD sensing circuit.

33. The method for eliminating the channel unexpected turn-ON during ESD zapping of claim 32 wherein said ESD sensing circuit detects a high voltage caused by ESD at an internal sensing node.

34. The method for eliminating the channel unexpected turn-ON during ESD zapping of claim 32 wherein said sensing node detects a high voltage ESD event by being charged up via ‘n’ serially connected NMOS devices.

35. The method for eliminating the channel unexpected turn-ON during ESD zapping of claim 34 wherein said ‘n’ serial connected to NMOS devices are connected between the power supply node and said internal sensing node.

36. The method for eliminating the channel unexpected turn-ON during ESD zapping of claim 34 wherein said ‘n’ serially connected NMOS FETS have their drains and gates connected to the power supply voltage, and have their sources are connected to a gate and drain of a next serially connected NMOS FET.

37. The method for eliminating the channel unexpected turn-ON during ESD zapping of claim 36 wherein said second serially connected NMOS FET has its drain and gate connected to said source of said first serially connected NMOS FET and whose source is connected to the drain and gate of said nth serially connected NMOS FET.

38. The method for eliminating the channel unexpected turn-ON during ESD zapping of claim 34 wherein said nth serially connected NMOS FET has its drain and gate connected to said source of a last serially connected NMOS FET and whose source is connected to an internal feedback node.

39. The method for eliminating the channel unexpected turn-ON during ESD zapping of claim 34 wherein said last serially connected NMOS FET has its drain and gate connected to said source of said previous serially connected NMOS FET, and whose source.

40. The method for eliminating the channel unexpected turn-ON during ESD zapping of claim 33 wherein said sensing circuit contains a discharge NMOS FET whose gate is connected to the source of said last serially connected NMOS FET device, whose drain is connected to said internal feedback node and whose source is connected to ground.