TWI658667B - Driving circuit - Google Patents

Abstract

A driving circuit includes a detection circuit, a first control circuit, a second control circuit, and a driving transistor. The detection circuit is coupled between a first power terminal and a second power terminal, and generates a detection signal according to the voltage of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving circuit operates according to the second control signal. The first level is different from the second level.

Description

Drive circuit

The invention relates to a driving circuit, and more particularly to a driving circuit with electrostatic discharge (ESD) protection.

Component damage caused by electrostatic discharge has become one of the most important reliability issues for integrated circuit products. In particular, as the size continues to shrink to the depth of the sub-micron range, the gate oxide layer of gold-oxide semiconductors is becoming thinner and thinner, and integrated circuits are more vulnerable to damage due to electrostatic discharge.

The invention provides a driving circuit including a detection circuit, a first control circuit, a second control circuit and a driving transistor. The detection circuit is coupled between a first power terminal and a second power terminal, and generates a detection signal according to the voltage of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving circuit operates according to the second control signal. The first level is different from the second level.

100, 400‧‧‧ drive circuit

110, 410‧‧‧detection circuit

111, 411‧‧‧ resistance

112, 412‧‧‧ capacitor

113, 413‧‧‧ common nodes

120, 130, 420, 430‧‧‧ control circuit

121, 210, 220, 320, 520‧‧‧P type transistors

122‧‧‧Voltage generating circuit

140, 440‧‧‧ driving transistor

141, 441‧‧‧diodes

151, 152, 451, 452‧‧‧ Power terminals

153, 453‧‧‧ input and output pads

160, 460‧‧‧Core circuit

310, 421, 510‧‧‧N type transistors

330, 530‧‧‧ inverter

422‧‧‧Coupling element

S _O ‧‧‧ Output signal

S _G1 , S _G4 ‧‧‧ detection signal

S _G2 , S _G3 , S _G5 , S _G6 ‧‧‧ control signals

V _O ‧‧‧ Output voltage

FIG. 1 is a possible schematic diagram of the driving circuit of the present invention.

FIG. 2 is a possible schematic diagram of the voltage generating circuit of the present invention.

FIG. 3 shows a possible embodiment of the control circuit of the present invention.

FIG. 4 is another possible schematic diagram of the driving circuit of the present invention.

FIG. 5 is another possible schematic diagram of the control circuit of the present invention.

In order to make the objects, features, and advantages of the present invention more comprehensible, embodiments are exemplified below and described in detail with the accompanying drawings. The description of the present invention provides different embodiments to explain the technical features of different embodiments of the present invention. Wherein, the arrangement of the elements in the embodiments is for the purpose of illustration and is not intended to limit the present invention. In addition, the part of the figures in the embodiments is repeated for the sake of simplifying the description, and does not mean the correlation between different embodiments.

FIG. 1 is a possible schematic diagram of the driving circuit of the present invention. As shown, the driving circuit 100 is coupled to the power terminals 151 and 152 and an input / output pad 153. When the power terminal 151 receives a high operating voltage (such as 5V) and the power terminal 152 receives a low operating voltage (such as 0V), the driving circuit 100 operates in a normal mode. In the normal mode, the driving circuit 100 drives an external circuit, such as an array device, coupled to the input-output pad 153 according to the output signal S _O generated by the core circuit 160.

However, when the power terminal 152 receives a ground voltage and the power terminal 151 is in a floating state, the driving circuit 100 enters a protection mode. In the protection mode, the driving circuit 100 has a releasing capability for releasing the electrostatic discharge current from the input / output pad 153 or the power terminal 152. For example, when a positive electrostatic discharge voltage occurs on the input / output pad 153 and the power terminal 152 is grounded, the driving circuit 100 releases an electrostatic discharge current from the input / output pad 153 to the power terminal 152. When a negative electrostatic discharge voltage occurs on the input / output pad 153 and the power supply terminal 152 is grounded, the driving circuit 100 releases an electrostatic discharge current from the power supply terminal 152 to the input / output pad 153.

In this embodiment, the driving circuit 100 includes a detection circuit 110, control circuits 120, 130, and a driving transistor 140. The detection circuit 110 is coupled between the power terminals 151 and 152 and generates a detection signal S _G1 according to the voltage of the power terminals 151 and 152. In a possible embodiment, when the voltage of the power terminal 152 is a ground voltage and the power terminal 151 is in a floating state, the detection circuit 110 sets the detection signal S _G1 to a first level (such as a low level). In another possible embodiment, when the power terminal 151 receives an operating voltage (such as 5V) and the power terminal 152 receives a ground voltage, the detection circuit 110 sets the detection signal S _G1 to a second level (such as a high level). .

The invention does not limit the circuit architecture of the detection circuit 110. In this embodiment, the detection circuit 110 includes a resistor 111 and a capacitor 112. The resistor 111 is coupled between the power terminal 151 and a common node 113. The capacitor 112 is coupled between the common node 113 and the power terminal 152. In this example, when the power terminal 152 receives a ground voltage and the power terminal 151 is in a floating state, the level of the common node 113 is a low level, in other words, the detection signal S _G1 is a low level. In another possible embodiment, when the power terminal 151 receives a first operating voltage (such as 5V) and the power terminal 152 receives a second operating voltage (such as a ground voltage), the level of the common node 113 is a high level In other words, the detection signal S _G1 is at a high level.

The control circuit 120 generates a control signal S _G2 according to the detection signal S _G1 . For example, when the detection signal S _G1 is at a first level (such as a low level), the control circuit 120 sets the control signal S _G2 to a third level. In a possible embodiment, the third level may be equal to the voltage level of the input / output pad 153. However, when the detection signal S _G1 is at a second level (such as a high level), the control circuit 120 stops providing the control signal S _G2 . At this time, the control signal S _G2 may be at a floating level.

The invention does not limit the circuit architecture of the control circuit 120. In a possible embodiment, the control circuit 120 includes a P-type transistor 121 and a voltage generating circuit 122. The gate of the P-type transistor 121 is coupled to the common node 113, its source is coupled to the input-output pad 153, its drain is coupled to the gate of the driving transistor 140, and its base receives an output voltage V _O. In a possible embodiment, the output voltage V _O is a high voltage. For example, the output voltage V _O may be approximately equal to the level of the input-output pad 153.

The voltage generating circuit 122 is used to generate a high voltage to the base electrode of the P-type transistor 121 to prevent the P-type transistor 121 from generating a leakage current. In a possible embodiment, the voltage generating circuit 122 generates an output voltage V _O according to the voltage of the power terminal 151 and the input / output pads 153. For example, when the voltage of the power terminal 151 is higher than the voltage of the input / output pad 153, the voltage generating circuit 122 outputs the voltage of the power terminal 151 to the base electrode of the P-type transistor 121. When the voltage of the input / output pad 153 is higher than the voltage of the power supply terminal 151, the voltage generating circuit 122 provides the voltage of the input / output pad 153 to the base electrode of the P-type transistor 121. The invention does not limit the circuit architecture of the voltage generating circuit 122. A possible implementation architecture of the voltage generating circuit 122 will be described later using FIG. 2.

The control circuit 130 generates a control signal S _G3 according to the detection signal S _G1 . In this embodiment, the control circuit 130 is coupled between the detection circuit 110 and the core circuit 160 and provides a control signal S _G3 to the gate of the driving transistor 140. When the detection signal S _G1 is at a second level (such as a high level), the control circuit 130 provides the output signal S _O generated by the core circuit 160 as the control signal S _G3 to the driving transistor 140. When the detection signal S _G1 is at a first level (such as a low level), the control circuit 130 stops using the output signal S _O as the control signal S _G3 . At this time, the control signal S _G3 may be at a floating level.

The invention does not limit the circuit architecture of the control circuit 130. In a possible embodiment, the control circuit 130 includes a transmission gate. In this example, when the detection signal S _G1 is at a high level, the transmission gate is turned on to provide the output signal S _O as the control signal S _G3 to the driving transistor 140. When the detection signal S _G1 is at a low level, the transmission gate is turned off to prevent an electrostatic discharge current from entering the core circuit 160. In other embodiments, if the core circuit 160 has a protection circuit for blocking the electrostatic discharge voltage, the control circuit 130 may be omitted. In this example, the core circuit 160 is directly coupled to the driving transistor 140.

In addition, the present invention does not limit the circuit architecture of the core circuit 160. In a possible embodiment, when the output signal S _O is at a high level, the control signal S _G3 is also at a high level. When the output signal S _O is at a low level, the control signal S _G3 is also at a low level. In other embodiments, the level of the output signal S _O is opposite to the level of the control signal S _G3 . For example, when the output signal S _O is at a high level, the control signal S _G3 is at a low level. When the output signal S _O is at a low level, the control signal S _G3 is at a high level.

The driving transistor 140 is coupled between the input / output pad 153 and the power terminal 152. When the power terminal 152 receives a ground voltage and the power terminal 151 is in a floating state, the detection signal S _G1 is at a low level. When the level of the input / output pad 153 is higher than the level of the detection signal S _G1 , the P-type transistor 121 is turned on. At this time, when the input / output pad 153 receives a positive electrostatic discharge voltage, the control signal S _G2 is at a high level. Therefore, the driving transistor 140 is turned on to discharge an electrostatic discharge current from the input / output pad 153 to the power terminal 152. However, if the input / output pad 153 receives a negative electrostatic discharge voltage and the power terminal 152 receives a ground voltage, the parasitic diode 141 of the driving transistor 140 is turned on to release an electrostatic discharge current.

When the power terminal 151 receives a first operating voltage (such as 5V) and the power terminal 152 receives a second operating voltage (such as a ground voltage), the detection signal S _G1 is at a second level (such as a high level). At this time, the control signal S _{G2 is} not controlled by the control circuit 120, and the driving transistor 140 operates according to the control signal S _G3 . For example, when the control signal S _G3 is at a fourth level, the driving transistor 140 is not turned on. When the control signal S _G3 is at a fifth level, the driving transistor 140 is turned on to provide a driving current (not shown). Because the channel size of the driving transistor 140 is large, it has a large driving capacity. In this embodiment, the driving transistor 140 is an N-type transistor. The gate of the driving transistor 140 is coupled to the control circuits 120 and 130, its source is coupled to the input / output pad 153, and its drain and base are coupled to the power terminal 152.

FIG. 2 is a possible schematic diagram of the voltage generating circuit of the present invention. In this embodiment, the voltage generating circuit 122 includes P-type transistors 210 and 220. The gate of the P-type transistor 210 is coupled to the input-output pad 153, its source is coupled to the power terminal 151, and its drain and base are coupled to the base of the P-type transistor 121. When the voltage of the input / output pad 153 is lower than the voltage of the power supply terminal 151, the P-type transistor 210 is turned on to use the voltage of the power supply terminal 151 as the output voltage V _O.

The gate of the P-type transistor 220 is coupled to the power terminal 151, its source is coupled to the input-output pad 153, and its drain and base are coupled to the base of the P-type transistor 121. In this embodiment, when the voltage of the power supply terminal 151 is lower than the voltage of the input / output pad 153, the P-type transistor 220 is turned on to use the voltage of the input / output pad 153 as the output voltage V _O.

FIG. 3 shows a possible embodiment of the control circuit 130 of the present invention. As shown, the control circuit 130 includes an N-type transistor 310, a P-type transistor 320, and an inverter 330. The gate of the N-type transistor 310 is coupled to the input terminal of the inverter 330 and receives a detection signal S _G1 . The drain of the N-type transistor 310 receives the output signal S _O , its source is coupled to the gate of the driving transistor 140, and its base is coupled to the power terminal 152. In this embodiment, when the detection signal S _G1 is at a second level (such as a high level) and the output signal S _O is at a low level, the N-type transistor 310 is turned on to use the output signal S _O as the control signal S _G3 Provided to the driving transistor 140. However, when the detection signal S _G1 is at a first level (such as a low level), the N-type transistor 310 is not turned on.

The gate of the P-type transistor 320 is coupled to the output terminal of the inverter 330, its source receives the output signal S _O , its drain is coupled to the gate of the driving transistor 140, and its base is coupled to the power terminal 151. In this embodiment, when the detection signal S _G1 is at a second level (such as a high level) and the output signal S _O is at a high level, the P-type transistor 320 is turned on to use the output signal S _O as the control signal S _G3 Provided to the driving transistor 140. However, when the detection signal S _G1 is at a first level (such as a low level), the P-type transistor 320 is not turned on.

FIG. 4 is another possible embodiment of the driving circuit of the present invention. As shown, the driving circuit 400 is coupled to the power terminals 451 and 452 and an input / output pad 453. When the power terminal 451 receives a high operating voltage (such as 5V) and the power terminal 452 receives a low operating voltage (such as 0V), the driving circuit 400 operates in a normal mode. In the normal mode, the driving circuit 400 drives a load (not shown) according to the output signal S _O generated by the core circuit 460. However, when the power terminal 451 receives a ground voltage and the power terminal 452 is in a floating state, the driving circuit 400 operates in a protection mode. In the protection mode, when an electrostatic discharge event occurs at the power terminal 451 or the input / output pad 453, the driving circuit 400 releases the electrostatic discharge current from the power terminal 451 or the input / output pad 453.

In this embodiment, the driving circuit 400 includes a detection circuit 410, control circuits 420 and 430, and a driving transistor 440. The detection circuit 410 is coupled between the power terminals 451 and 452 and generates a detection signal S _G4 according to the voltage of the power terminals 451 and 452. In a possible embodiment, when the power terminal 451 receives a first operating voltage (such as 5V) and the power terminal 452 receives a second operating voltage (such as a ground voltage), the detection circuit 410 sets the detection signal S _G4 to a First level (such as low level). In another possible embodiment, when the voltage of the power terminal 451 is a ground voltage and the power terminal 452 is in a floating state, the detection circuit 410 sets the detection signal S _G4 to a second level (such as a low level).

The invention does not limit the circuit architecture of the detection circuit 410. In a possible embodiment, the detection circuit 410 includes a resistor 411 and a capacitor 412. The resistor 411 is coupled between the power terminal 452 and a common node 413. The capacitor 412 is coupled between the common node 413 and the power terminal 451. In this example, when the power terminal 451 receives a ground voltage and the power terminal 452 is in a floating state, the level of the common node 413 is a second level (such as a low level). Therefore, the detection signal S _G4 is also at the second level. In another possible embodiment, when the power terminal 451 receives a first operating voltage (such as 5V) and the power terminal 452 receives a second operating voltage (such as a ground voltage), the level of the common node 413 is first. Standard (such as low level). In this example, the detection signal S _G4 is at the first level.

The control circuit 420 generates a control signal S _G5 according to the detection signal S _G4 . For example, when the power terminal 451 receives a ground voltage and the power terminal 452 is in a floating state, if the input / output pad 453 receives a negative electrostatic discharge voltage, the control circuit 420 sets the control signal S _G5 to a first Three levels (such as a low level). In a possible embodiment, the third level may be equal to the voltage level of the input / output pad 453. However, when the power terminal 451 receives a first operating voltage (such as 5V) and the power terminal 452 receives a second operating voltage (such as a ground voltage), the control circuit 420 stops providing the control signal S _G5 . At this time, the control signal S _G5 may be at a floating level.

The invention does not limit the circuit architecture of the control circuit 420. In a possible embodiment, the control circuit 420 includes an N-type transistor 421 and a coupling element 422. The gate of the N-type transistor 421 is coupled to the common node 413, its source is coupled to the input / output pad 453, its drain is coupled to the gate of the driving transistor 440, and its base is coupled to the power terminal 452. The coupling element 422 is coupled between the gate of the driving transistor 440 and the input / output pad 453. In a possible embodiment, the coupling element 422 is a capacitor. When the input / output pad 453 receives a negative electrostatic discharge voltage, the coupling element 422 pulls down the level of the control signal S _G5 . In another possible embodiment, the N-type transistor 421 is turned on, and the level of the control signal S _G5 can also be lowered. In a possible embodiment, the control signal S _G5 is approximately equal to the level of the input / output pad 453.

The control circuit 430 generates a control signal S _G6 according to the detection signal S _G4 . In this embodiment, the control circuit 430 is coupled between the gate of the driving transistor 440 and the detection circuit 410 and receives an output signal S _O generated by the core circuit 460. In a possible embodiment, the power terminal 452 is grounded, so the detection signal S _G4 is at a first level (such as a low level). At this time, if an electrostatic discharge event does not occur, the control circuit 430 provides the output signal S _O generated by the core circuit 460 as the control signal S _G6 to the driving transistor 440. However, when the voltage of the power supply terminal 451 is a ground voltage and the power supply terminal 452 is in a floating state, when an electrostatic discharge event occurs on the input / output pad 453, the control circuit 430 stops using the output signal _SO as the control signal S _G6 . At this time, the control signal S _G6 may be in a floating state. The invention does not limit the circuit architecture of the control circuit 430. A possible circuit architecture of the control circuit 430 will be described later with reference to FIG. 5. In addition, the characteristics of the core circuit 460 are similar to those of the core circuit 160 in FIG.

The driving transistor 440 is coupled between the input / output pad 453 and the power terminal 451. When the power terminal 451 receives a ground voltage and the power terminal 452 is in a floating state, the control signal S _G4 is at a second level (such as a low level). At this time, if the input / output pad 453 receives a negative electrostatic discharge voltage, since the source voltage of the N-type transistor 421 is lower than the gate voltage of the N-type transistor 421, the N-type transistor 421 is turned on and coupled. The element 422 pulls down the level of the control signal S _G5 . Since the control signal S _G5 is at a low level, the driving transistor 440 is turned on to discharge an electrostatic discharge current. However, if the input / output pad 453 receives a positive electrostatic discharge voltage and the power terminal 151 receives a ground voltage, the parasitic diode 441 of the driving transistor 440 is turned on to discharge an electrostatic discharge current to the ground.

When the power terminal 451 receives a first operating voltage (such as 5V) and the power terminal 452 receives a second operating voltage (such as a ground voltage), the voltage between the gate and the base of the N-type transistor 421 is approximately equal to the second operating voltage. . Therefore, the N-type transistor 421 is not turned on. At this time, the control signal S _G5 is at a floating level. In this example, the driving transistor 440 operates in accordance with the control signal S _G6 . For example, when the control signal S _G6 is at a fourth level (such as a high level), the driving transistor 440 is not turned on. When the control signal S _G6 is at a fifth level (such as a low level), the driving transistor 440 is turned on. Because the channel size of the driving transistor 440 is large, it has a large driving capacity.

In this embodiment, the driving transistor 440 is a P-type transistor. The gate of the driving transistor 440 is coupled to the control circuits 420 and 430, its drain is coupled to the input / output pad 453, and its source and base are coupled to the power terminal 451.

FIG. 5 is a possible embodiment of the control circuit 430 of FIG. 4. The control circuit 430 includes an N-type transistor 510, a P-type transistor 520, and an inverter 530. An input terminal of the inverter 530 receives a control signal S _G4 . An output terminal of the inverter 530 is coupled to a gate of the N-type transistor 510. Because the operating voltage of the inverter 530 comes from the power terminals 451 and 452. Therefore, when the power terminal 451 receives a first operating voltage (such as 5V) and the power terminal 452 receives a second operating voltage (such as a ground voltage), the inverter 530 is enabled to invert the control signal S _G4 . In another possible embodiment, when the voltage at the power terminal 451 is a ground voltage and the power terminal 452 is in a floating state, the inverter 530 is disabled because the inverter 530 no longer receives a normal operating voltage. Yes, the control signal S _{G4 is} no longer inverted. In this example, the output of the inverter 530 is at a floating level. The drain of the N-type transistor 510 receives the output signal S _O , its source is coupled to the gate of the driving transistor 440, and its base is coupled to the power terminal 452. P-type gate electrode coupled to the crystal 520 connected to the input of inverter 530 which receives the output signal of the source S _O, its drain coupled to the driving transistor gate electrode 440, its base electrode coupled to the power terminal 451.

When the power terminal 451 receives a first operating voltage (such as 5V) and the power terminal 452 receives a second operating voltage (such as a ground voltage), the detection signal S _G4 is at a first level (such as a low level). The inverter 530 inverts the control signal S _G4 and outputs a high-level signal for turning on the N-type transistor 510. At this time, when the core circuit 460 generates an output signal S _O, P-type electrically conducting crystal 520 on. In this example, the N-type transistor 510 and the P-type transistor 520 are turned on. Therefore, the output signal S _{O is provided} as the control signal S _G6 to the driving transistor 440. When the voltage of the power terminal 451 is a ground voltage and the power terminal 452 is in a floating state, the inverter 530 is disabled. Since the output signal of the inverter 530 is a floating level, the N-type transistor 510 is not turned on. At this time, since the core circuit 460 stops generating the output signal S _O , the output signal S _O is in a floating state. Therefore, the P-type transistor 520 is not turned on. In this example, the N-type transistor 510 and the P-type transistor 520 are not turned on. At this time, the control signal S _G6 may be at a floating level.

Unless otherwise defined, all terms (including technical and scientific terms) herein are generally understood by those having ordinary knowledge in the technical field to which this invention belongs. In addition, unless explicitly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with its meaning in articles in the relevant technical field, and should not be interpreted as ideal or overly formal.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device, or method according to the embodiments of the present invention may be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

Claims (14)

A driving circuit includes: a detection circuit coupled between a first power terminal and a second power terminal, and generating a detection signal according to the voltage of the first and second power terminals; a first control circuit Generating a first control signal according to the detection signal; a second control circuit generating a second control signal according to the detection signal; and a driving transistor coupled to an input / output pad and the second power terminal Between, when the detection signal is a first level, the driving transistor is turned on according to the first control signal, and when the detection signal is a second level, the driving transistor is turned on according to the second control Signal, the first level is different from the second level. The driving circuit according to item 1 of the scope of the patent application, wherein the driving transistor system is an N-type transistor. The driving circuit according to item 2 of the scope of the patent application, wherein the detection circuit includes a resistor and a capacitor, the resistor is coupled between the first power terminal and a common node, and the capacitor is coupled to the common node And the second power terminal. The driving circuit according to item 3 of the scope of patent application, wherein the first control circuit includes: a voltage generating circuit that generates an output voltage according to the voltage of the first power supply terminal and the input-output pad; and a first P-type The gate of the transistor is coupled to the common node, the source is coupled to the input-output pad, the drain is coupled to the gate of the N-type transistor, and the base of the transistor receives the output voltage. The driving circuit according to item 4 of the scope of patent application, wherein when the voltage of the first power terminal is higher than the voltage of the input / output pad, the output voltage is equal to the voltage of the first power terminal, and when the voltage of the input / output pad is high When the voltage at the first power source terminal, the output voltage is equal to the voltage of the input / output pad. The driving circuit according to item 4 of the scope of patent application, wherein the voltage generating circuit includes a second P-type transistor, the gate of which is coupled to the input-output pad, the source of which is coupled to the first power terminal, and The drain electrode and the base electrode are coupled to the base electrode of the first P-type transistor; and a third P-type transistor, the gate of which is coupled to the first power terminal, the source of which is coupled to the input-output pad, and the drain thereof. A pole and a base electrode are coupled to the base electrode of the first P-type transistor. The driving circuit according to item 1 of the scope of the patent application, wherein the driving transistor system is a P-type transistor. The driving circuit according to item 7 of the scope of patent application, wherein the detection circuit includes a first capacitor and a resistor, the first capacitor is coupled between the first power terminal and a common node, and the resistor is coupled Between the common node and the second power terminal. The driving circuit according to item 8 of the scope of patent application, wherein the first control circuit includes: an N-type transistor whose gate is coupled to the common node and whose drain is coupled to the gate of the P-type transistor, Its source is coupled to the input-output pad, its base is coupled to the first power terminal; and a coupling element is coupled between the gate of the P-type transistor and the input-output pad. The driving circuit according to item 9 of the scope of patent application, wherein the coupling element is a second capacitor. The driving circuit according to item 1 of the scope of patent application, wherein the second control circuit includes: a transmission gate, coupled between the gate of the driving transistor and a core circuit, when the detection signal is the first At the second level, the transmission gate provides an output signal generated by the core circuit as the second control signal to the driving transistor. When the detection signal is at the first level, the transmission gate stops the output signal. As the second control signal. The driving circuit according to item 11 of the patent application, wherein when the detection signal is the first level, the second control signal is a floating level. The driving circuit according to item 1 of the scope of patent application, wherein the second control circuit includes: a transmission gate, coupled between the gate of the driving transistor and a core circuit, when the detection signal is the first When one bit is on time, the transmission gate provides an output signal generated by the core circuit to the driving transistor as the second control signal. When the detection signal is the second level, the transmission gate stops outputting the output signal. As the second control signal. The driving circuit according to item 13 of the patent application, wherein when the detection signal is the second level, the second control signal is a floating level.