TWI716939B - Operation circuit - Google Patents

Abstract

An operation circuit coupled between an input/output pad and a ground terminal and including a core circuit, an N-type transistor, an electrostatic discharge (ESD) protection circuit and a control circuit is provided. The N-type transistor determines whether to turn on a path between the core circuit and the ground terminal according to a voltage level of a specific node. The ESD protection circuit is coupled between the input/output pad and the core circuit to avoid an ESD current passing through the core circuit and includes a detection circuit and a release element. The detection circuit detects whether an ESD event occurs at the input/output to generate a detection signal. The release element provides a discharge path to release the ESD current. The control circuit controls the voltage level of the specific node according to the detection signal.

Description

Operating circuit

The present invention relates to an operating circuit, in particular to an operating circuit with electrostatic discharge (ESD) protection function.

The component damage caused by electrostatic discharge (ESD) has become one of the most important reliability problems for integrated circuit products. In particular, as the size continues to shrink to the depth of sub-micron level, the gate oxide layer of the MOS semiconductor is getting thinner and thinner, and the integrated circuit is more susceptible to damage due to electrostatic discharge.

The present invention provides an operating circuit, which is coupled between an input and output pad and a ground terminal, and includes a core circuit, an N-type transistor, an electrostatic discharge protection circuit and a control circuit. The N-type transistor determines whether to conduct a path between the core circuit and the ground terminal according to the voltage level of a specific node. The electrostatic discharge protection circuit is coupled between the input and output pads and the core circuit to prevent an electrostatic discharge current from flowing through the core circuit, and includes a detection circuit and a release element. The detection circuit detects whether an electrostatic discharge event occurs on the input and output pads to generate a detection signal. The release element provides a release path according to the detection signal to release the electrostatic discharge current. The control circuit controls the voltage level of a specific node according to the detection signal.

In order to make the purpose, features and advantages of the present invention more comprehensible, embodiments are specifically listed below, in conjunction with the accompanying drawings, for detailed description. The specification of the present invention provides different examples to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustrative purposes, and is not intended to limit the present invention. In addition, the part of the repetition of the drawing symbols in the embodiments is for simplifying the description and does not mean the relevance between different embodiments.

Figure 1 is a possible schematic diagram of the operating circuit of the present invention. As shown in the figure, the operating circuit 100 includes a core circuit 110, an N-type transistor NT1, an electrostatic discharge protection circuit 120, and a control circuit 130. The core circuit 110 is controlled by the control circuit 130. FIG. 1 only shows a part of the structure of the control circuit 130, and this part of the structure is related to the present invention, but is not intended to limit the present invention. The control circuit 130 may still have other hardware architectures. For the convenience of description, the other hardware architectures of the control circuit 130 are omitted in FIG. 1. The present invention does not limit the structure of the core circuit 110. Any circuit that is affected by electrostatic discharge current can be used as the core circuit 110.

In a possible embodiment, the core circuit 110 includes a fuse 111 and an internal circuit 112. The internal circuit 112 is used to program the fuse 111. The present invention does not limit the connection relationship between the fuse 111 and the internal circuit 112. In this embodiment, the internal circuit 112 is coupled between the electrostatic discharge protection circuit 120 and the fuse 111, and the fuse 111 is coupled between the internal circuit 112 and the N-type transistor NT1. In other embodiments, the fuse 111 is coupled between the electrostatic discharge protection circuit 120 and the internal circuit 112, and the internal circuit 112 is coupled between the fuse 111 and the N-type transistor NT1.

When the ESD event does not occur, the internal circuit 112 through the input-output pad 140 may receives a drive signal S _D, and the drive signal S _D, generates a current I, for stylized (Programming) fuse 111. When the fuse 111 is programmed, the fuse 111 may switch from a first state to a second state. For example, when the current I flows through the fuse 111, the fuse 111 may switch from a short state to an open state. In another possible embodiment, the fuse 111 may be switched from an open circuit state to a short circuit state.

However, when an electrostatic discharge event occurs to the input/output pad 140, the internal circuit 112 may be damaged by the electrostatic discharge current from the input/output pad 140. In addition, the internal circuit 112 may incorrectly program the fuse 111 due to the influence of the electrostatic discharge current. Since the state of the fuse 111 is changed abnormally, the internal circuit 112 may malfunction. In this embodiment, when an electrostatic discharge event occurs, the control circuit 130 can prevent the fuse from being programmed incorrectly.

The N-type transistor NT1 determines whether to turn on the path PA between the core circuit 110 and the ground terminal 150 according to the voltage level of a specific node NG. For example, when the voltage level of the specific node NG is a high level (such as 5V), the N-type transistor NT1 is turned on, so the path PA is turned on. Therefore, the core circuit 110 is coupled to the ground terminal 150 through the path PA. However, when the voltage level of the specific node NG is at a low level (such as 0V), the N-type transistor NT1 is not conductive, so the path PA is not conductive. Therefore, the core circuit 110 is not electrically connected to the ground terminal 150.

In this embodiment, the gate of the N-type transistor NT1 is coupled to a specific node NG, its drain is coupled to the core circuit 110, and its source and bulk are coupled to ground端150. When an electrostatic discharge event occurs on the input/output pad 140, the N-type transistor NT1 is not turned on, so that the electrostatic discharge current does not flow through the core circuit 110.

The electrostatic discharge protection circuit 120 is coupled between the input/output pad 140 and the core circuit 110 to prevent electrostatic discharge current from flowing through the core circuit 110. The invention does not limit the structure of the electrostatic discharge protection circuit 120. Any circuit architecture that can prevent electrostatic discharge current from flowing into the core circuit 110 and does not affect the operation of the core circuit 110 when an electrostatic discharge event does not occur can be used as the electrostatic discharge protection circuit 120. In this embodiment, the electrostatic discharge protection circuit 120 includes a detection circuit 121 and a release element 122.

The detection circuit 121 detects whether an electrostatic discharge event occurs on the input/output pad 140 to generate a detection signal T2. For example, when an electrostatic discharge event occurs on the input/output pad 140 and the ground terminal 150 receives a ground level VSS, the detection signal T2 is at a specific level (such as a high level). When the electrostatic discharge event does not occur, the detection signal T2 is not at a specific level (for example, a low level).

In other embodiments, the detection circuit 121 further generates another detection signal T1. The detection signal T1 is an inverted signal of the detection signal T2. For example, when the detection signal T1 is at a high level, the detection signal T2 is at a low level. When the detection signal T1 is at a low level, the detection signal T2 is at a high level. The invention does not limit the structure of the detection circuit 121. The possible implementation of the detection circuit 121 will be described later through FIGS. 4 and 5.

The release element 122 provides a release path according to the detection signal T2 to release the electrostatic discharge current. For example, when an electrostatic discharge event occurs on the input/output pad 140 and the ground terminal 150 receives the ground level VSS, the detection signal T2 is at a specific level. Therefore, the release element 122 is turned on to release the electrostatic discharge current from the input/output pad 140 to the ground terminal 150. When the electrostatic discharge event does not occur, the discharge element 122 is not conductive.

The invention does not limit the type of release element 122. In a possible embodiment, the release element 122 is an N-type transistor ESDN. The gate of the N-type transistor ESDN is coupled to the node ND2, its first source/drain is coupled to the input/output pad 140, and its second source/drain and base are coupled to the ground terminal 150.

When an electrostatic discharge event occurs on the input/output pad 140 and the ground terminal 150 receives the ground level VSS, the N-type transistor ESDN is turned on. At this time, if the I/O pad 140 receives a positive electrostatic discharge voltage, the N-type transistor ESDN will discharge the electrostatic discharge current from the I/O pad 140 to the ground terminal 150. If the input/output pad 140 receives a negative electrostatic discharge voltage, the parasitic diode D between the drain and the base of the N-type transistor ESDN releases the electrostatic discharge current from the ground terminal 150 to the input/output pad 140.

The control circuit 130 controls the voltage level of the specific node NG according to the detection signal T2. For example, when the detection signal T2 is at a specific level, it indicates that an electrostatic discharge event has occurred, so the control circuit 130 sets the level of the specific node NG to be equal to a predetermined level SP. In a possible embodiment, the preset level SP is equal to the ground level VSS. In another possible embodiment, the preset level SP is equal to the level of the detection signal T1. However, when the detection signal T2 is not at a specific level, it means that no electrostatic discharge event has occurred, so the control circuit 130 provides a specific signal SIG to a specific node NG.

In this embodiment, the control circuit 130 includes an N-type transistor N4. The gate of the N-type transistor N4 receives the detection signal T2, its drain is coupled to the specific node NG, its source receives the preset level SP, and its base receives the ground level VSS. When the detection signal T2 is at a specific level, the N-type transistor N4 is turned on to transmit the preset level SP to the specific node NG. When the detection signal T2 is not at a specific level, the N-type transistor N4 is not turned on to stop transmitting the preset level SP to the specific node NG. At this time, the control circuit 130 transmits the specific signal SIG to the specific node NG. In one possible embodiment, the specific signal SIG is generated by a signal generating circuit (not shown).

Figure 2 is another possible schematic diagram of the operating circuit of the present invention. The operating circuit 200 includes a core circuit 210, an N-type transistor NT2, an electrostatic discharge protection circuit 220, and a control circuit 230. The electrostatic discharge protection circuit 220 is coupled to the input and output pad 240 and the ground terminal 250. The ground terminal 250 receives a ground level VSS. Since the characteristics of the core circuit 210, the N-type transistor NT2, and the electrostatic discharge protection circuit 220 in Figure 2 are similar to those of the core circuit 110, the N-type transistor NT1, and the electrostatic discharge protection circuit 120 in Figure 1, they will not be repeated here. .

In this embodiment, the control circuit 230 in FIG. 2 has one more P-type transistor P4 than the control circuit 130 in FIG. As shown in the figure, the P transistor P4 is connected in parallel with the N type transistor N4, and the voltage level of the specific node NG is set according to the detection signal T1. Since the detection signal T2 is an inverted signal of the detection signal T1, when the N-type transistor N4 is turned on, the P-type transistor P4 is also turned on. Therefore, the N-type transistor N4 and the P-type transistor P4 transmit a specific level SP to a specific node NG. When the N-type transistor N4 is not conducting, the P-type transistor P4 is also not conducting. Therefore, the N-type transistor N4 and the P-type transistor P4 stop transmitting the specific level SP to the specific node NG.

In this embodiment, the gate of the P-type transistor P4 receives the detection signal T1, its first source/drain is coupled to a specific node NG, its second source/drain receives a specific level SP, and its base receives An operating voltage VDD. In a possible embodiment, the operating voltage VDD is higher than the ground level VSS.

Figure 3 is another possible schematic diagram of the operating circuit of the present invention. The operating circuit 300 includes a core circuit 310, an N-type transistor NT3, an electrostatic discharge protection circuit 320, and a control circuit 330. The electrostatic discharge protection circuit 320 is coupled to the input/output pad 340 and the ground terminal 350. The ground terminal 350 receives a ground level VSS. Since the characteristics of the core circuit 310, the N-type transistor NT3, and the electrostatic discharge protection circuit 320 in FIG. 3 are similar to those of the core circuit 110, the N-type transistor NT1, and the electrostatic discharge protection circuit 120 in FIG. 1, they will not be repeated here. .

The control circuit 330 in FIG. 3 has an N-type transistor N3 and a P-type transistor P3 more than the control circuit 230 in FIG. 2. The N-type transistor N3 is coupled between the specific node NG and a signal generating circuit (not shown), and determines whether to transmit the specific signal SIG to the specific node NG according to the detection signal T1. As shown in the figure, the gate of the N-type transistor N3 receives the detection signal T1, its first source/drain is coupled to the specific node NG, its second source/drain receives the specific signal SIG, and its base receives the ground bit Quasi-VSS.

The P-type transistor P3 is connected in parallel with the N-type transistor N3, and according to the detection signal T2, it is determined whether to send a specific signal SIG to a specific node NG. As shown in the figure, the gate of the P-type transistor P3 receives the detection signal T2, its first source/drain is coupled to the specific node NG, the second source/drain receives the specific signal SIG, and its base receives the operating voltage VDD .

In this embodiment, since the detection signal T2 is an inverted signal of the detection signal T1, when the N-type transistor N3 is turned on, the P-type transistor P3 is also turned on. Therefore, the N-type transistor N3 and the P-type transistor P3 transmit the specific signal SIG to the specific node NG. When the N-type transistor N3 is not conducting, the P-type transistor P3 is also not conducting. Therefore, the N-type transistor N3 and the P-type transistor P3 stop transmitting the specific signal SIG to the specific node NG.

In other embodiments, when the N-type transistor N4 is turned on, the N-type transistor N3 is not turned on. Therefore, the level of the specific node NG is equal to the ground level VSS. When the N-type transistor N4 is not conducting, the N-type transistor N3 is conducting. Therefore, the level of the specific node NG is equal to the specific signal SIG.

Figure 4 is a possible example of the detection circuit of the present invention. As shown in the figure, the detection circuit 400 includes a resistor 410, a capacitor 420, and an inverter 430. The resistor 410 is coupled between the input/output pad 440 and the node ND1. The capacitor 420 is coupled between the node ND1 and the ground terminal 450. In this embodiment, the capacitor 420 is an N-type transistor N0. As shown in the figure, the gate of the N-type transistor N0 is coupled to the node ND1. The source, drain and base of the N-type transistor N0 are all coupled to the ground terminal 450. In a possible embodiment, the ground terminal 450 receives a ground level VSS.

When an electrostatic discharge event occurs on the input/output pad 440 and the ground terminal 450 receives the ground level VSS, due to the characteristics of the capacitor 420, the node ND1 is at a low level, which is approximately equal to the ground level VSS. However, when the electrostatic discharge event does not occur on the input and output pad 440, if the input and output pad 440 receives a first operating voltage (such as 5V) and the ground terminal 450 receives the ground level VSS, the node ND1 is at a high level (such as 5V). In this embodiment, the level of the node ND1 is used as a detection signal T1.

The inverter 430 inverts the level of the detection signal T1 to generate the detection signal T2. Therefore, the detection signal T2 (such as the first detection signal) is an inverted signal of the detection signal T1 (such as the second detection signal). In this embodiment, the inverter 430 includes a P-type transistor P1 and an N-type transistor N1.

The gate of the P-type transistor P1 is coupled to the node ND1. The first source/drain and base of the P-type transistor P1 are coupled to the input/output pad 440. The second source/drain of the P-type transistor P1 is coupled to the node ND2. The gate of the N-type transistor N1 is coupled to the node ND1. The first source/drain of the N-type transistor N1 is coupled to the node ND2. The second source/drain and base of the N-type transistor N1 are coupled to the ground terminal 450. In this embodiment, the voltage level of the node ND2 is used as the detection signal T2.

In a normal mode (no electrostatic discharge event occurs), the input and output pad 440 receives a first operating voltage (such as 5V), and the ground terminal 450 receives a second operating voltage (such as 0V), wherein the first operating voltage is greater than the second Operating voltage. At this time, the detection signal T1 is approximately equal to the first operating voltage. Therefore, the N-type transistor N1 is turned on, so that the detection signal T2 is approximately equal to the second operating voltage.

In a protection mode (an electrostatic discharge event occurs), the input/output pad 440 receives an electrostatic discharge voltage, and the ground terminal 450 receives a ground level (such as 0V). At this time, the detection signal T1 is approximately equal to the ground level. Therefore, the P-type transistor P1 is turned on, so that the detection signal T2 is at a high level (ie, a specific level). At this time, a release element (such as the release element 122 in FIG. 1) outside the detection circuit 400 is turned on to release the electrostatic current from the input/output pad 440 to the ground terminal 450 to prevent the electrostatic current from flowing into the core circuit.

Figure 5 is another implementation structure of the detection circuit of the present invention. As shown in the figure, the detection circuit 500 includes a capacitor 510, a resistor 520, and an inverter 530. The capacitor 510 is coupled between the input/output pad 540 and the node ND3. In this embodiment, the capacitor 510 is a P-type transistor P0. The gate of the P-type transistor P0 is coupled to the node ND3. The source, drain, and base of the P-type transistor P0 are coupled to the input/output pad 540. The resistor 520 is coupled between the node ND3 and the ground terminal 550. In this embodiment, the voltage level of the node ND3 is used as the detection signal T2.

The inverter 530 inverts the voltage level of the detection signal T2 to generate the detection signal T1. In this embodiment, the inverter 530 includes a P-type transistor P2 and an N-type transistor N2. The gate of the P-type transistor P2 is coupled to the node ND3, its first source/drain and base are coupled to the input/output pad 540, and its second source/drain is coupled to the node ND4. The gate of the N-type transistor N2 is coupled to the node ND3, its first source/drain is coupled to the node ND4, and its second source/drain and base are coupled to the ground terminal 550.

In a normal mode (no electrostatic discharge event occurs), the input/output pad 540 receives a first operating voltage (such as 5V), and the ground terminal 550 receives a second operating voltage (such as 0V), where the first operating voltage is greater than the second Operating voltage. At this time, the detection signal T2 is approximately equal to the second operating voltage. Therefore, the P-type transistor P2 is turned on, so that the detection signal T1 is approximately equal to the first operating voltage.

In a protection mode (an electrostatic discharge event occurs), the input/output pad 540 receives an electrostatic discharge voltage, and the ground terminal 550 receives a ground level (such as 0V). At this time, the detection signal T2 is at a high level (for example, called a specific level). Therefore, the N-type transistor N2 is turned on, so that the detection signal T1 is at a low level.

Unless otherwise defined, all vocabulary (including technical and scientific vocabulary) herein belong to the general understanding of persons with ordinary knowledge in the technical field of the present invention. In addition, unless clearly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device, or method of the embodiment of the present invention can be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100, 200, 300: operating circuit

110, 210, 310: core circuit

111: Fuse

112: Internal circuit

120, 220, 320: Electrostatic discharge protection circuit

121, 400, 500: detection circuit

122, 222, 322: release element

130, 230, 330: control circuit

140, 240, 340, 440, 540: input and output pads

150, 250, 350, 450, 550: ground terminal

410, 520: resistance

420, 510: Capacitor

430, 530: inverter

I: Operating current

NG: specific node

ND1~ND4: Node

T1, T2: detection signal

VSS: Ground level

NT1~NT3, ESDN, N0~N4: N-type transistor

P0~P4: P-type transistor

D: Parasitic diode

SP: preset level

SIG: specific signal

PA: path

S _D : drive signal

Figure 1 is a possible schematic diagram of the operating circuit of the present invention. Figure 2 is another possible schematic diagram of the operating circuit of the present invention. Figure 3 is another possible schematic diagram of the operating circuit of the present invention. Figure 4 is a possible example of the detection circuit of the present invention. Figure 5 is another implementation structure of the detection circuit of the present invention.

100: operating circuit

110: core circuit

111: Fuse

112: Internal circuit

120: Electrostatic discharge protection circuit

121: detection circuit

122: release element

130: control circuit

S _D : drive signal

140: input and output pad

150: Ground terminal

I: Operating current

NG: specific node

T1, T2: detection signal

VSS: Ground level

D: Parasitic diode

SP: preset level

SIG: specific signal

PA: path

NT1, ESDN, N4: N-type transistor

Claims (14)

An operating circuit, coupled between an input and output pad and a ground terminal, and comprising: a core circuit; a first N-type transistor, according to the voltage level of a specific node, determines whether to conduct the core circuit and the A path between the ground terminals; an electrostatic discharge protection circuit, coupled between the input and output pad and the core circuit, to prevent an electrostatic discharge current from flowing through the core circuit, and includes: a detection circuit, detection Detecting whether an electrostatic discharge event occurs on the input and output pad to generate a first detection signal; and a release element, which provides a release path according to the first detection signal, to discharge the electrostatic discharge current; and a The control circuit controls the voltage level of the specific node according to the first detection signal; the detection circuit further generates a second detection signal, and the second detection signal is the inverse of the first detection signal Signal; wherein when the electrostatic discharge event occurs, the control circuit transmits the second detection signal to the specific node. The operating circuit described in claim 1, wherein the core circuit includes a fuse and an internal circuit. When the internal circuit receives a driving signal through the input/output pad, the internal circuit generates a current according to the driving signal When the current flows through the fuse, the fuse is programmed. As for the operating circuit described in item 1 of the scope of the patent application, when the electrostatic discharge event occurs on the input and output pad, the first N-type transistor is not turned on to prevent The path between the core circuit and the ground terminal is turned on. For example, the operating circuit described in claim 1, wherein the control circuit includes: a first transistor, when the electrostatic discharge event occurs on the input and output pad, the voltage level of the specific node is set to prevent The first N-type transistor is turned on. According to the operating circuit described in claim 4, the first transistor sets the voltage level of the specific node to be equal to the second detection signal according to the first detection signal. The operating circuit described in claim 4, wherein the control circuit further includes: a second transistor connected in parallel with the first transistor, and setting the voltage level of the specific node according to the second detection signal; When the first transistor is turned on, the second transistor is also turned on, and when the first transistor is not turned on, the second transistor is also not turned on. For the operation circuit described in item 6 of the scope of patent application, the control circuit further includes: a third transistor coupled to the specific node, and according to the second detection signal, determines whether to transmit a specific signal to the A specific node; and a fourth transistor, coupled to the specific node, and according to the first detection signal, determines whether to transmit the specific signal to the specific node; when the third transistor is turned on, the fourth transistor The crystal is also conductive. When the third transistor is not conductive, the fourth transistor is also not conductive. As the operating circuit described in item 7 of the scope of patent application, when the first transistor is conducting, the third transistor is not conducting, and when the first transistor is not conducting, the The third transistor is turned on. The operating circuit described in claim 1, wherein the detection circuit includes: a resistor coupled between the input and output pad and a first node; and a capacitor coupled between the first node and the first node Between the ground terminals, the voltage level of the first node is used as the second detection signal; and an inverter inverts the second detection signal to generate the first detection signal. The operating circuit described in item 9 of the scope of patent application, wherein the capacitor is a second N-type transistor, the gate of the second N-type transistor is coupled to the first node, and the second N-type transistor The source and drain are coupled to the ground terminal. The operating circuit described in claim 10, wherein the inverter includes: a P-type transistor having a first gate, a first source/drain, and a second source/drain, the The first gate is coupled to the first node, the first source/drain is coupled to the input output pad, the second source/drain is coupled to a second node; and a third N-type transistor having a A second gate, a third source/drain, and a fourth source/drain, the second gate is coupled to the first node, the third source/drain is coupled to the second node, the fourth The source/drain is coupled to the ground terminal. According to the operating circuit described in claim 1, wherein the detection circuit includes: a capacitor coupled between the input and output pad and a first node; and a resistor coupled between the first node and the first node Between ground terminals, the voltage level of the first node is used as the first detection signal; and an inverter inverts the first detection signal to generate the second detection signal. The operating circuit described in claim 12, wherein the capacitor is a first P-type transistor, the gate of the first P-type transistor is coupled to the first node, and the first P-type transistor The source and drain are coupled to the input and output pad. The operating circuit described in claim 13, wherein the inverter includes: a second P-type transistor having a first gate, a first source/drain, and a second source/drain , The first gate is coupled to the first node, the first source/drain is coupled to the input and output pad, the second source/drain is coupled to a second node; and a second N-type transistor, Has a second gate, a third source/drain, and a fourth source/drain, the second gate is coupled to the first node, the third source/drain is coupled to the second node, the The fourth source/drain is coupled to the ground terminal.

Images