TWI795068B - Electrostatic discharge protection circuit - Google Patents

Abstract

An electrostatic discharge (ESD) protection circuit including a detection circuit, a voltage divider, and a discharge element is provided. The detection circuit is coupled between a first power line and a second power line. When an ESD event occurs, the detection circuit enables a turning-on signal. The voltage divider is coupled between the first power line and a third power line and receives the turning-on signal. The discharge element is coupled between the second and third power lines. When the turning-on signal is enabled, the discharge element releases an ESD current.

Description

Electrostatic discharge protection circuit

The invention relates to a protection circuit, in particular to an electrostatic discharge protection circuit.

Component damage caused by Electrostatic discharge (ESD) has become one of the most important reliability issues for integrated circuit products. Especially as the size continues to shrink down to the sub-micron level, the gate oxide layer of the metal oxide semiconductor is getting thinner and thinner, and the integrated circuit is more likely to be damaged by electrostatic discharge.

An embodiment of the present invention provides an electrostatic discharge protection circuit, which includes a detection circuit (110), a voltage dividing element (120) and a release element (130). The detection circuit is coupled between a first power line (PL1) and a second power line (PL2). The voltage dividing element is coupled between the first power line ( PL1 ) and the third power line ( PL3 ), and receives the conduction signal. The release element is coupled between the second and third power lines. When an electrostatic discharge event occurs on the third power line, the detection circuit is activated by the voltage dividing element, and the detection circuit enables a conduction signal. When the conduction signal is enabled, the release element releases an electrostatic discharge current.

In another embodiment, the electrostatic discharge protection circuit includes a detection circuit (110), a voltage dividing element (120), a first transistor (130) and a second transistor (140). The detection circuit is coupled between a first power line (PL1) and a second power line (PL2). When an electrostatic discharge event occurs on the third power line, the detection circuit is activated by the voltage dividing element, and the detection circuit enables a conduction signal. When the conduction signal is enabled, the first transistor (130) discharges an electrostatic discharge current. When an electrostatic discharge event occurs on the first power line, the detection circuit enables a conduction signal. When the conduction signal is enabled, the second transistor (140) discharges an electrostatic discharge current. The first transistor includes a first base, a first gate, a first drain and a first source. The first gate receives the conduction signal. The first drain is coupled to a third power line. The first source and the first base are coupled to the second power line. The second transistor includes a second base, a second gate, a second drain and a second source. The second gate receives the conduction signal. The second drain is coupled to the first power line. The second source and the second base are coupled to the second power line. When the conduction signal is enabled, the first and second transistors are conducted to release an electrostatic discharge current.

In order to make the purpose, features and advantages of the present invention more comprehensible, the following specifically cites the embodiments, together with the accompanying drawings, for a detailed description. The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. Wherein, the arrangement of each element in the embodiment is for illustration, not for limiting the present invention. In addition, the partial repetition of the symbols in the figures in the embodiments is for the purpose of simplifying the description, and does not imply the relationship between different embodiments.

Figure 1 is a possible embodiment of the electrostatic discharge protection circuit of the present invention. As shown in the figure, the ESD protection circuit 100 includes a detection circuit 110 , a voltage dividing element 120 and a release element 130 . The detection circuit 110 is coupled between the power lines PL1 and PL2 and detects whether an electrostatic discharge event occurs. When an ESD event occurs, the detection circuit 110 enables a turn-on signal SON. If the ESD event does not occur, the detection circuit 110 cannot turn on the signal SON. In a possible embodiment, when no electrostatic discharge event occurs, the power line PL1 receives a low operating voltage VDD, and the power line PL2 receives a ground voltage VSS. In this example, the low operating voltage VDD is greater than the ground voltage VSS. In one possible embodiment, the low operating voltage VDD is about 5V, and the ground voltage VSS is about 0V.

The voltage dividing element 120 is coupled between the power lines PL1 and PL3 and receives the turn-on signal SON. In this embodiment, the voltage dividing element 120 is a bridge between the high operating voltage VCC and the low operating voltage VDD. For example, in a normal mode (ie, no ESD event), the power line PL1 receives a low operating voltage VDD, and the power line PL3 receives a high operating voltage VCC. In a possible embodiment, the low operating voltage VDD is smaller than the high operating voltage VCC. For example, the low operating voltage VDD is about 1.8V, 3.3V or 5V, and the high operating voltage VCC is about 30V. Since the voltage dividing element 120 is a high voltage element, it can withstand a high operating voltage VCC.

In this embodiment, the voltage dividing element 120 is a high voltage transistor HVN2. A gate 121 of the high voltage transistor HVN2 receives the turn-on signal SON. The drain 122 of the high voltage transistor HVN2 is coupled to the power line PL3. A source 123 of the high voltage transistor HVN2 is coupled to the power line PL1. A bulk 124 of the high voltage transistor HVN2 is coupled to the power line PL2.

The present invention does not limit the type of the high voltage transistor HVN2. In this embodiment, the high voltage transistor HVN2 is an N-type transistor, but it is not intended to limit the invention. In other embodiments, the high voltage transistor HVN2 is a P-type transistor. In some embodiments, the junction voltage between the drain 122 and the base 124 of the high voltage transistor HVN2 is higher than the junction voltage between the source 123 and the base 124 . In a possible embodiment, the drain of the high voltage transistor HVN2 is formed in a diffused region. Due to the low impurity concentration in the diffusion region, it can withstand high voltage. In a possible embodiment, the high voltage transistor HVN2 is a Lateral Diffused Metal-Oxide-Semiconductor Field-Effect Transistor (LDMOSFET) or a double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor. Transistor (Double Diffused Metal-Oxide-Semiconductor Field-Effect Transistor; DDMOSFET).

The release element 130 is coupled between the power lines PL2 and PL3. When the turn-on signal SON is enabled, the release element 130 releases an electrostatic discharge current. In this embodiment, the releasing element 130 is a high voltage transistor HVN1. The gate 131 of the high voltage transistor HVN1 receives the turn-on signal SON. The drain 132 of the high voltage transistor HVN1 is coupled to the power line PL3. The source 133 and the base 134 of the high voltage transistor HVN1 are coupled to the power line PL2. The present invention does not limit the type of the high voltage transistor HVN1. In this embodiment, the high voltage transistor HVN1 is an N-type transistor, but it is not intended to limit the invention. In other embodiments, the high voltage transistor HVN1 is a P-type transistor. In some embodiments, the junction voltage between the drain 132 and the base 134 of the high voltage transistor HVN1 is higher than the junction voltage between the source 133 and the base 134 . In a possible embodiment, the high voltage transistor HVN1 is an LDMOSFET or a DDMOSFET.

When an electrostatic discharge event occurs on the power line PL3 and the power line PL1 is at a floating level, since the high voltage transistor HVN2 is not completely closed, part of the electrostatic discharge current flows from the power line PL3 through the high voltage transistor HVN2 , into the detection circuit 110 . At this time, the detection circuit 110 is enabled to turn on the signal SON. Therefore, the high voltage transistor HVN1 is turned on. At this time, most of the electrostatic discharge current enters the power line PL2 from the power line PL3 through the high voltage transistor HVN1.

When the ESD event does not occur, the power lines PL1 and PL3 respectively receive a low operating voltage VDD and a high operating voltage VCC, and the power line PL2 receives a ground voltage VSS. At this time, the detection circuit 110 is disabled to turn on the signal SON. Therefore, neither the high voltage transistors HVN1 nor HVN2 are turned on. Since the high-voltage transistor HVN2 blocks the high operating voltage VCC from entering the detection circuit 110 , damage to components (such as transistors) in the detection circuit 110 can be prevented.

Fig. 2 is another embodiment of the electrostatic discharge protection circuit of the present invention. Figure 2 is similar to Figure 1, the difference is that there is an additional release element 140 in Figure 2 . The release element 140 is coupled between the power lines PL1 and PL2. When the turn-on signal SON is enabled, the release element 140 releases an electrostatic discharge current. In this embodiment, the releasing element 140 is a low voltage transistor LVN1. The gate 141 of the low-voltage transistor LVN1 receives the turn-on signal SON. The drain 142 of the low voltage transistor LVN1 is coupled to the power line PL1. The source 143 and the base 144 of the low voltage transistor LVN1 are coupled to the power line PL2.

The present invention does not limit the type of the low voltage transistor LVN1. In this embodiment, the low-voltage transistor LVN1 is an N-type transistor, but it is not intended to limit the invention. In other embodiments, the low voltage transistor LVN1 is a P-type transistor. In some embodiments, the junction voltage between the drain 122 and the base 124 of the high voltage transistor HVN2 is higher than the junction voltage between the drain 142 and the base 144 of the low voltage transistor LVN1 . In another possible embodiment, the junction voltage between the drain 132 and the base 134 of the high voltage transistor HVN1 is also higher than the junction voltage between the drain 142 and the base 144 of the low voltage transistor LVN1 . In a possible embodiment, the drain 142 and the source 143 of the low voltage transistor LVN1 are formed between the same well region (such as P well).

Fig. 3 is a possible schematic diagram of the detection circuit of the present invention. As shown in the figure, the detection circuit 110 includes a resistor R, a capacitor C, low voltage transistors LVP and LVN2. The resistor R is coupled between the power line PL1 and the node A. The capacitor C is coupled between the node A and the power line PL2. In other embodiments, the capacitor C is formed by a transistor. In this example, the gate of the transistor is coupled to the node A, and the drain, source and base of the transistor are all coupled to the power line PL2.

The gate 311 of the low voltage transistor LVP is coupled to the node A, the source 312 thereof is coupled to the power line PL1 , and the drain 313 thereof is coupled to the node B. The gate 315 of the transistor LVN2 is coupled to the node A, the source 317 thereof is coupled to the power line PL2 , and the drain 316 thereof is coupled to the node B. In this embodiment, both the low voltage transistors LVP and LVN2 are low voltage transistors. In a possible embodiment, the low voltage transistor LVP is a P-type transistor, and the transistor LVN2 is an N-type transistor. In this example, the low-voltage transistors LVP and LVN2 constitute an inverter for inverting the level of the node A. For example, when an ESD event occurs, the node A is at a low level. Therefore, node B is at a high level. When an ESD event does not occur, node A is at a high level. Therefore, node B is at a low level.

In this embodiment, the junction voltage between the source 312 and the base 314 of the low-voltage transistor LVP or the junction voltage between the drain 313 and the base 314 is smaller than that of the drain of the high-voltage transistor HVN2 The junction voltage between 122 and base 124. In this example, the junction voltage between the source 312 and the base 314 of the low voltage transistor LVP or the junction voltage between the drain 313 and the base 314 are smaller than the drain 132 of the high voltage transistor HVN1 The junction voltage with the base 134.

In another possible embodiment, the junction voltage between the drain 316 and the base 318 of the low voltage transistor LVN2 or the junction voltage between the source 317 and the base 318 is smaller than that of the high voltage transistor HVN2 The junction voltage between the drain 122 and the base 124 . In this example, the junction voltage between the drain 316 and the base 318 of the low voltage transistor LVN2 or the junction voltage between the source 317 and the base 318 are smaller than the drain 132 of the high voltage transistor HVN1 The junction voltage with the base 134.

Fig. 4 is a schematic diagram of the low voltage transistor of the present invention. As shown in the figure, the low voltage transistor 400 includes a well region 410 , doped regions 421 - 423 and a gate structure 424 . The doped regions 421 - 423 are disposed in the well region 410 . In this embodiment, the well region 410 and the doped region 421 have the first conductivity type, wherein the doping concentration of the doped region 421 is higher than that of the well region 410 . The doped regions 422 and 423 have the second conductivity type. In this embodiment, the junction voltage between the doped region 423 and the well region 410 is similar to the junction voltage between the doped region 422 and the well region 410 . In a possible embodiment, the first conductivity type is P-type, and the second conductivity type is N-type. A gate structure 424 is formed over the well region 410 .

In some embodiments, the doped region 421 is electrically connected to a base contact pad 431 . The doped region 422 is electrically connected to a source contact pad 432 . The gate structure 424 is electrically connected to a gate contact pad 433 . The doped region 423 is electrically connected to a drain contact pad 434 . In this example, the base contact pad 431 serves as the base of the transistor 400, the source contact pad 432 serves as the source of the transistor 400, the gate contact pad 433 serves as the gate of the transistor 400, and the drain contact pad 434 serves as the gate of the transistor 400. Drain of transistor 400 .

Fig. 5 is a schematic diagram of the high voltage transistor of the present invention. As shown in the figure, the high voltage transistor 500 includes a well region 510 , a diffusion region 520 , doped regions 531 - 533 and a gate structure 534 . The doped regions 531 and 532 are disposed in the well region 510 . In this embodiment, the well region 510 and the doped region 531 have the first conductivity type, wherein the doping concentration of the doped region 531 is higher than that of the well region 510 . The doped region 532 has a second conductivity type. The second conductivity type is relative to the first conductivity type. For example, when the first conductivity type is P type, the second conductivity type is N type.

The diffusion region 520 is disposed in the well region 510 . The doping region 533 is disposed in the diffusion region 520 . The diffusion region 520 and the doped region 533 have the second conductivity type, wherein the doping concentration of the diffusion region 520 is lower than that of the doping region 533 . In one possible embodiment, the diffusion region 520 is a high voltage N-type diffusion region (HVNDD). In this embodiment, the junction voltage between the diffusion region 520 and the well region 510 is higher than the junction voltage between the doped region 532 and the well region 510 . In a possible embodiment, the junction voltage between the doped region 532 and the well region 510 is similar to the junction voltage between the doped region 423 and the well region 410 and the doped region 422 and the well region 410 in FIG. 4 the junction voltage between them. In this embodiment, the gate structure 534 is formed above the well region 510 and overlaps part of the diffusion region 520 .

In some embodiments, the doped region 531 is electrically connected to a base contact pad 541 . The doped region 532 is electrically connected to a source contact pad 542 . The gate structure 534 is electrically connected to a gate contact pad 543 . The doped region 533 is electrically connected to a drain contact pad 544 . In this example, base contact pad 541 serves as the base of transistor 500, source contact pad 542 serves as the source of transistor 500, gate contact pad 543 serves as the gate of transistor 500, and drain contact pad 544 serves as the gate of transistor 500. Drain of transistor 500 .

Since the diffusion region 520 has a lower doping concentration, the junction voltage between the doped region 533 and the base 510 can be increased, so that the doped region 533 can withstand a high operating voltage (such as VCC). In FIG. 1 , when the high voltage transistor 500 is used as the voltage dividing element 120 , it can not only withstand the high operating voltage VCC, but also prevent the components inside the detection circuit 110 from being damaged by the high operating voltage VCC.

It should be understood that when an element or layer is referred to as being "coupled" to another element or layer, it can be directly coupled or connected to the other element or layer or have the other element or layer interposed. Conversely, when an element or layer is "connected" to other elements or layers, there will be no intervening elements or layers.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be understood by those of ordinary skill in the art to which this invention belongs. In addition, unless expressly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice. Although terms such as 'first' and 'second' may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device or method described in the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

100: Electrostatic discharge protection circuit 110: detection circuit 120: Voltage divider element 130, 140: release element PL1~PL3: Power cord SON: ON signal VDD: Low operating voltage VCC: High operating voltage VSS: ground voltage HVN1, HVN2, 500: High voltage transistor LVP, LVN1, LVN2, 400: low voltage transistor 121, 131, 141, 311, 315: gate 122, 132, 142, 313, 316: drain 123, 133, 143, 312, 317: source 124, 134, 144, 314, 318: base R: resistance C: Capacitance A, B: node 410, 510, 520: well area 421~423, 531~533: doping area 424, 534: gate structure 431~434, 541~544: contact pad

Figure 1 is a possible embodiment of the electrostatic discharge protection circuit of the present invention. Fig. 2 is another embodiment of the electrostatic discharge protection circuit of the present invention. Fig. 3 is a possible schematic diagram of the detection circuit of the present invention. Fig. 4 is a schematic diagram of the low voltage transistor of the present invention. Fig. 5 is a schematic diagram of the high voltage transistor of the present invention.

100: Electrostatic discharge protection circuit

110: detection circuit

120: Voltage divider element

130: release element

PL1~PL3: Power cord

SON: ON signal

VDD: Low operating voltage

VCC: High operating voltage

VSS: ground voltage

HVN1, HVN2: high voltage transistor

121, 131: gate

122, 132: drain

123, 133: source

124, 134: base

Claims (16)

An electrostatic discharge protection circuit, comprising: a detection circuit coupled between a first power line and a second power line, enabling a conduction signal when an electrostatic discharge event occurs; a voltage divider, coupled between the first power line and a third power line, and receive the conduction signal; and a first release element, coupled between the second and third power lines, when the conduction signal When enabled, an electrostatic discharge current is released; wherein when the electrostatic discharge event does not occur, the first power line receives a first voltage, the second power line receives a second voltage, and the third power line receives a A third voltage, the first voltage is greater than the second voltage, the third voltage is greater than the first voltage. The electrostatic discharge protection circuit according to claim 1, wherein the first release element includes a first transistor, the gate of the first transistor receives the conduction signal, and the drain of the first transistor is coupled to the third A power line, the source and base of the first transistor are coupled to the second power line. The electrostatic discharge protection circuit according to claim 2, wherein the voltage dividing element includes a second transistor, the gate of the second transistor receives the conduction signal, and the drain of the second transistor is coupled to the third power supply line, the source of the second transistor is coupled to the first power line, and the base of the second transistor is coupled to the second power line. The electrostatic discharge protection circuit according to claim 3, wherein the first and second transistors are both laterally diffused transistors. The electrostatic discharge protection circuit according to claim 2, wherein the detection circuit includes: a resistor, coupled between the first power line and a first node; a capacitor, coupled between the first node and the second power line; a third transistor, the gate of which is coupled to the A first node, its source is coupled to the first power line, its drain is coupled to a second node; and a fourth transistor, its gate is coupled to the first node, its source is coupled to the second A power line, the drain of which is coupled to the second node; wherein the junction voltage between the drain and base of the third transistor is lower than the junction voltage between the drain and base of the first transistor. The electrostatic discharge protection circuit according to claim 1 further includes: a second discharge element coupled between the first and second power lines, and discharges the electrostatic discharge current when the conduction signal is enabled. The electrostatic discharge protection circuit according to claim 6, wherein: the first release element includes a first transistor, the gate of the first transistor receives the conduction signal, and the drain of the first transistor is coupled to the first transistor three power lines, the source and base of the first transistor are coupled to the second power line; and the second release element includes a second transistor, the gate of the second transistor receives the conduction signal, The drain of the second transistor is coupled to the first power line, and the source and base of the second transistor are coupled to the second power line. The electrostatic discharge protection circuit according to claim 7, wherein the junction voltage between the drain and base of the second transistor is lower than the junction voltage between the drain and base of the first transistor. The electrostatic discharge protection circuit according to claim 1, wherein when the electrostatic discharge event occurs on the third power line, part of the electrostatic discharge current enters the detection circuit through the voltage dividing element, so that the detection circuit enables the conduction signal . An electrostatic discharge protection circuit, comprising: a detection circuit coupled between a first power line and a second power line, enabling a conduction signal when an electrostatic discharge event occurs; a first transistor , including a first base, a first gate, a first drain and a first source, the first gate receives the conduction signal, the first drain is coupled to a third power line, The first source is coupled to the second power line; and a second transistor includes a second base, a second gate, a second drain and a second source, the second gate receives The conduction signal, the second drain is coupled to the third power line, and the second source is coupled to the first power line; wherein: when the conduction signal is enabled, the first and second power The crystal is turned on to release an electrostatic discharge current; the junction voltage between the first drain and the first base is higher than the junction voltage between the first source and the first base; the first The junction voltage between the second drain and the second base is higher than the junction voltage between the second source and the second base. Such as the electrostatic discharge protection circuit of claim 10, further comprising: a third transistor, including a third base, a third gate, a third drain and a third source, the third gate receives The conduction signal, the third drain is coupled to the first power line, the third source and the third base are coupled to the second power line; wherein: when the conduction signal is enabled, the first The tri-transistor is turned on to discharge the electrostatic discharge current. The electrostatic discharge protection circuit according to claim 11, wherein the first drain The junction voltage between the first base and the third drain is higher than the junction voltage between the third drain and the third base, and the junction voltage between the second drain and the second base is higher The junction voltage between the third drain and the third base. The electrostatic discharge protection circuit according to claim 10, wherein the detection circuit includes: a resistor coupled between the first power line and a first node; a capacitor coupled between the first node and the second Between the power lines; a fourth transistor, including a fourth base, a fourth gate, a fourth drain and a fourth source, the fourth gate is coupled to the first node, the first Four sources are coupled to the first power line, the fourth drain is coupled to a second node; and a fifth transistor includes a fifth base, a fifth gate, a fifth drain and a fifth transistor. a fifth source, the fifth gate is coupled to the first node, the fifth source is coupled to the second power line, and the fifth drain is coupled to the second node; wherein: the first drain and The junction voltage between the first base is higher than the junction voltage between the fourth drain and the fourth base; the junction voltage between the first drain and the first base is higher than The junction voltage between the fifth drain and the fifth base. The electrostatic discharge protection circuit according to claim 13, wherein the first, second, third and fifth transistors are N-type transistors, and the fourth transistor is a P-type transistor. The electrostatic discharge protection circuit according to claim 10, wherein the second base is coupled to the second power line. The electrostatic discharge protection circuit according to claim 10, wherein when the electrostatic discharge event does not occur, the first power line receives a first voltage, and the second power line receives A second voltage, the third power line receives a third voltage, the first voltage is greater than the second voltage, the third voltage is greater than the first voltage.

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