201042748 六、發明說明： 【發明所屬之技術領域】 本發明係有關於靜電放電防護電路，特別有關於可節省面積以 及防止漏電流的靜電放電防護電路。 【先前技術】 第1圖緣不了習知技術之靜電放電保護（ESDpr〇tec㈣電路 娜。如第1圖所示，習知技術之靜電放電防護電路_▼包含靜電 放電保護元件m、1G3，觸發電路1G7、⑽以及靜電放電偵測電 路⑴’其主要目的在於避免靜電放電電壓產生時，直接由輸入/輸 出墊m傳入内部電路⑽而造成内部電路奶的損壞。靜電放電 防護電路⑽之動作原理可簡述如下：當舰放電偵測電路⑴偵 測到靜電放電電壓產生時’會產生—控制訊號來控綱發電路贿 和:而觸發電路107和109會觸發靜電放電保護元件HH或103, 使付靜電放電保心件1G1或1G3可將靜電放電電流導引出去，達 到保護内部電路1〇5的目的。 —細，觸發電路107通常會佔據相當大的面積，而在此結構下， 每/靜電放電防7〇件皆雜配—觸發電路。目此觸發電路會佔據 相當大的面積。除此之外，為了降低晶片的複雜度和製造成本，靜 201042748 電放電偵測電路以及觸發電路通常會以具有薄氧化層的元件來實 • 施。如此一來，可能會有漏電流iLeA沿著第1圖所示的路徑流至電 壓vss而造成靜電防護電路中的電容之跨壓不足，而影響到靜電防 護電路中的作用。而當内部電路105在正常運作時，漏電流則會造 成額外的功率消耗。 【發明内容】 Ο 本發明之一目的在於提供一種可節省觸發電路面積的靜電放電 • 防護電路。 本發明之另一目的在於提供一種可減少漏電流的靜電放電防護 電路。 本發明之一實施例揭露了一種靜電放電防護電路，其包含一靜 〇 電放電偵測電路、一第一類型靜電放電保護元件、一第二類型靜電 放電保護元件以及一觸發電路。靜電放電偵測電路用以偵測—靜電 放電電壓來產生一控制訊號。第一類型靜電放電保護元件用以輪出 一第一觸發電流。第二類型靜電放電保護元件用以接收一第二觸發 電流。觸發電路用以根據控制訊號形成一導通路徑，以自第一類型 靜電放電保§蔓元件接收該第一觸發電流，並輸出第二觸發電流至兮 ， 第二類型靜電放電保護元件。 Λ 201042748 此外，靜電放電防護電路可更包含一第一開關以及一第二開 ，關’第一開關根據控制訊號來決定是否導通第一類型靜電放電保護 元件和第二類型靜電放電保護元件，第二開關根據控制訊號來決定 是否讓第一電壓位準、第二電壓位準以及靜電故電偵測電路形成一 導通路徑。 根據上述之實施例，根據本發明之實施例的靜電放電防護電路 〇 可節省觸發電路之面積，更可提供降低漏電流之結構。因此可改善 習知技術之靜電放電防護電路的問題。 【實施方式】 在說明書及後續的申請專利範圍當中使用了某些詞彙 來才曰稱特疋的元件。所屬領域中具有通常知識者應可理解， D 硬體製造商可能會用不同的名詞來稱呼同一個元件。本說明 書及後續的申請專利範圍並不以名稱的差異來作為區分元 件的方式，而是以元件在功能上的差異來作為區分的準則。 在通篇說明書及後續的請求項當中所提及的「包含」係為一 開放式的用語，故應解釋成「包含但不限定於」。以外，「耦 接」一詞在此係包含任何直接及間接的電氣連接手段。因 此，若文中彳田述一第一裝置耦接於一第二裝置，則代表該第 一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連 接手段間接地電氣連接至該第二裝置。 201042748 第2圖繪示了根據本發明之實施例的可節省觸發電路面積之靜 1 電放電防護電路200。在此實施例中，係以N型矽控整流器和p型 矽控整流器來實施靜電放電保護元件，但並非用以限定本發明。如 第2圖所示，靜電放電防護電路200包含一 N型石夕控整流器2〇1、 一 P型矽控整流器203、一觸發電路205以及一靜電放電偵測電路 207。請注意為了方便說明’第1圖中所述的内部電路予以省略不表 〇 示。靜電放電偵測電路207用以偵測一靜電放電電壓來產生一控制 訊號CS。N型石夕控整流器201用以輸出一第一觸發電流Itril ; N型 • 矽控整流器201經由此第一觸發電流Itril之觸發即可在其兩端間（也 就是供應電位VDD與輸入/輸出墊208之間）導通一導通路徑。p型 矽控整流器203用以接收一第二觸發電流1说；經由此第二觸發電流 之觸發，P型矽控整流器203可在其兩端間（也就是輸入/輸出墊2〇8 與地電位Vss之間）導通一導通路徑。觸發電路2〇5用以根據控制 ^ 訊號CS形成一導通路徑’以自N型矽控整流器201接收第一觸發 電流Itrii ’並輸出第二觸發電流1尬至P型矽控整流器2〇3。在一實 施例中，第一觸發電流1如以及第二觸發電流14^具有相同的電流 值；換句話說，在本發明的一實施例中，觸發電路2〇5即可將矽控 整流器201之觸發電流傳輸至另一矽控整流器2〇3，以單一觸發電 路205來觸發兩個石夕控整流器。在此架構下，僅需要一個觸發電路 便可觸發一個以上的靜電放電保護元件，此機制稱為合併觸發機 制，可節省觸發電路所佔的面積。第一觸發電流Itrii以及第二觸發 電流Itri2之電流值可隨矽控整流器所須的觸發電流之不同而被調整 7 201042748 成其他值；基本上，矽控整流器201及203可以有不同的臨限導通 ， 電流’而觸發電路205只要能將足夠大的電流（譬如說，大於矽控 整流器201及203之臨限電流）由矽控整流器2〇1汲取並傳輸至另 一矽控整流器203，即可一併觸發兩者。而且，在第2圖所繪示的 方塊圖中’觸發電路205未搞接至供應電位VDD和地電位Vss，然 而觸發電路205亦可耦接至供應電位Vdd和地電位Vss。另外，觸 發電路205及靜電放電偵測電路2〇7可整合至一複合電路2〇9中。 〇 第3、4圖分別繪示了第2圖所示之靜電放電防護電路的詳細結 構之其中一例。在第3圖所示的實施例中，靜電放電偵測電路207 具有電阻301和電容303。第3圖中的觸發電路205包含一第一 NMOS 305以及一反相器307。第一 NMOS 305具有耦接於N型矽 控整流器201的一汲極以及耦接於P型矽控整流器203的一源極。 反相器307具有耦接於第一 NMOS 305之一閘極的一輸出端’且具 q 有耦接於電阻301之第二端的一輸入端。 供應電位VDD和地電位vss係作為反相器307的供應電壓。正 常情況下供應電位VDD會對電容303進行充電，因此A點之電壓準 位為HIGH而B點之電壓準位為LOW，第一 NMOS 305會呈現不 . 導通的狀態。相反的，當靜電放電電壓產生時，由於電容303無法 ， 快速的進行充電，因此A點之電壓準位為LOW而B點之電壓準位 為HIGH’第一 NMOS 305會呈現導通的狀態。N型矽控整流器201 和P型矽控整流器203會分別因接收負電流和正電流而被觸發導 8 201042748 通，觸發形成的導通路徑即可將靜電放電電流導出’因此可避免靜 電放電電流傷害内部電路。201042748 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an electrostatic discharge protection circuit, and more particularly to an electrostatic discharge protection circuit that can save area and prevent leakage current. [Prior Art] The first picture does not have the electrostatic discharge protection of the prior art (ESDpr〇tec (4) circuit Na. As shown in Fig. 1, the conventional electrostatic discharge protection circuit _▼ contains the electrostatic discharge protection element m, 1G3, trigger The main purpose of the circuits 1G7, (10) and the electrostatic discharge detecting circuit (1)' is to prevent the internal circuit milk from being directly damaged by the input/output pad m when the electrostatic discharge voltage is generated. The action of the electrostatic discharge protection circuit (10) The principle can be briefly described as follows: When the ship discharge detection circuit (1) detects the generation of the ESD voltage, it will generate a control signal to control the circuit and bribes: and the trigger circuits 107 and 109 will trigger the ESD protection component HH or 103. The electrostatic discharge current protection 1G1 or 1G3 can guide the electrostatic discharge current out to protect the internal circuit 1〇5. - Fine, the trigger circuit 107 usually occupies a relatively large area, and under this structure, Every / ESD protection is a miscellaneous - trigger circuit. The trigger circuit will occupy a considerable area. In addition, in order to reduce the complexity and system of the chip Cost, static 201042748 The electric discharge detection circuit and the trigger circuit are usually implemented with components with a thin oxide layer. As a result, leakage current iLeA may flow along the path shown in Figure 1 to the voltage vss. The voltage across the capacitor in the ESD protection circuit is insufficient, which affects the role in the ESD protection circuit. When the internal circuit 105 is in normal operation, the leakage current causes additional power consumption. [Abstract] The present invention An object of the present invention is to provide an electrostatic discharge protection circuit capable of reducing the area of a trigger circuit. Another object of the present invention is to provide an electrostatic discharge protection circuit capable of reducing leakage current. One embodiment of the present invention discloses an electrostatic discharge protection circuit. The utility model comprises a static electric discharge detecting circuit, a first type electrostatic discharge protection component, a second type electrostatic discharge protection component and a trigger circuit. The electrostatic discharge detecting circuit detects the electrostatic discharge voltage to generate a control. Signal. The first type of electrostatic discharge protection element is used to rotate a first trigger current. The second type of static The electric discharge protection component is configured to receive a second trigger current. The trigger circuit is configured to form a conduction path according to the control signal, to receive the first trigger current from the first type of electrostatic discharge protection component, and output the second trigger current to兮, the second type of electrostatic discharge protection component. Λ 201042748 In addition, the electrostatic discharge protection circuit may further include a first switch and a second switch, the first switch determines whether to conduct the first type of electrostatic discharge protection component according to the control signal. And the second type of electrostatic discharge protection component, the second switch determines whether to make the first voltage level, the second voltage level, and the static electricity detecting circuit form a conduction path according to the control signal. According to the embodiment, according to the embodiment The electrostatic discharge protection circuit of the embodiment of the invention can save the area of the trigger circuit, and can further provide a structure for reducing leakage current. Therefore, the problem of the electrostatic discharge protection circuit of the prior art can be improved. [Embodiment] Some terms are used in the specification and the subsequent patent application to nickname a special component. It should be understood by those of ordinary skill in the art that a D hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application does not use the difference in name as the means of distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if the first device in the text is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. Device. 201042748 FIG. 2 illustrates a static 1 electric discharge protection circuit 200 that can save the area of the trigger circuit in accordance with an embodiment of the present invention. In this embodiment, the electrostatic discharge protection element is implemented with an N-type 矽-controlled rectifier and a p-type 矽-controlled rectifier, but is not intended to limit the invention. As shown in FIG. 2, the ESD protection circuit 200 includes an N-type Xi-controlled rectifier 2〇1, a P-type 矽-controlled rectifier 203, a trigger circuit 205, and an ESD detection circuit 207. Please note that the internal circuits described in Figure 1 are omitted for convenience of explanation. The ESD detecting circuit 207 is configured to detect an ESD voltage to generate a control signal CS. The N-type sigma rectifier rectifier 201 is configured to output a first trigger current Itril; the N-type 矽-controlled rectifier 201 can be triggered between the two ends (ie, the supply potential VDD and the input/output) via the triggering current Itril Between the pads 208) a conduction path is conducted. The p-type pilot rectifier 203 is configured to receive a second trigger current 1; via the triggering of the second trigger current, the P-type pilot rectifier 203 can be between the two ends thereof (ie, the input/output pad 2〇8 and the ground) A potential path is turned on between the potentials Vss. The trigger circuit 2〇5 is configured to form a conduction path ′ according to the control signal CS to receive the first trigger current Itrii′ from the N-type controlled rectifier 201 and output the second trigger current 1尬 to the P-type controlled rectifier 2〇3. In an embodiment, the first trigger current 1 and the second trigger current 14^ have the same current value; in other words, in an embodiment of the invention, the trigger circuit 2〇5 can control the rectifier 201 The trigger current is transmitted to another step-controlled rectifier 2〇3, and a single trigger circuit 205 is used to trigger two rock-controlled rectifiers. In this architecture, only one trigger circuit is required to trigger more than one ESD protection component. This mechanism is called a combined trigger mechanism, which saves the area occupied by the trigger circuit. The current values of the first trigger current Itrii and the second trigger current Itri2 can be adjusted according to the trigger current required by the step-controlled rectifier. 7 201042748 becomes other values; basically, the step-controlled rectifiers 201 and 203 can have different thresholds. Turning on, current' and trigger circuit 205 is capable of drawing a sufficiently large current (for example, a threshold current greater than that of step-controlled rectifiers 201 and 203) from the controlled rectifier 2〇1 and transmitting it to another step-controlled rectifier 203, ie Both can be triggered together. Further, in the block diagram shown in Fig. 2, the flip-flop circuit 205 is not connected to the supply potential VDD and the ground potential Vss, but the flip-flop circuit 205 can also be coupled to the supply potential Vdd and the ground potential Vss. In addition, the trigger circuit 205 and the electrostatic discharge detecting circuit 2〇7 can be integrated into a composite circuit 2〇9. 〇 Figures 3 and 4 show an example of the detailed structure of the ESD protection circuit shown in Figure 2, respectively. In the embodiment shown in FIG. 3, the electrostatic discharge detecting circuit 207 has a resistor 301 and a capacitor 303. The flip-flop circuit 205 in FIG. 3 includes a first NMOS 305 and an inverter 307. The first NMOS 305 has a drain coupled to the N-type PWM rectifier 201 and a source coupled to the P-type PWM rectifier 203. The inverter 307 has an output terminal coupled to one of the gates of the first NMOS 305 and has an input coupled to the second terminal of the resistor 301. The supply potential VDD and the ground potential vss are used as the supply voltage of the inverter 307. Normally, the supply potential VDD charges the capacitor 303. Therefore, the voltage level at point A is HIGH and the voltage level at point B is LOW, and the first NMOS 305 is in a non-conducting state. Conversely, when the electrostatic discharge voltage is generated, since the capacitor 303 cannot be charged quickly, the voltage level at point A is LOW and the voltage level at point B is HIGH'. The first NMOS 305 is in an on state. The N-type 矽-controlled rectifier 201 and the P-type 矽-controlled rectifier 203 are respectively triggered by the negative current and the positive current, and the conduction path is triggered to lead the electrostatic discharge current. Therefore, the electrostatic discharge current can be prevented from harming the internal Circuit.
在第4圖中，靜電放電偵測電路207亦具有電阻401和電容 403，但其位置和第3圖的電阻301和電容303相反。此外，第3 圖的第一 NMOS 305由第一 PMOS 405所取代。在第4圖所示的例 子中’正常情況下供應電位VDD會對電容403進行充電，A點的電 〇 壓準位會呈現LOW’B點的電壓準位會呈現HIGH，因此第一 PMOS 405會呈現不導通的狀態。相反的，當靜電放電電壓產生時，A點 之電壓準位為HIGH而B點之電壓準位為LOW，因此第一 PMOS 405會呈現導通的狀態。n型矽控整流器2〇1和p型矽控整流器2〇3 會刀別因接收負電流和正電流而被觸發，觸發後會將靜電放電電流 導出，因此可避免靜電放電電流傷害内部電路。 〇 。第5圖至第7眺不了根據本發明的實施例之可防止漏電流的 靜電放電防護電路之詳細結構。相較於第2圖至第4圖所示的實施 =5圖至第7圖所示的實施例除了具有第2圖至第4圖所示的 =Γ面積之結構外’更包含了可防止漏電流的結構。且在 人電路電路和觸發電路可更整合成一複 能，且具有防止漏電流之結^ = _電路和觸發電路之功 相較於㈣，複合電路5(^^所示綱放電防護電路 觸S305以及反相器3〇7外=電_、電容舶、第- 尺已含了一第二NMOS503。因此 9 201042748 當第一 NMOS305不導通時，第二nm〇s5〇3亦不導通，故可防止 漏電流的產生。譬如說’在正常情況下進行正常運作時，停止導通 的第二NMOS 503會切斷電容3〇3往地電位Vss的漏電路徑’防止 漏電流持續導通而消耗功率。同樣的，第5(b)圖所示的靜電放電防 護電路500相較於第4圖，複合電路504更包含了 一第二PMOS 505 ’因此當第一 PMOS405不導通時，第二PMOS 505亦不導通， 故可防止漏電流的產生。 ❹ 第5(a)和第5(b)圖所示之實施例的概念可如下所示：靜電放電 防護電路包含一第一開關(第一 NMOS 305或第一 PMOS 405)以及 一第二開關(第二NMOS 503或第二PMOS 505)，第一開關根據該控 制訊號來決定是否導通第一類型靜電放電保護元件型矽控整流 器201)和第二類型靜電放電保護元件(ρ型矽控整流器2〇3)，第二開 關根據控制訊號來決定是否讓第一電壓位準(如供應電位Vdd)、第 Q 二電壓位準（如地電位Vss)以及靜電放電偵測電路形成一導通路 徑。 第6圖至第7圖繪示了根據本發明的實施例之可防止漏電流的 靜電放電防護電路之詳細結構。靜電放電防護電路6⑻和7〇〇之共 通概念在於，降低複合電路電容之跨壓，藉以改善漏電流之現象。 在第6圖所示的靜電放電防護電路6〇〇中，複合電路6〇ι包含一第 一 PMOS 603、一第一 NMOS 605、一第一電阻 607、一電容 6〇9、 一第二電阻 611、一第二 PMOS613、一第二NMOS615 以及一第 201042748 三NMOS 617。第- PMOS 603具有祕至供應電位Vdd的一源極， 、以及搞接至N型梦控整流器201的一閘極。第-NM0S 605具有搞 接至N型矽控整流器201的一閘極，以及耦接至第一 pM〇s6〇3之 一沒極的一汲極。第一電阻607具有耦接至第一刪〇$ 6〇5的一源 極之一第一端以及耦接至地電位vss之一第二端。第二PMOS613 具有搞接至供應電位VDD之一源極以及耦接至第一 pM〇s 6〇3之一 汲極的一閘極、以及耦接至N型矽控整流器201之一汲極。第二 〇 NM0S 615具有麵接至第二PM0S 613之汲極的一汲極以及耦接至 第一 PM0S 603之汲極的一閘極。電容6〇9具有耦接至第二NM〇s 615之閘極的一第一端。第三nm〇S617具有耦接至第：nm〇s6i5 之一源極的一汲極、耦接至電容之一第二端的一閘極、以及耦接至 P型石夕控整流器203之一源極。第二電阻611具有輕接至第三nm〇s 617之閘極的一第一端以及耦接至地電位vss之一第二端。 》 第6圖所示的靜電放電防護電路6〇〇之動作可簡述如下：在正 常運作時，第二PM0S 613會導通而使B點的電壓位準為， 而藉由回授機制，A點的電壓位準會被拉低至low，如此一來，電 谷609兩端之跨壓減少，並可有效地關閉第二nm〇s 615與第三 NM0S 617，因此，漏電路徑便會被截斷而降低漏電流的情形。 第7圖所示的靜電放電防護電路700之動作概念和靜電放電防 護電路600類似’但靜電放電防護電路700以兩個PM0S和一個 NM0S取代了靜電放電防護電路600的兩個NM0S和一個PMOS。 201042748 而且複合電路中的電阻和電容之位置有所不同。靜電放電偵測電路 700中的複合電路701包含：一第一 pm〇S 703、一第一 NMOS 705、 一第一電阻707、一電容709、一第二電阻711、一第二PMOS713、 一第二 PMOS715 以及一第二nm〇S717。第一 pm〇S703 具有耦 接至P型砂控整流器203的一閘極。第一 nm〇S 705具有輕接至P 型矽控整流器203的一閘極，耦接至第一 PM〇S7〇3之一汲極的一 汲極、以及耦接至地電位VSS的一源極。第一電阻707具有耦接至 〇 供應電位VDD之一第一端以及第一 pm〇s 705之一源極的一第二 端。 第一電阻711具有搞接至供應電位vDD的一第一端。第二pm〇s 713具有耦接至N型矽控整流器203之一源極，以及耦接至第二電 阻711之一第二端的一閘極。電容7〇9具有耦接至第二pM〇S713 之閘極的一第一端，以及耦接至第—NM〇S 7〇5之汲極之一第二 〇 端。第三PM0S爪具有耦接至第二PMOS 713之一汲極的一源極， 麵接至電容709之第二端的一閘極’以及麵接至p型石夕控整流器203 的一汲極。第二NMOS 717具有耦接至P型矽控整流器2〇3之一汲 極、耦接至電容709之第二端之一閘極，以及耦接地電位vss之一 源極。 第7圖所示的靜電放電防護電路700之動作可簡述如下：在正 常運作時’第二NMOS 717會導通而使B點的電壓·位準為LOW， 而藉由回授機制，電容709耦接至第一 NMOS 705之汲極之第二端 12 201042748 的電壓位準會被拉高至HIGH，如此一來，電容709兩端之跨壓減 • 少，並可有效地關閉第三PMOS715與第二PMOS713，因此，漏 電路徑便會被截斷而降低漏電流的情形。 根據上述之實施例，根據本發明之實施例的靜電放電防護電路 可節省觸發電路之面積，更可提供降低漏電流之結構。因此可改善 習知技術之靜電放電防護電路的問題。 〇 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖繪示了習知技術之靜電放電防護電路。 〇 第2圖緣示了根據本翻之實施_可節拥發電路面積之靜 電放電防護電路。 、，第3圖和第4圖分別输示了第2圖所示之靜電放電防護電路的 詳細結構之其中一例。 第5圖至第7崎示了根據本發_實施例之可防止漏電流的 .靜電放電防護電路之詳細結構。 【主要元件符號說明】 13 201042748 200、300、400、402、500、502、600、700 靜電放電防護電路 201 N型矽控整流器 203 P型矽控整流器 205觸發電路 207靜電放電偵測電路 208輸入/輸出墊 〇 301、401 電阻 303、403、609、709 電容 307反相器In Fig. 4, the electrostatic discharge detecting circuit 207 also has a resistor 401 and a capacitor 403, but its position is opposite to that of the resistor 301 and the capacitor 303 of Fig. 3. Further, the first NMOS 305 of FIG. 3 is replaced by the first PMOS 405. In the example shown in Figure 4, the supply potential VDD will charge the capacitor 403 under normal conditions, and the voltage level at point A will exhibit a voltage level of LOW'B point, which will be HIGH, so the first PMOS 405 Will be in a non-conducting state. Conversely, when the ESD voltage is generated, the voltage level at point A is HIGH and the voltage level at point B is LOW, so the first PMOS 405 will be in an on state. The n-type 矽-controlled rectifier 2〇1 and the p-type 矽-controlled rectifier 2〇3 will be triggered by receiving negative current and positive current. After the trigger, the electrostatic discharge current will be derived, thus avoiding the electrostatic discharge current from damaging the internal circuit. Oh. 5 to 7 show a detailed structure of an electrostatic discharge protection circuit capable of preventing leakage current according to an embodiment of the present invention. Compared with the embodiment shown in FIGS. 2 to 4, the embodiment shown in FIG. 5 to FIG. 7 has a structure other than the structure of the area shown in FIG. 2 to FIG. The structure of the leakage current. And in the human circuit circuit and the trigger circuit can be more integrated into a complex energy, and has a function of preventing leakage current ^ = _ circuit and the function of the trigger circuit compared with (4), the composite circuit 5 (^^ indicates that the discharge protection circuit touches S305 And the inverter 3〇7=electric_, capacitor, and the first ruler already contain a second NMOS 503. Therefore 9 201042748 When the first NMOS 305 is not turned on, the second nm 〇s5〇3 is not turned on, so Prevent leakage current. For example, 'When normal operation is performed under normal conditions, the second NMOS 503 that stops conducting will cut off the leakage path of the capacitor 3〇3 to the ground potential Vss' to prevent the leakage current from continuing to conduct and consume power. Similarly, in the electrostatic discharge protection circuit 500 shown in FIG. 5(b), the composite circuit 504 further includes a second PMOS 505 ′. Therefore, when the first PMOS 405 is not turned on, the second PMOS 505 is also It is not conductive, so leakage current can be prevented. 概念 The concepts of the embodiments shown in Figures 5(a) and 5(b) can be as follows: The ESD protection circuit includes a first switch (first NMOS 305) Or a first PMOS 405) and a second switch (a second NMOS 503 or a second PM) OS 505), the first switch determines whether to turn on the first type electrostatic discharge protection element type controlled rectifier 201) and the second type electrostatic discharge protection element (p type controlled rectifier 2〇3) according to the control signal, and the second switch According to the control signal, whether to make the first voltage level (such as the supply potential Vdd), the Qth voltage level (such as the ground potential Vss), and the electrostatic discharge detecting circuit form a conduction path. 6 to 7 illustrate the detailed structure of an electrostatic discharge protection circuit capable of preventing leakage current according to an embodiment of the present invention. The common concept of the ESD protection circuit 6(8) and 7〇〇 is to reduce the cross-over voltage of the composite circuit capacitor, thereby improving the leakage current. In the ESD protection circuit 6A shown in FIG. 6, the composite circuit 6〇1 includes a first PMOS 603, a first NMOS 605, a first resistor 607, a capacitor 6〇9, and a second resistor. 611, a second PMOS 613, a second NMOS 615, and a 201042748 triple NMOS 617. The first PMOS 603 has a source that is secret to the supply potential Vdd, and a gate that is connected to the N-type sleep control rectifier 201. The first-NM0S 605 has a gate connected to the N-type pilot rectifier 201, and a gate coupled to one of the first pM〇s6〇3. The first resistor 607 has a first end of a source coupled to the first erased $6〇5 and a second end coupled to one of the ground potential vss. The second PMOS 613 has a gate connected to one of the supply potential VDD and a gate coupled to one of the first pM〇s 6〇3, and a drain coupled to one of the N-type controlled rectifiers 201. The second NMOS NM0S 615 has a drain connected to the drain of the second PMOS 613 and a gate coupled to the drain of the first PMOS 603. The capacitor 6〇9 has a first end coupled to the gate of the second NM〇s 615. The third nm 〇S617 has a drain coupled to one of the sources of the :nm〇s6i5, a gate coupled to the second end of the capacitor, and a source coupled to the P-type Xi-controlled rectifier 203 pole. The second resistor 611 has a first end that is connected to the gate of the third nm 〇 s 617 and a second end that is coupled to the ground potential vss. The action of the ESD protection circuit 6 shown in Figure 6 can be briefly described as follows: In normal operation, the second PMOS 613 will be turned on and the voltage level of point B will be, and by the feedback mechanism, A The voltage level of the point is pulled down to low, so that the voltage across the valley 609 is reduced, and the second nm 〇 s 615 and the third NM0S 617 are effectively turned off, so that the leakage path is Cut off and reduce leakage current. The action concept of the ESD protection circuit 700 shown in Fig. 7 is similar to that of the ESD protection circuit 600. However, the ESD protection circuit 700 replaces the two NMOSs and one PMOS of the ESD protection circuit 600 with two PMOSs and one NMOS. 201042748 And the position of the resistors and capacitors in the composite circuit is different. The composite circuit 701 in the ESD detection circuit 700 includes: a first pm 〇 S 703, a first NMOS 705, a first resistor 707, a capacitor 709, a second resistor 711, a second PMOS 713, and a first Two PMOS 715 and one second nm 〇 S717. The first pm 〇 S 703 has a gate coupled to the P-type sand control rectifier 203. The first nm〇S 705 has a gate connected to the P-type pilot rectifier 203, a drain coupled to one of the first PM〇S7〇3, and a source coupled to the ground potential VSS. pole. The first resistor 707 has a second end coupled to one of the first end of the supply potential VDD and one source of the first pm〇s 705. The first resistor 711 has a first end that is connected to the supply potential vDD. The second pm s 713 has a source coupled to one of the N-type pilot rectifiers 203 and a gate coupled to the second terminal of the second resistor 711. The capacitor 7〇9 has a first end coupled to the gate of the second pM〇S713, and a second end coupled to one of the drains of the first—NM〇S 7〇5. The third PMOS pad has a source coupled to one of the drains of the second PMOS 713, a gate connected to the second end of the capacitor 709, and a drain connected to the p-type XiCheng rectifier 203. The second NMOS 717 has a gate coupled to one of the P-type pilot rectifiers 2〇3, a gate coupled to the second terminal of the capacitor 709, and one source coupled to the ground potential vss. The operation of the ESD protection circuit 700 shown in FIG. 7 can be briefly described as follows: during normal operation, the second NMOS 717 is turned on and the voltage level of the B point is LOW, and by the feedback mechanism, the capacitor 709 The voltage level of the second terminal 12 201042748 coupled to the drain of the first NMOS 705 is pulled high to HIGH, so that the voltage across the capacitor 709 is reduced, and the third PMOS 715 can be effectively turned off. With the second PMOS 713, therefore, the leakage path is cut off to reduce the leakage current. According to the above embodiments, the electrostatic discharge protection circuit according to the embodiment of the present invention can save the area of the flip-flop circuit and can provide a structure for reducing the leakage current. Therefore, the problem of the electrostatic discharge protection circuit of the prior art can be improved. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an electrostatic discharge protection circuit of the prior art. 〇 Figure 2 shows the electrostatic discharge protection circuit according to the implementation of this turn. Fig. 3 and Fig. 4 respectively show an example of the detailed structure of the electrostatic discharge protection circuit shown in Fig. 2. 5 to 7 show the detailed structure of the electrostatic discharge protection circuit which can prevent leakage current according to the present invention. [Main component symbol description] 13 201042748 200, 300, 400, 402, 500, 502, 600, 700 Electrostatic discharge protection circuit 201 N-type 矽 control rectifier 203 P-type 矽 control rectifier 205 trigger circuit 207 ESD detection circuit 208 input /output pad 301, 401 resistor 303, 403, 609, 709 capacitor 307 inverter
305、605、705 第一 NMOS 405、603、703 第一 PMOS 209、501、504複合電路 503 第二 NMOS305, 605, 705 first NMOS 405, 603, 703 first PMOS 209, 501, 504 composite circuit 503 second NMOS
q 505、613、713 第二 PMOS 601、701複合電路 607、707第一電阻 611、711第二電阻 617、717 第三 NMOS 14q 505, 613, 713 second PMOS 601, 701 composite circuit 607, 707 first resistance 611, 711 second resistance 617, 717 third NMOS 14