TWI449158B - Esd protection circuit for integrated circuit with multiple power domain - Google Patents

Description

Electrostatic discharge protection circuit with multiple power supply area integrated circuits

The present invention relates to an electrostatic discharge protection circuit having multiple power supply area integrated circuits, and particularly relates to a multi-power supply area integrated body that does not conduct between an internal circuit and a power supply line or a ground line when an electrostatic discharge signal is detected. Electrostatic discharge protection circuit for circuits.

In general, the integrated circuit has an ESD (Electrostatic Discharge) protection mechanism, which is generally set between the input/output pad and the internal circuit. However, an integrated circuit usually has multiple power domains, and the interface between these power regions may also have an ESD phenomenon. In high-speed circuits, the gate oxide of the transistor is usually thin, so it may be broken by the ESD current and cause damage to the circuit. Some integrated circuits may place ESD protection components on the signal transmission path between these power supply areas, but such components tend to cause signal delays and fail to meet the high speed requirements of the circuit.

It is an object of the present invention to provide an ESD protection mechanism for circuits of different power supply areas.

Another object of the present invention is to provide an ESD protection mechanism that is not located on the signal transmission path.

An embodiment of the present invention discloses an ESD protection circuit having a plurality of power supply area integrated circuits, including: an ESD protection component coupled between a first power supply line and a first ground line; An internal circuit having a first end coupled to the first power supply line; a first switch coupled between a second end of the first internal circuit and a second ground; and a first The ESD detection circuit is coupled to the first switch for detecting an electrostatic discharge signal, and the first switch is not turned on when the electrostatic discharge signal is generated.

Another embodiment of the present invention discloses an integrated circuit having a sudden current protection mechanism, including: a first protection circuit having a first end coupled to the first power supply line; The switch is coupled between a second end of the first protection circuit and a second ground; and a first burst current detecting circuit is coupled to the first switch for detecting The electrostatic discharge signal, and when the electrostatic discharge signal is generated, the first switch is not turned on.

According to the above embodiment, ESD protection can be provided to circuits of different power supply areas, and the protection elements are not on the signal transmission path, so that the problem of signal delay can be avoided.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means. In addition, the first device and the second device used in the specification and the following claims are not to be in a prioritized relationship, but merely indicate that they are different devices.

1 to 4 are circuit diagrams respectively showing an ESD protection circuit 100 having multiple power supply area integrated circuits in accordance with an embodiment of the present invention. As shown in FIG. 1a, the ESD protection circuit 100 having multiple power supply area integrated circuits includes: an ESD protection component 101, a first internal circuit 103 (ie, a protection circuit), and a first switch 105 (eg, The figure is labeled as switch 1), a first ESD detecting circuit 107 (shown as ESD detecting circuit 1), a second switch 109 (shown as switch 2) and a second ESD detecting circuit 111 ( As shown in the figure, the ESD detection circuit 2). The first internal circuit 103 is coupled between the first power supply line Vcc1 and the second ground line GND2, and can be regarded as a power supply area. The second internal circuit 115 is coupled to the second power supply line Vcc2 and the first ground. Between GND1, it can be regarded as another power supply area. The ESD protection component 101 is coupled between the first power supply line Vcc1 and a first ground line GND1. The first internal circuit 103 has a first end coupled to the first power supply line Vcc1. The first switch 105 is coupled between a second end of the first internal circuit 103 and a second ground line GND2. The first ESD detecting circuit 107 is coupled to the first switch 105 for detecting an electrostatic discharge signal (for example, a sudden large voltage or a sudden large current), and when the electrostatic discharge signal is generated, The first switch 105 is rendered non-conductive. Similarly, the second switch 109 is coupled between the first internal circuit 103 and the first power line Vcc1, and the second ESD detecting circuit 111 is coupled to the second switch 109 for detecting an electrostatic discharge signal (for example, A burst voltage or a sudden current) outputs an ESD notification signal ES, and causes the second switch 109 to be non-conductive when the electrostatic discharge signal is generated. By doing so, it is possible to prevent the ESD current from flowing through the delay element 113 (which may be the parasitic resistance of the signal line itself or the resistance added to the operation speed of the circuit) to the second internal circuit 115 to penetrate the second internal circuit. The gate oxide layer of the 115 transistor. Moreover, since the first switch 105, the second switch 109, the first ESD detecting circuit 107, and the second ESD detecting circuit 111 are not on the signal transmission path (that is, the first internal circuit 103 and the second internal circuit 115) The signal interface between the two power zones can therefore improve the delay in the signal in the prior art.

The structure and components of the ESD protection circuit 120 having the multi-power supply area integrated circuit shown in FIG. 1b are substantially the same as the ESD protection circuit having the multi-power supply area integrated circuit shown in FIG. The difference is that the second ESD detecting circuit 111 shown in FIG. 1b is omitted, and the electrostatic discharge protection circuit having the multiple power supply area integrated circuit shown in FIG. 1b uses the first ESD detecting circuit 107 to simultaneously The first switch 105 and the second switch 109 are controlled. Therefore, when the ESD detecting circuit 107 senses the ESD signal, the first switch 105 and the second switch 109 are simultaneously turned off to prevent the ESD current from flowing to the second internal circuit 115 and flowing through the delay element 113 (this example). The gate oxide layer of the transistor of the second internal circuit 115 is penetrated by a resistor. Other detailed technical features have been disclosed in FIG. 1b, and therefore will not be described again here. In the above embodiment, the first internal circuit 101 has a PMOS 102 and an NMOS 104.

The electrostatic discharge protection circuit 200 having the multiple power supply area integrated circuit shown in Fig. 2a has the same elements as the electrostatic discharge protection circuit 100 having the multiple power supply area integrated circuit shown in Fig. 1a. The first internal circuit 201 in the ESD protection circuit 200 having multiple power supply area integrated circuits has a PMOS 202 and an NMOS 204 like the first internal circuit 101 in the ESD protection circuit 100 having multiple power supply area integrated circuits. . The difference is that the base of the NMOS 204 in FIG. 2a is directly connected to the second ground GND2, and the base of the NMOS 104 in FIG. 1a is directly connected to the source of the NMOS 104 and the first switch 105. If the structure in Figure 1a is to be used, the NMOS 104 can be implemented using an NMOS having a deep N-type implant layer (Deep N Well).

Similarly, the electrostatic discharge protection circuit 220 having the multiple power supply area integrated circuit shown in Fig. 2b has the same elements as the electrostatic discharge protection circuit 120 having the multiple power supply area integrated circuit shown in Fig. 1b. The first internal circuit 203 of the ESD protection circuit 220 having multiple power supply area integrated circuits has a PMOS 206 and an NMOS 208 like the first internal circuit 103 of the ESD protection circuit 120 having multiple power supply area integrated circuits. . The difference is that the base of the NMOS 208 in FIG. 2b is directly connected to the second ground GND2, and the base of the NMOS 104 in FIG. 1b is directly connected to the source of the NMOS 104 and the first switch 105.

In the embodiment shown in Figure 3, the internal circuitry of each power region uses a single switch and a single ESD detection circuit as protection. As shown in FIG. 3a, the integrated circuit 300 of the ESD protection mechanism includes an ESD protection component 301, an internal circuit 303, a switch 305, and an ESD detection circuit 307. Similarly, the ESD detection circuit 307 is coupled to the switch 305 for detecting an electrostatic discharge signal (eg, a sudden large voltage or a sudden large current), and causing the switch to be generated when the electrostatic discharge signal is generated. 305 does not conduct. In the embodiment shown in FIG. 3a, the internal circuit 309 and the internal circuit 303 belong to different power supply areas, but also have corresponding ESD protection elements 311, switches 313, and ESD detection circuits 315, and their operation modes are also internal. Circuit 303 is the same.

The electrostatic discharge protection circuit 320 having the multiple power supply area integrated circuit shown in Fig. 3b has the same elements as the electrostatic discharge protection circuit 300 having the multiple power supply area integrated circuit shown in Fig. 3a. The first internal circuit 317 of the ESD protection circuit 320 having multiple power supply area integrated circuits has a PMOS 306 and an NMOS 308 like the first internal circuit 303 of the ESD protection circuit 300 having multiple power supply area integrated circuits. . The difference is that the base of the NMOS 308 in FIG. 3b is directly connected to the second ground GND2, and the base of the NMOS 304 in FIG. 3a is directly connected to the source of the NMOS 304 and the first switch 305.

In the embodiment shown in FIG. 4, a plurality of internal circuits can share a set of protection circuits, and the set of protection circuits includes two switches and an ESD detection circuit. As shown in FIG. 4, the internal circuits 401 and 403 (the internal circuits of the two internal circuits may be internal circuits of the same power supply area) share the switch 405, the switch 407, and the ESD detecting circuit 409, so that a set of protection circuits can simultaneously prevent ESD. Current flows to internal circuits 411 and 413.

Fig. 5 is a diagram showing an exemplary detailed structure of the switches of the circuits shown in Figs. 1 to 4. In Figure 5a, an NMOS 501 is used as a switch. The base of the NMOS 501 is coupled to the ground and its gate receives the ESD notification signal ES from the ESD detection circuit to be turned on or off. In Figure 5b, a PMOS 503 is used as the switch. The base of the PMOS 503 is coupled to the ground and its gate receives the ESD notification signal ES from the ESD detection circuit to be turned on or off.

Fig. 6 is a diagram showing an exemplary detailed structure of the ESD detecting circuit 600 of the circuits shown in Figs. 1 to 4. As shown in FIG. 6, the ESD detecting circuit 600 has a first impedance element 601, a second impedance element 603, and an inverter 605. The input of the inverter 605 is coupled to the NMOS 501 shown in FIG. 5, and the output of the inverter 605 is coupled to the PMOS 503 shown in FIG. The first impedance element 601 and the second impedance element 603 can be implemented by a diode, a capacitor, a resistor, or the like.

Fig. 7 is a circuit diagram showing an electrostatic discharge protection circuit 700 having a multi-power supply area integrated circuit using the structure shown in Figs. 5-6. As shown in FIG. 7, the ESD protection circuit 700 having multiple power supply area integrated circuits has an internal circuit 701, a first switch 703, a second switch 705, and an ESD detection circuit 707. In this embodiment, the first switch 703 is an NMOS, the second switch 705 includes a PMOS 711 and an inverter 713, and the ESD detecting circuit 707 includes a resistor 715 and a capacitor 717. In the normal state, the power supply Vcc2 can normally charge the capacitor 717, so the contact A will remain in the high level state, and the first switch 703 and the second switch 705 will remain in the on state. When the ESD is generated, the capacitor 717 cannot be normally charged, so the contact A will remain in the low level state, and the first switch 703 and the second switch 705 will become non-conductive. It should be noted that the structure shown in FIG. 7 is for example only and is not intended to limit the present invention, and those skilled in the art can obtain the same result when the circuit structure can be arbitrarily changed.

According to the above embodiment, ESD protection can be provided to circuits of different power supply areas, and the protection elements are not on the signal transmission path, so that the problem of signal delay can be avoided.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 120. . . Electrostatic discharge protection circuit with multiple power supply area integrated circuits

101, 301, 311. . . ESD protection component

103, 201, 203. . . First internal circuit

105, 703. . . First switch

107. . . First ESD detection circuit

109, 705. . . Second switch

111. . . Second ESD detection circuit

113. . . Delay element

115. . . Second internal circuit

202, 206, 302, 306, 503, 711. . . PMOS

204, 208, 304, 308, 501. . . NMOS

303, 309, 317, 401, 403, 411, 413, 701‧‧‧ internal circuits

305, 313, 405, 407‧‧ ‧ switch

301, 311‧‧‧ ESD protection components

307, 315, 409, 600, 707‧‧ ESD detection circuit

601‧‧‧First impedance element

603‧‧‧second impedance element

605, 713‧‧ ‧Inverter

715‧‧‧resistance

717‧‧‧ Capacitance

1a, 1b, 2a, 2b, 3a, 3b, and 4 are circuit diagrams respectively showing an ESD protection circuit having multiple power supply area integrated circuits in accordance with an embodiment of the present invention.

Fig. 5 is a diagram showing an exemplary detailed structure of switches of the circuits 1a, 1b, 2a, 2b, 3a, 3b and 4th.

Fig. 6 is a diagram showing an exemplary detailed structure of the ESD detecting circuit of the circuits 1a, 1b, 2a, 2b, 3a, 3b and 4th.

Fig. 7 is a circuit diagram showing an electrostatic discharge protection circuit having a multi-power supply area integrated circuit using the structure shown in Figs. 5-6.

100, 120. . . Electrostatic discharge protection circuit with multiple power supply area integrated circuits

101. . . ESD protection component

103. . . First internal circuit

105. . . First switch

107. . . First ESD detection circuit

109. . . Second switch

111. . . Second ESD detection circuit

113. . . Delay element

115. . . Second internal circuit

Claims (14)

An ESD protection circuit having a plurality of power supply area integrated circuits, comprising: a first ESD protection component coupled between a first power supply line and a first ground line; and a first internal circuit coupled a first switch of the first power supply line; a first switch coupled between a second end of the first internal circuit and a second ground; and a first ESD detection circuit coupled Connected to the second power supply line and the second ground line, coupled to the first switch, for detecting an electrostatic discharge signal, and preventing the first switch from being turned on when the electrostatic discharge signal is generated a second internal circuit coupled between the second power supply line and the first ground line; and a second ESD protection component coupled between the second power supply line and the second ground line . The ESD protection circuit of claim 1, further comprising: a second switch coupled between the first end of the first internal circuit and the first power supply line; and a second The ESD detection circuit is coupled between the first power supply line and the first ground line, and coupled to the second switch for detecting an electrostatic discharge signal, and when the electrostatic discharge signal is generated, The second switch is not conducting. The electrostatic discharge protection circuit of claim 1, wherein the first open relationship is an NMOS, and a base system of the first switch is directly connected to a source of the first switch and the first switch . The electrostatic discharge protection circuit of claim 3, wherein the first switch has a deep N-type implant layer (Deep N Well). The electrostatic discharge protection circuit of claim 1, wherein the first open relationship is an NMOS, and a base system of the first switch is directly connected to the first ground. The ESD protection circuit of claim 1, further comprising a second switch coupled between the first end of the first internal circuit and the first power supply line, and coupled to the The first ESD detecting circuit prevents the second switch from being turned on when the electrostatic discharge signal is generated. An integrated circuit with a sudden current protection mechanism includes: a first protection circuit having a first end coupled to a first power supply line; a first switch coupled to the first a second current end of the protection circuit and a second ground line; a first burst current detecting circuit coupled between the second power supply line and the second ground line, coupled to the first a switch for detecting an electrostatic discharge signal, and causing the first switch to be non-conducting when the electrostatic discharge signal is generated, and A second protection circuit is coupled between the second power supply line and the first ground line. The integrated circuit with the sudden current protection mechanism described in claim 7 further includes: a second switch coupled to the first end of the first circuit to be protected and the first power supply And a second burst current detecting circuit coupled between the first power supply line and the first ground line, coupled to the second switch for detecting an electrostatic discharge signal And when the electrostatic discharge signal is generated, the second switch is not turned on. The integrated circuit with a sudden current protection mechanism according to the seventh aspect of the invention, wherein the first open relationship is an NMOS, and a base system of the first switch is directly connected to one of the first switches a source and the first switch. The integrated circuit with a sudden current protection mechanism according to claim 9, wherein the first switch has a deep N-type implant layer (Deep N Well). The integrated circuit with a sudden current protection mechanism according to claim 7, wherein the first open relationship is an NMOS, and a base system of the first switch is directly connected to the first ground. The integrated circuit with the sudden current protection mechanism described in claim 7 further includes a second switch coupled to the first end of the first circuit to be protected. And the first power supply line is coupled to the first burst current detecting circuit, and the first burst current detecting circuit disables the second switch when the static discharge signal is generated. . The ESD protection circuit of claim 1, further comprising: a signal transmission path coupled between the first internal circuit and the second internal circuit. The integrated circuit with the sudden current protection mechanism described in claim 7 further includes: a signal transmission path coupled between the first protection circuit and the second protection circuit.