JP5082841B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  FIG. 5 is a diagram illustrating a configuration example of a normal I / O (input / output) semiconductor device. In normal I / O, the voltage input to the input / output pad 501 is equal to or lower than the voltage of the power supply voltage node VDE. The semiconductor device includes ESD (electro-static discharge) protection circuits 505 to 507. The output buffer 502 includes transistors 503 and 504. The ESD protection circuit 505 has a parasitic diode and is connected between the power supply voltage node VDE and the ground potential node GND. The ESD protection circuit 506 includes a parasitic diode and is connected between the power supply voltage node VDE and the input / output pad 501. The ESD protection circuit 507 has a parasitic diode and is connected between the input / output pad 501 and the ground potential node GND. The ESD protection circuits 505 to 507 are circuits for preventing malfunction or damage of the semiconductor device when static electricity is input to the input / output pad 501.

  FIG. 6 is a diagram illustrating a configuration example of a tolerant I / O semiconductor device. In the tolerant I / O, the voltage input to the input / output pad 601 is equal to or lower than the voltage of the power supply voltage node VDE. For example, the voltage of the power supply voltage node VDE is 3.3 V, and a 5 V power supply signal is input to the input / output pad 601. Therefore, an ESD protection circuit cannot be provided between the power supply voltage node VDE and the input / output pad 601. The semiconductor device includes ESD protection circuits 607 and 608. The output buffer 602 includes transistors 603 to 605. The ESD protection circuit 607 has a parasitic diode and is connected between the power supply voltage node VDE and the ground potential node GND. The ESD protection circuit 608 has a parasitic diode and is connected between the input / output pad 601 and the ground potential node GND. The potential control circuit 606 controls the potential of the back gate of the p-channel MOS field effect transistor 603.

  In addition, since a voltage higher than the withstand voltage of the transistors constituting the circuit is applied to the input / output pad 601 (for example, in the case of 5V tolerant, the circuit is constituted by a 3.3V withstand voltage transistor and the input voltage is 5V). And the circuit (output buffer 602 and input buffer, ESD protection circuit, etc.) must be connected via a voltage drop circuit (eg, transistor 604).

  Patent Document 1 listed below is an input / output protection device for an integrated circuit formed on a semiconductor substrate, and this input / output protection device has a MOS structure including a drain, a gate, a source, and a body. The drain is connected to an input / output pad, the gate is connected to an internal circuit or a first reference potential terminal, the source is connected to a first reference potential terminal, and the body is electrically connected to the semiconductor substrate. And an input / output protection device for a semiconductor integrated circuit, wherein the input / output protection device is connected to a control circuit.

  Patent Document 2 below is provided corresponding to a plurality of power supply systems, and one of each power supply terminal or ground terminal is separated from each other, or each power supply terminal and ground terminal are separated from each other. A plurality of power system circuits, an electrostatic discharge protection circuit connected between a power terminal and a ground terminal corresponding to each power system circuit, an internal circuit provided in each power system circuit, and each power system An internal signal propagation wiring for propagating a signal from an internal circuit of a first power supply system circuit to an internal circuit of a second power supply system circuit, a surge input detection circuit for detecting a surge voltage input of a power supply terminal, Inserted on the input side of each internal circuit and inserted on the output side of the input protection circuit for limiting the voltage of the signal propagated from the internal signal propagation wiring and / or on the output side of each internal circuit. And an output logic setting circuit having a function capable of setting a logic level of a signal output to the internal signal propagation wiring to “L” when a detection output of the surge input detection circuit is obtained. A semiconductor integrated circuit device is described.

  Further, in Patent Document 3 below, in an electrostatic discharge protection circuit for protecting an internal circuit from electrostatic discharge, a first power line connected to a first power terminal and a first power line connected to a second power terminal are disclosed. A power supply clamp unit having an n-channel MOS field effect transistor electrically connected between the two power lines and a gate voltage control unit for controlling the gate voltage of the n-channel MOS field effect transistor. The gate voltage control unit has one input / output terminal connected to the first power supply line and the other input / output terminal connected to the gate terminal of the n-channel MOS field effect transistor. An effect transistor, and one terminal in front of the other input / output terminal of the p-channel MOS field effect transistor and the n-channel MOS field effect transistor. A gate terminal, a first resistor having the other terminal connected to the second power supply line, one terminal to the first power supply line, and the other terminal to the gate terminal of the p-channel MOS field effect transistor A second resistor connected to the first resistor, one terminal connected to the other terminal of the second resistor and the gate terminal of the p-channel MOS field effect transistor, and the other terminal connected to the second power line. An electrostatic discharge protection circuit including a capacitor is described.

  Patent Document 4 listed below discloses a discharge circuit installed between a voltage input terminal for inputting a voltage supplied from the outside into an internal circuit and a power supply, and a voltage for detecting the voltage of the voltage input terminal. An input protection circuit comprising a detection circuit, wherein the voltage detection circuit stops the operation of the discharge circuit when the voltage at the voltage input terminal exceeds a reference voltage. Has been.

JP 2001-186003 A JP 2005-184623 A JP 2005-235947 A JP 2001-127172 A

  FIG. 7 is a diagram illustrating a configuration example of the ESD protection circuit 608 in the semiconductor device of FIG. The ESD protection circuit 608 includes n-channel MOS field effect transistors 701 and 702 and has the same configuration as the transistors 604 and 605 in the output buffer 602. As shown in FIG. 9, when the parasitic bipolar transistor 901 of the n-channel MOS field effect transistors 701 and 702 is used as the ESD protection circuit 608, an input voltage higher than the transistor breakdown voltage is applied to the input / output pad 601. It is necessary to ensure a withstand voltage by using a 702 cascade structure.

  FIG. 8 is a surface view of the ESD protection circuit 608, and FIG. 9 is an equivalent circuit diagram of the ESD protection circuit 608. In the guard ring 801, two sets of cascade connection circuits of transistors 701 and 702 are connected in parallel. Thus, the current flowing through the transistors 701 and 702 can be increased. Transistors 701 and 702 each have a gate G, a source S, and a drain D. A parasitic bipolar transistor 901 is formed in the cascade structure of the field effect transistors 701 and 702. This parasitic bipolar transistor 901 is used as the ESD protection circuit 608. In the cascade connection circuit of two sets of transistors 701 and 702, when current flows in one cascade connection circuit, the voltage of the input / output pad 601 decreases, and in order to prevent the current from flowing in the other cascade connection circuit, Block 802 prevents silicidation and adds ballast resistance.

  The parasitic bipolar transistor 901 has a lower discharge capability than the single transistor ESD protection circuit because the distance between the two gates is the base distance LN. Field effect transistors 701 and 702 are formed so that the base distance LN becomes a minimum value. Therefore, when the parasitic bipolar transistor 901 is used as an ESD protection circuit, the following special tuning may be required.

・ Additional ion implantation (increase process steps and development period)
・ Ion implantation only for transistors used in ESD protection circuits (I / O size increase, development period increase)
Addition of ballast resistor (silicide block 802) (increase in process steps and I / O size)

  An object of the present invention is to provide a semiconductor device having an electrostatic discharge (ESD) protection circuit that does not require special tuning, can reduce process steps and development periods, and can be reduced in size.

  In the semiconductor device of the present invention, an input / output pad, a power supply voltage node to which a power supply voltage is supplied, a reference potential node to which a reference potential is supplied, an anode is connected to the input / output pad, and a cathode is a first node. The first diode is connected to the input / output pad and the power supply voltage node. When a voltage lower than the power supply voltage is input to the input / output pad, the first node becomes the power supply voltage. A potential control circuit that controls the input and output pads, a trigger circuit that outputs a static on signal when static electricity is input to the input / output pad, and the first node and the reference potential when the static on signal is output. And an electrostatic discharge surge path circuit for passing an electrostatic discharge current between the nodes.

  An electrostatic discharge surge path circuit can be provided to protect the semiconductor device from electrostatic discharge. At that time, special tuning is not required, and the process steps and the development period can be reduced and the size can be reduced.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration example of a tolerant I / O semiconductor device according to the first embodiment of the present invention. In the tolerant I / O, the voltage input to the input / output pad 101 is equal to or lower than the voltage of the power supply voltage node VDE. For example, the voltage of the power supply voltage node VDE is 3.3 V, and a 5 V power supply signal is input to the input / output pad 101. The semiconductor device includes an input / output pad 101, an I / O circuit 102, and ESD protection circuits 104 to 106. The ESD protection circuits 104 to 106 are circuits for preventing malfunction or damage of the semiconductor device when high voltage static electricity is input to the input / output pad 101.

  The I / O circuit 102 includes a potential control circuit 103 and an output buffer 110. The output buffer 110 includes a p-channel MOS field effect transistor 121 and n-channel MOS field effect transistors 122 and 123. Transistor 121 has a source connected to power supply voltage node VDE, a drain connected to the drain of transistor 122, and a back gate connected to node BP. Transistor 122 has a gate connected to power supply voltage node VDE and a source connected to the drain of transistor 123. The source of the transistor 123 is connected to the ground potential node (reference potential node) GND. The input / output pad 101 is connected to the drain of the transistor 121.

  The transistor 122 functions as a voltage drop circuit. For example, when the power supply voltage of the power supply voltage node VDE is 3.3V and a signal of 5V power supply is input to the input / output pad 101, a voltage drop of 1.7V occurs in the transistor 122, and the drain of the transistor 123 A voltage of 3.3V (= 5V-1.7V) is applied. As the transistor 123, a 3.3V withstand voltage transistor can be used.

  In the output buffer 110, a high level (power supply voltage) can be output to the input / output pad 101 by setting the gates of the transistors 121 and 123 to a low level. Conversely, when the gates of the transistors 121 and 123 are set to the high level, a low level (ground potential) can be output to the input / output pad 101. When the gate of the transistor 121 is set to a high level and the gate of the transistor 123 is set to a low level, the output terminal of the output buffer 110 is in a high impedance state, and a signal can be input from the input / output pad 101.

  The I / O circuit 102 has a potential control circuit 103. The potential control circuit 103 includes p-channel MOS field transistors 111 and 112. When a voltage equal to or lower than the power supply voltage node VDE is applied to the input / output pad 101 or when the input / output pad 101 is in an open state, the potential of the node BP is Control is performed to be the same as the power supply voltage of the power supply voltage node VDE. The transistor 111 has a source connected to the power supply voltage node VDE, and a drain and a back gate connected to the node BP. The transistor 112 has a gate connected to the power supply voltage node VDE, a source and a back gate connected to the node BP, and a drain connected to the drain of the transistor 121.

  The ESD protection circuits 104 and 105 are ESD protection circuits for the input / output pad 101. The ESD protection circuit 104 includes a diode 131. The diode 131 has an anode connected to the input / output pad 101 and a cathode connected to the node BP. When a voltage higher than the power supply voltage node VDE is input to the input / output pad 101, a current flows through the diode 131, and the node BP has the same potential as the input / output pad 101. That is, the node BP has the same potential as the power supply voltage of the power supply voltage node VDE when a voltage equal to or lower than the power supply voltage node VDE is applied to the input / output pad 101 or when the input / output pad 101 is in an open state. When a voltage higher than the power supply voltage node VDE is applied, the potential is the same as that of the input / output pad 101.

  The ESD protection circuit 105 includes a diode 132. The diode 132 has an anode connected to the ground potential node GND and a cathode connected to the input / output pad 101. When a voltage lower than the ground potential is applied to the input / output pad 101, a current flows through the diode 132, and the semiconductor device can be protected.

  The ESD protection circuit 106 includes a voltage drop circuit 107, an ESD surge path circuit 108, and a trigger circuit 109. The voltage drop circuit 107 includes diodes 141 and 142 and an n-channel MOS field effect transistor 143. The diode 141 has an anode connected to the node BP and a cathode connected to the anode of the diode 142. The diode 142 has a cathode connected to the node N1. A voltage lower than the node BP by a voltage drop of the diodes 141 and 142 is applied to the node N1. Transistor 143 has a gate connected to node N 1, a drain connected to node BP, and a source connected to the drain of n-channel MOS field effect transistor 144. A voltage lower than the node BP by a voltage drop of the transistor 143 is applied to the drain of the transistor 144.

  The trigger circuit 109 includes a resistor 151, a capacitor 152, a diode 153, and inverters 154 to 156, and uses an RC timer. The resistor 151 is connected between the node N1 and the input terminal of the inverter 154. The capacitor 152 is connected between the input terminal of the inverter 154 and the ground potential node GND. The diode 153 has an anode connected to the node N <b> 1 and a cathode connected to the power supply terminal of the inverter 153. Inverter 154 has a ground terminal connected to ground potential node GND and an output terminal connected to an input terminal of inverter 155. The threshold value is adjusted by the inverter 154 and the diode 153. Inverter 155 has a power supply terminal connected to node N 1, a ground terminal connected to ground potential node GND, and an output terminal connected to the input terminal of inverter 156. Inverter 156 has a power supply terminal connected to node N 1, a ground terminal connected to ground potential node GND, and an output terminal connected to the gate of transistor 144. Inverters 154 to 156 invert the signals of the input terminals and output the signals from the output terminals.

  The ESD surge path circuit 108 includes n-channel MOS field effect transistors 143 and 144, and forms an ESD surge path between the node BP and the ground potential node GND. The transistor 144 has a gate connected to the output terminal of the inverter 156, a drain connected to the source of the transistor 143, and a source connected to the ground potential node GND.

  The trigger circuit 109 functions as a low pass filter. For example, when an input signal of 5V power is input to the input / output pad 101, the node BP becomes, for example, 5V to 3.3V. When the input signal has a frequency lower than that of static electricity, the input terminal of the inverter 154 becomes high level and the output terminal of the inverter 156 becomes low level. As a result, the transistor 144 is turned off, no current flows through the transistors 143 and 144, and the ESD protection circuit 106 is disconnected. Further, even when the input signal has a higher frequency than that of static electricity, the ESD protection circuit 106 is cut off by preventing threshold voltage adjustment by the inverter 154 and the diode 153 so as not to operate with a voltage fluctuation of 5 V to 3.3 V. be able to. That is, the ESD protection circuit 106 does not adversely affect the normal operation of the semiconductor device.

  When high-voltage static electricity is input to the input / output pad 101, the node BP has almost the same voltage as the input / output pad 101. Since static electricity has a higher frequency and a higher voltage than the low-pass filter of the trigger circuit, the input terminal of the inverter 154 is at a low level and the output terminal of the inverter 156 is at a high level. As a result, the transistor 144 is turned on, and an ESD surge current flows in the ESD surge path of the transistors 143 and 144. Thereby, the ESD protection circuit 106 can protect the semiconductor device from static electricity.

  As described above, when high-frequency and high-voltage static electricity is input to the input / output pad 101, the transistors 143 and 144 are turned on, and the ESD surge current of the ESD surge path circuit 108 flows.

  In the present embodiment, an RC timer is used for the trigger circuit 109, a diode 141 and 142 are connected in series to the voltage drop circuit 107, and a cascade connection circuit of n-channel MOS field effect transistors 143 and 144 is used as the ESD surge path circuit 108. Is used. The transistor 143 in the ESD surge path circuit 108 is also used as the voltage drop circuit 107. Since the RC timer is used for the trigger circuit 109, the ESD surge path circuit 108 operates at a sufficiently low voltage.

  A voltage higher than the withstand voltage of the transistor (a voltage higher than the power supply voltage of the power supply voltage node N1) can be input to the input / output pad 101. Input / output pad ESD protection circuit 104 is connected to node BP different from power supply voltage node VDE (in the case of tolerant I / O, node BP that controls the back gate of p-channel MOS field effect transistor 121 is used). The ESD protection circuit 106 is connected between the node BP and the ground potential node GND. The ESD protection circuit 106 includes a voltage drop circuit 107, a trigger circuit 109, and an ESD surge path circuit 108.

  Since the input potential is transmitted to the node BP by the forward bias of the ESD protection circuit 104 during normal operation, the voltage drop circuit 107 is a circuit that drops the voltage so as not to exceed the transistor breakdown voltage of the trigger circuit 109 and the ESD surge path circuit 108. However, the ESD surge path circuit 108 may be directly connected to the node BP without using the voltage drop circuit 107 when the voltage of the node BP during normal operation is equal to or lower than the withstand voltage of the ESD surge path circuit 108.

  The trigger circuit 109 is a circuit that senses voltage fluctuation when static electricity is applied and operates the ESD surge path circuit 108.

  The ESD surge path circuit 108 is an off state during normal operation, and is a circuit that inputs a signal from the trigger circuit 109 when static electricity is applied and releases the ESD surge to the ground potential node GND. The necessary characteristics of the ESD surge path circuit 108 include the necessity of the ESD surge path circuit 108 that operates at a voltage lower than the breakdown voltage of the I / O circuit 102.

  Advantages of the semiconductor device of this embodiment include the following. First, since it can be composed of a normal transistor, the number of process steps is not increased and ion implantation is not required. That is, a specially tuned transistor is not required.

  Since it is possible to develop an ESD protection circuit by means of Spice simulation, development with a short TAT is possible, and the development period can be shortened.

  The parasitic bipolar transistor type ESD protection circuit has a large layout size due to the addition of a ballast resistor and a limited layout pattern. However, the MOS operation ESD protection circuit can be laid out with the minimum rule, so the size is reduced. be able to.

(Second Embodiment)
FIG. 2 is a circuit diagram showing a configuration example of a tolerant I / O semiconductor device according to the second embodiment of the present invention. This embodiment (FIG. 2) differs from the first embodiment (FIG. 1) in the configuration of the voltage drop circuit 107. Hereinafter, the points of the present embodiment different from the first embodiment will be described. The voltage drop circuit 107 includes resistors 201 and 202 and an n-channel MOS field effect transistor 143. That is, the voltage drop circuit 107 includes resistors 201 and 202 instead of the diodes 141 and 142 in FIG. The resistor 201 is connected between the node BP and the node N1. The resistor 202 is connected between the node N1 and the ground potential node GND. The resistors 201 and 202 can apply a voltage obtained by dropping the voltage of the node BP to the node N1.

  As described above, in this embodiment, the RC timer is used for the trigger circuit 109, the resistors 201 and 202 are used for the voltage drop circuit 107, and the cascade connection circuit of the n-channel transistors 143 and 144 is used for the ESD surge path circuit 108. To do. The transistor 143 of the ESD surge path circuit 108 is also used as the voltage drop circuit 107. Since this embodiment uses an RC timer as the trigger circuit 109 as in the first embodiment, the ESD surge path circuit 108 operates at a sufficiently low voltage.

(Third embodiment)
FIG. 3 is a circuit diagram showing a configuration example of a tolerant I / O semiconductor device according to the third embodiment of the present invention. In the present embodiment (FIG. 3), the transistor 143 is omitted from the first embodiment (FIG. 1). Hereinafter, the points of the present embodiment different from the first embodiment will be described. The drain of the transistor 144 is connected to the node N1. The voltage drop circuit 107 includes diodes 141 and 142. The ESD surge path circuit 108 includes diodes 141 and 142 and a transistor 144. When static electricity is input to the input / output pad 101, the node BP becomes higher than the power supply voltage node VDE, and the transistor 144 is turned on as in the first embodiment. At that time, an ESD surge current flows from the node BP to the ground potential node GND through the diodes 141 and 142 and the transistor 144, so that the semiconductor device can be protected from static electricity. In the ESD surge path, the diodes 141 and 142 function as a voltage drop circuit.

  As described above, in this embodiment, the RC timer is used for the trigger circuit 109, the series connection circuit of the diodes 141 and 142 is used for the voltage drop circuit 107, and the single n-channel transistor 144 is added to the ESD surge path circuit 108. use. Since the voltage drop circuit 107 also serves as the ESD surge path circuit 108, it is necessary to increase the size of the diodes 141 and 142. In this case, since the voltage drop circuit 107 also serves as the ESD surge path circuit 108, a resistor cannot be used as the voltage drop circuit 107 as in the second embodiment. Since the RC timer is used as the trigger circuit 109, the ESD surge path circuit 108 operates at a sufficiently low voltage.

(Fourth embodiment)
FIG. 4 is a circuit diagram showing a configuration example of a tolerant I / O semiconductor device according to the fourth embodiment of the present invention. This embodiment (FIG. 4) differs from the first embodiment (FIG. 1) in the configuration of the trigger circuit 109. Hereinafter, the points of the present embodiment different from the first embodiment will be described.

  The trigger circuit 109 includes transistors 401 to 408. P channel MOS field effect transistor 401 has a gate connected to power supply voltage node VDE, a source connected to node N 1, and a drain connected to the drain of n channel MOS field effect transistor 402. Transistor 402 has a gate connected to power supply voltage node VDE and a source connected to ground potential node GND. In the p-channel MOS field effect transistor 403, the gate and source are connected to the node N1, and the drain is connected to the drain of the n-channel MOS field effect transistor 404. Transistor 404 has a gate connected to node N 1 and a source connected to the drain of n-channel MOS field effect transistor 405. The transistor 405 has a gate connected to the drain of the transistor 401 and a source connected to the ground potential node GND. In the p-channel MOS field effect transistor 406, the gate is connected to the drain of the transistor 401, the source is connected to the node N1, and the drain is connected to the drain of the transistor 403. In the p-channel MOS field effect transistor 407, the gate is connected to the drain of the transistor 406, the source is connected to the node N1, and the drain is connected to the drain of the n-channel MOS field effect transistor 408. The transistor 408 has a gate connected to the drain of the transistor 406 and a source connected to the ground potential node GND. The interconnection point of the drains of transistors 407 and 408 is connected to the gate of transistor 144.

  When static electricity is input to the input / output pad 101, the voltage at the node N1 rises, but the node VDE is in an open state, so that the VDE becomes the GND potential due to the capacitance between VDE and GND. That is, the gates of the transistors 401 and 402 are at a low level, and the drains of the transistors 401 and 402 are at a high level. As in the first embodiment, since the node N1 has a high potential, the drains of the transistors 403 and 404 are at a low level. As a result, the drains of the transistors 407 and 408 become high level, and the transistor 144 of the ESD surge path circuit 108 is turned on. An ESD surge current flows through the transistor 144, and the semiconductor device can be protected from static electricity.

  When an input signal (5 V power supply) is input to the input / output pad 101, the gates of the transistors 401 and 402 are at a high level and the drains of the transistors 401 and 402 are at a low level. As in the first embodiment, since the node N1 has a low potential, the drains of the transistors 403 and 404 are at a high level. As a result, the drains of the transistors 407 and 408 become low level, and the transistor 144 of the ESD surge path circuit 108 is turned off. In that case, the ESD protection circuit 106 does not adversely affect the normal operation of the semiconductor device.

  As described above, in the present embodiment, the above circuit configuration is used for the trigger circuit 109, the series connection circuit of the diodes 141 and 142 is used for the voltage drop circuit 107, and the cascade of the transistors 143 and 144 is used for the ESD surge path circuit 108. Use a connection circuit. The transistor 143 of the ESD surge path circuit 108 is also used as the voltage drop circuit 107. The trigger circuit 109 outputs a low level to the gate of the transistor 144 of the ESD surge path circuit 108 by a signal from the power supply voltage node VDE during normal operation, and the power supply voltage node VDE is open (≈ground potential) when ESD is applied. Therefore, a high level is output to the gate of the transistor 144 of the ESD surge path circuit 108.

  As described above, the semiconductor device according to the first to fourth embodiments includes the input / output pad 101, the power supply voltage node VDE to which the power supply voltage is supplied, the reference potential node GND to which the reference potential is supplied, and the anode. The input / output pad 101 is connected to the first diode 131 whose cathode is connected to the first node BP, the input / output pad 101 and the power supply voltage node VDE, and the input / output pad 101 is connected to the power supply. When a voltage lower than the voltage is input, a potential control circuit 103 that controls the first node BP to be the power supply voltage, and when static electricity is input to the input / output pad 101, a static electricity on signal is output. When the trigger circuit 109 and the static on signal are output, a static discharge current flows between the first node BP and the reference potential node GND. And a gas discharge Sajipasu circuit 108.

  The output buffer 110 includes a first field effect transistor 121, a second field effect transistor 122, and a third field effect transistor 123. The first field effect transistor 121 has a source connected to the power supply voltage node VDE, a drain connected to the input / output pad 101, and a back gate connected to the first node BP. The second field effect transistor 122 has a gate connected to the power supply voltage node VDE and a drain connected to the input / output pad 101. The third field effect transistor 123 has a drain connected to the source of the second field effect transistor 122 and a source connected to the reference potential node GND.

  The voltage drop circuit 107 drops the voltage at the first node BP and outputs the voltage to the trigger circuit 109. The trigger circuit 109 outputs the static electricity on signal according to the voltage output from the voltage drop circuit 107.

  The voltage drop circuit 107 has a second diode 141 and / or 142 whose anode side is connected to the first node BP and whose cathode side is connected to the trigger circuit 109.

  The voltage drop circuit 107 includes a plurality of resistors 201 and 202 connected in series between the power supply voltage node VDE and the reference potential node GND, and an interconnection point of the plurality of resistors 201 and 202 is: Connected to the trigger circuit 109.

  The electrostatic discharge surge path circuit 108 includes a voltage drop circuit 107 (143 or 141 and 142) for dropping the voltage of the first node BP, a gate connected to the output of the trigger circuit 109, and a drain connected to the voltage drop. A field effect transistor 144 connected to the circuit 107 and having a source connected to the reference potential node GND;

  The trigger circuit 109 includes a resistor 151 and a capacitor 152 connected in series between the first node BP and the reference potential node GND.

  The diode 132 has an anode connected to the reference potential node GND and a cathode connected to the input / output pad 101.

  An electrostatic discharge surge path circuit 108 can be provided to protect the semiconductor device from electrostatic discharge. At that time, special tuning is not required, and the process steps and the development period can be reduced and the size can be reduced.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

  The embodiment of the present invention can be applied in various ways as follows, for example.

(Appendix 1)
Input / output pads;
A power supply voltage node to which the power supply voltage is supplied; and
A reference potential node to which a reference potential is supplied;
A first diode having an anode connected to the input / output pad and a cathode connected to a first node;
A potential control circuit that is connected to the input / output pad and the power supply voltage node, and controls the first node to be the power supply voltage when a voltage lower than the power supply voltage is input to the input / output pad;
A trigger circuit that outputs a static on signal when static electricity is input to the input / output pad;
A semiconductor device comprising: an electrostatic discharge surge path circuit that causes an electrostatic discharge current to flow between the first node and the reference potential node when the static on signal is output.
(Appendix 2)
2. The supplementary note 1, further comprising: a first field effect transistor having a source connected to the power supply voltage node, a drain connected to the input / output pad, and a back gate connected to the first node. Semiconductor device.
(Appendix 3)
A second field effect transistor having a gate connected to the power supply voltage node and a drain connected to the input / output pad;
The semiconductor device according to claim 2, further comprising: a third field effect transistor having a drain connected to a source of the second field effect transistor and a source connected to the reference potential node.
(Appendix 4)
And a voltage drop circuit that drops the voltage of the first node and outputs a voltage to the trigger circuit,
2. The semiconductor device according to claim 1, wherein the trigger circuit outputs the static on signal according to a voltage output from the voltage drop circuit.
(Appendix 5)
The electrostatic discharge surge path circuit is:
A voltage drop circuit for dropping the voltage of the first node;
2. The semiconductor device according to claim 1, further comprising: a field effect transistor having a gate connected to the output of the trigger circuit, a drain connected to the voltage drop circuit, and a source connected to the reference potential node.
(Appendix 6)
5. The semiconductor device according to claim 4, wherein the voltage drop circuit includes a second diode having an anode connected to the first node and a cathode connected to the trigger circuit.
(Appendix 7)
The voltage drop circuit includes a plurality of resistors connected in series between the power supply voltage node and the reference potential node, and an interconnection point of the plurality of resistors is connected to the trigger circuit. The semiconductor device according to appendix 4.
(Appendix 8)
2. The semiconductor device according to claim 1, wherein the trigger circuit includes a resistor and a capacitor connected in series between the first node and the reference potential node.
(Appendix 9)
The semiconductor device according to claim 1, further comprising a second diode having an anode connected to the reference potential node and a cathode connected to the input / output pad.

1 is a circuit diagram showing a configuration example of a tolerant I / O semiconductor device according to a first embodiment of the present invention; It is a circuit diagram which shows the structural example of the semiconductor device of tolerant I / O by the 2nd Embodiment of this invention. It is a circuit diagram which shows the structural example of the semiconductor device of tolerant I / O by the 3rd Embodiment of this invention. It is a circuit diagram which shows the structural example of the semiconductor device of tolerant I / O by the 4th Embodiment of this invention. It is a figure which shows the structural example of the semiconductor device of normal I / O. It is a figure which shows the structural example of the semiconductor device of tolerant I / O. FIG. 7 is a diagram illustrating a configuration example of an ESD protection circuit in the semiconductor device of FIG. 6. It is a surface view of an ESD protection circuit. It is an equivalent circuit diagram of an ESD protection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Input / output pad 102 I / O circuit 103 Potential control circuit 104-106 ESD protection circuit 107 Voltage drop circuit 108 ESD surge path circuit 109 Trigger circuit 110 Output buffer

Claims (5)

Input / output pads;
A power supply voltage node to which the power supply voltage is supplied; and
A reference potential node to which a reference potential is supplied;
A first diode having an anode connected to the input / output pad and a cathode connected to a first node;
A potential control circuit that is connected to the input / output pad and the power supply voltage node, and controls the first node to be the power supply voltage when a voltage lower than the power supply voltage is input to the input / output pad;
A trigger circuit that outputs a static on signal when static electricity is input to the input / output pad;
An electrostatic discharge surge path circuit for passing an electrostatic discharge current between the first node and the reference potential node when the static on signal is output;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, further comprising a first field effect transistor having a source connected to the power supply voltage node, a drain connected to the input / output pad, and a back gate connected to the first node. The semiconductor device described. A second field effect transistor having a gate connected to the power supply voltage node and a drain connected to the input / output pad;
3. The semiconductor device according to claim 2, further comprising: a third field effect transistor having a drain connected to a source of the second field effect transistor and a source connected to the reference potential node. And a voltage drop circuit that drops the voltage of the first node and outputs a voltage to the trigger circuit,
The semiconductor device according to claim 1, wherein the trigger circuit outputs the static electricity on signal according to a voltage output from the voltage drop circuit. The electrostatic discharge surge path circuit is:
A voltage drop circuit for dropping the voltage of the first node;
2. The semiconductor device according to claim 1, further comprising: a field effect transistor having a gate connected to the output of the trigger circuit, a drain connected to the voltage drop circuit, and a source connected to the reference potential node.

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