CN101197500A - Electrostatic discharge protecting circuit - Google Patents
Electrostatic discharge protecting circuit Download PDFInfo
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- CN101197500A CN101197500A CNA2006101642951A CN200610164295A CN101197500A CN 101197500 A CN101197500 A CN 101197500A CN A2006101642951 A CNA2006101642951 A CN A2006101642951A CN 200610164295 A CN200610164295 A CN 200610164295A CN 101197500 A CN101197500 A CN 101197500A
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- oxide semiconductor
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- esd protection
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- 230000005540 biological transmission Effects 0.000 claims abstract description 61
- 239000004065 semiconductor Substances 0.000 claims abstract description 60
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 51
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 51
- 238000003466 welding Methods 0.000 claims description 22
- 230000003068 static effect Effects 0.000 claims description 12
- 230000001012 protector Effects 0.000 claims description 11
- 238000001514 detection method Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 abstract 3
- 229910000679 solder Inorganic materials 0.000 abstract 2
- 238000005516 engineering process Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
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Abstract
The invention provides an electrostatic discharge protective circuit, comprising an electrostatic discharge protective element, a transmission gate circuit, a first N-type metal oxide semiconductor transistor, a first P-type metal oxide semiconductor transistor, a delay circuit, a first inverting logic circuit, and a second inverting logic circuit. The electrostatic discharge protective element is connected with a solder joint; the transmission gate circuit is connected with the solder joint and an output terminal; the first N-type metal oxide semiconductor transistor is used to provide the transmission gate circuit with a bias voltage according to a second voltage level; the first P-type metal oxide semiconductor transistor is used to provide the transmission gate circuit with a second bias voltage according to the first voltage level; the delay circuit is used to decide the turn-on time and the turn-off time of the transmission gate circuit; the first inverting logic circuit is used to produce a first control signal according to the output of the delay circuit; the second inverting logic circuit is used to produce a second control signal according to the output of the first inverting logic circuit, wherein the transmission gate circuit is alternatively turned on or turned off according to the first control signal and the second control signal.
Description
Technical field
The present invention is particularly to completely cut off connection welding (pad) and internal circuit fully relevant for a kind of ESD protection circuit, and prevents the ESD protection circuit of parasitic NPN passage.
Background technology
Fig. 1 represents the ESD protection circuit 100 of known technology.As shown in Figure 1, ESD protection circuit 100 comprises one first rectifier cell 101, one second rectifier cell 103, a resistive element 105.First rectifier cell 101 and second rectifier cell 103 utilize metal oxide semiconductor transistor or diode to implement usually.ESD protection circuit 100 is connected to a connection welding 107 and an internal circuit 109, flow to internal circuit 109 in order to prevent esd pulse from connection welding 107.Generally speaking; can be led from first rectifier cell 101 or second rectifier cell 103 from the esd pulse that connection welding 107 enters; yet if resistance 105 too hour electric current can flow through resistance 105 and enter internal circuit 109; and then cause the damage of internal circuit 109; otherwise if resistance 105 is too big; though internal circuit 109 can be more protected, also cause the circuit delay increase to be difficult for the problem of high speed operation simultaneously.
Fig. 2 represents the ESD protection circuit 200 of known technology.As shown in Figure 2, ESD protection circuit 200 comprises a transmission gating circuit 201 and a control circuit 203.Control circuit 203 is in order to the operation of control transmission gating circuit 201.When normal operation, transmission gating circuit 201 is the state of conducting, and when esd pulse was imported into by connection welding 205, transmission gating circuit 201 states for shutoff entered internal circuit to avoid esd pulse.This circuit can be adjusted the size of transmission gating circuit 201 to adjust the size of the input resistance that enters from connection welding 205.Electric capacity 207 in the control circuit 203 and resistance 209 constitute a delay circuit, in order to turning on and off the time of decision transmission gating circuit 201.N type metal oxide semiconductor transistor 211 and 213 is respectively in order to provide bias voltage to the P trap (P-Well) of N type metal oxide semiconductor transistor 215 or the N trap (N-Well) of substrate (body) and P-type mos transistor 214 in the transmission gating circuit 201.
Yet, because P-type mos transistor 214 is directly connected to electric capacity 207 and resistance 209, therefore when esd pulse enters, the grid voltage of P-type mos transistor 214 is that esd pulse produces via electric capacity 207 couplings, therefore transistor 214 possibly can't turn-off fully, and N type metal oxide semiconductor transistor 213 may be because of improper formation one parasitism of layout figure (parasitic) NPN path in addition; If esd pulse is by the first voltage level Vcc, the second voltage level VGND that leads, destructive ESD electric current may and cause the damage of transistor 213 via this path conducting.Make ESD protection circuit 200 can't reach the effect of protection.
A kind of invention that utilizes oscillating circuit as the ESD protection circuit is also disclosed in this external United States Patent (USP) 7009826.Yet, the RF circuit of this invention not with the perfect isolation of connection welding.And, can make circuit that bigger area is arranged, and under normal operating state, unnecessary resonance also might take place in this circuit because of using the LC resonant circuit.Other detailed descriptions about this circuit have been disclosed in the United States Patent (USP) 7009826, so do not repeat them here.
Therefore, need a kind of invention of novelty to solve the above problems.
Summary of the invention
Therefore, purpose of the present invention one for a kind of ESD protection circuit is provided, it makes the transmission gating circuit not be directly connected to delay circuit, can't turn-off when esd pulse enters to avoid transmitting gating circuit.
Purpose of the present invention one for a kind of ESD protection circuit is provided, it utilizes specific metal oxide semiconductor transistor to provide bias voltage to the transmission gating circuit, to avoid parasitic NPN path.
Preferred embodiment of the present invention discloses a kind of ESD protection circuit, comprises: an electric static discharge protector, a transmission gating circuit, one the one N type metal oxide semiconductor transistor, one first P-type mos transistor, a delay circuit, one first inverted logic circuit and one second inverted logic circuit.Electric static discharge protector is connected to a connection welding.The transmission gating circuit is connected to a connection welding and an output.The one N type metal oxide semiconductor transistor is connected to transmission gating circuit and one second voltage level, in order to provide one first to be biased into the transmission gating circuit according to second voltage level.The first P-type mos transistor is connected to the transmission gating circuit and first voltage level, in order to provide one second to be biased into the transmission gating circuit according to first voltage level.Delay circuit is connected to electric static discharge protector, in order to turning on and off the time of decision transmission gating circuit.The first inverted logic circuit is connected to delay circuit, transmission gating circuit and N type metal oxide semiconductor transistor, produces one first control signal in order to the output of foundation delay circuit.The second inverted logic circuit is connected to the first inverted logic circuit, P-type mos transistor and transmission gating circuit, in order to produce one second control signal, wherein transmit gating circuit and optionally open or turn-off according to first, second control signal according to the output of the first inverted logic circuit.
The transmission gating circuit can comprise: a N type metal oxide semiconductor transistor, its grid is connected to the transistorized grid of a N type metal oxide semiconductor, and wherein transistorized source electrode of a N type metal oxide semiconductor and drain electrode are connected respectively to second voltage level and transistorized P trap of the 2nd N type metal oxide semiconductor (P-Well) or substrate (body); One second P-type mos transistor, be parallel to the 2nd N type metal oxide semiconductor transistor, and its grid is connected to the grid of first P-type mos, and wherein transistorized source electrode of first P-type mos and drain electrode are connected respectively to first voltage level and the transistorized N trap of second P-type mos (N-Well).
According to above circuit, not only can be when esd pulse produce, the transmission gating circuit is turn-offed and is made that internal circuit and connection welding are completely cut off.Also can avoid producing unnecessary guiding path because of parasitization.
Description of drawings
Fig. 1 represents the ESD protection circuit of known technology.
Fig. 2 represents the ESD protection circuit of known technology.
Fig. 3 represents the preferred embodiment according to ESD protection circuit of the present invention.
The main element symbol description
100 ESD protection circuits
101 first rectifier cells
103 second rectifier cells
105 resistive elements
107 connection welding
109 internal circuits
200 ESD protection circuits
201 transmission gating circuits
203 control circuits
205 connection welding
207 electric capacity
209 resistance
211,213,215N type metal oxide semiconductor transistor
214P type metal oxide semiconductor transistor
300 ESD protection circuits
301 electric static discharge protectors
303 transmission gating circuits
305N type metal oxide semiconductor transistor
307P type metal oxide semiconductor transistor
309 delay circuits
311 first inverted logic circuit
313 second inverted logic circuit
315 connection welding
317,319 rectifier cells
321 outputs
323 internal circuits
325 electric capacity
327 resistance
329N type metal oxide semiconductor transistor
331P type metal oxide semiconductor transistor
Embodiment
In the middle of specification and follow-up claim, used some vocabulary to censure specific element.The person with usual knowledge in their respective areas should understand, and hardware manufacturer may be called same element with different nouns.This specification and follow-up claim are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function.Be an open term mentioned " comprising " in the middle of specification and the follow-up request in the whole text, so should be construed to " comprise but be not limited to ".In addition, " connection " speech comprises any indirect means that are electrically connected that directly reach at this.Therefore, be connected to one second device, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly through other devices or connection means if describe one first device in the literary composition.
Fig. 3 represents the ESD protection circuit 300 according to preferred embodiment of the present invention.As shown in Figure 3, ESD protection circuit 300 comprises: an electric static discharge protector 301, a transmission gating circuit 303, a N type metal oxide semiconductor transistor 305, a P-type mos transistor 307, a delay circuit 309, one first inverted logic circuit 311, one second inverted logic circuit 313.Electric static discharge protector 301 is connected to a connection welding 315, and electrostatic protection element 301 is made up of two rectifier cells 317 and 319 in this embodiment, and this two rectifier cell 317 and 319 can be made up of diode or metal oxide semiconductor transistor.Transmission gating circuit 303 be connected to connection welding 315 and an output 321 and in this embodiment output 321 be connected to an internal circuit 323, but this output 321 also can be connected to other circuit.N type metal oxide semiconductor transistor 305 (can be considered the semiconductor unit) is connected to transmission gating circuit 303 and one second voltage level VGND (i.e. a power line), is biased into transmission gating circuit 303 in order to provide one first.It is noted that the structure of transmission gating circuit 303 is not limited to structure shown in Figure 3 only in order to for example.
P-type mos transistor 307 (can be considered second half conductor element) then is connected to transmission gating circuit 303 and one first voltage level Vcc (another power line), is biased into transmission gating circuit 303 in order to provide one second according to the first voltage level Vcc.Delay circuit 309 is connected to electric static discharge protector 301, in order to turning on and off the time of decision transmission gating circuit 303.In this embodiment, delay circuit 309 comprises electric capacity 325 and a resistance 327, and utilizes the value of electric capacity 325 and resistance 327 to transmit turning on and off the time of gating circuit 303 with decision, but is not in order to limit the present invention.Electric capacity 325 and resistance 327 are connected in series with node C, and the signal on this node C promptly can be considered the detection signal of a static discharge.The first inverted logic circuit 311 is connected to delay circuit 309, transmission gating circuit 303 and N type metal oxide semiconductor transistor 305, produces one first control signal in order to the output (being detection signal) of foundation delay circuit 309.The second inverted logic circuit 313 is connected to the first inverted logic circuit 311, P-type mos transistor 307 and transmission gating circuit 303, in order to produce one second control signal CS2, wherein transmit gating circuit 303 and optionally open or turn-off according to first, second control signal CS1, CS2 according to the output of the first inverted logic circuit 311.
Transmission gating circuit 303 is a transmission gating (transmission gate), and comprises a N type metal oxide semiconductor transistor 329 and a P-type mos transistor 331, but is not in order to limit the present invention.As shown in Figure 3, the grid of N type metal oxide semiconductor transistor 329 (can be considered the first controlled end) is connected to the grid of N type metal oxide semiconductor transistor 325, and the source electrode of N type metal oxide semiconductor transistor 305 is connected respectively to the P trap (P-Well) or the substrate (body) of the second voltage level VGND and N type metal oxide semiconductor transistor 329 with drain electrode.P-type mos transistor 331 is parallel to N type metal oxide semiconductor transistor 329, and its grid (can be considered the second controlled end) is connected to the grid of this P-type mos 307, and wherein the source electrode of P-type mos transistor 307 and drain electrode are connected respectively to the N trap (N-Well) of the first voltage level Vcc and P-type mos transistor 331.And in this embodiment, the first inverted logic circuit 311 and the second inverted logic circuit 313 are inverter, but also can utilize other logical circuits to realize identical effect.
To illustrate below according to the operation situation of ESD protection circuit 300 under normal operation, PS (positiveto Vss) pattern, NS (negative to Vss) pattern, PD (positive to Vdd) pattern and ND (negative to Vdd) pattern.Under normal circumstances (that is not having esd pulse to produce), level from the first control signal CS1 of the output point A of the first inverted logic circuit 311 output be high, and the level of the second control signal CS2 that exports from the output point B of the second inverted logic circuit 312 is low.Therefore N type metal oxide semiconductor transistor 305, P-type mos transistor 307, N type metal oxide semiconductor transistor 329 and P-type mos transistor 331 are the state of conducting, have lower input impedance.
When esd pulse entered, if the PS pattern, then the lock point C of the first inverted logic circuit 311 was owing to see through the relation that electric capacity 325 is coupled to esd pulse, and its level is high, so the voltage of output point A is high for low output point B.Therefore N type metal oxide semiconductor transistor 305, P-type mos transistor 307, N type metal oxide semiconductor transistor 329 and P-type mos transistor 331 are for the state of shutoff, so esd pulse can't flow into internal circuit 323.In the case, esd pulse mainly is to be derived by rectifier cell 319, also can be derived by other peripheral auxiliary circuits.This peripheral auxiliary circuit is owing to known to those skilled in the art knowing, so do not repeat them here.
Under the NS pattern, rectifier cell 319 is switched on to derive esd pulse.Under the PD pattern, rectifier cell 317 is switched on to derive esd pulse.
And under the ND pattern, rectifier cell 319 is switched on, second voltage level is pulled to the voltage close with esd pulse, because esd pulse is a negative voltage, relatively first voltage level becomes high relatively level, the lock point C of inverted logic circuit 311 is connected to high relatively level simultaneously, therefore be height from the level of the control signal CS1 of output point A output for the level of low control signal CS2 from output point B output, so N type metal oxide semiconductor transistor 305, P-type mos transistor 307, N type metal oxide semiconductor transistor 329 and the state of P-type mos transistor 331 for turn-offing be not so esd pulse can flow into internal circuit 323.In the case, esd pulse mainly is to be derived by rectifier cell 317, also can be derived by other peripheral auxiliary circuits.This peripheral auxiliary circuit is owing to known to those skilled in the art knowing, so do not repeat them here.
According to the foregoing circuit structure, because P-type mos transistor 331 is not directly connected to delay circuit 309, therefore do not have situation about can't turn-off, and P-type mos transistor 307 can prevent the generation of parasitic path (for example being the NPN parasitic path).And this circuit does not use the LC resonant circuit, therefore can avoid potential oscillation problem, and the area aspect also can be adjusted by the grid width of adjusting the transmission gating circuit.
The above only is the preferred embodiments of the present invention, and all equivalences of carrying out according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.
Claims (13)
1. ESD protection circuit comprises:
One electric static discharge protector is connected to a connection welding;
One transmission gating circuit is connected to this connection welding and an output;
One N type metal oxide semiconductor transistor is connected to this transmission gating circuit and one second voltage level, in order to provide one first to be biased into this transmission gating circuit according to this second voltage level;
One first P-type mos transistor is connected to this transmission gating circuit and one first voltage level, in order to provide one second to be biased into this transmission gating circuit according to this first voltage level;
One delay circuit is connected to this electric static discharge protector, in order to determine turning on and off the time of this transmission gating circuit;
One first inverted logic circuit is connected to this delay circuit, this transmission gating circuit and this N type metal oxide semiconductor transistor, in order to produce one first control signal according to the output of this delay circuit; And
One second inverted logic circuit, be connected to this first inverted logic circuit, this P-type mos transistor and this transmission gating circuit, in order to produce one second control signal according to the output of this first inverted logic circuit, wherein this transmission gating circuit is optionally opened or is turn-offed according to this first, second control signal.
2. ESD protection circuit as claimed in claim 1, wherein this transmission gating circuit comprises:
One the 2nd N type metal oxide semiconductor transistor, its grid is connected to the transistorized grid of a N type metal oxide semiconductor, and wherein transistorized source electrode of a N type metal oxide semiconductor and drain electrode are connected respectively to this second voltage level and transistorized P trap of the 2nd N type metal oxide semiconductor or substrate; And
One second P-type mos transistor, be parallel to the 2nd N type metal oxide semiconductor transistor, and its grid is connected to the grid of this first P-type mos, and wherein transistorized source electrode of this first P-type mos and drain electrode are connected respectively to this first voltage level and the transistorized N trap of this second P-type mos.
3. ESD protection circuit as claimed in claim 1, wherein this electric static discharge protector comprises:
One first rectifier cell is connected between this delay circuit, this transmission gating circuit and this connection welding; And
One second rectifier cell is connected to this first rectifier cell and this second voltage level.
4. ESD protection circuit as claimed in claim 3, wherein this first rectifier cell or this second rectifier cell are diode or metal oxide semiconductor transistor.
5. ESD protection circuit as claimed in claim 1, wherein this delay circuit comprises:
One electric capacity is connected to this first voltage level and this electric static discharge protector; And
One resistance is connected to this first inverted logic circuit and this electric capacity.
6. ESD protection circuit as claimed in claim 1, wherein this first inverted logic circuit or this second inverted logic circuit are inverter.
7. an ESD protection circuit is used for protecting an internal circuit; This ESD protection circuit comprises:
One transmission gating circuit is connected between a connection welding and this internal circuit; This transmission gating circuit has one first controlled end and one second controlled end, and this transmission gating circuit is controlled between this connection welding and this internal circuit whether conducting according to the signal of this first controlled end and this second controlled end;
One delay circuit, whether it can detect electrostatic discharge event and take place and provide a detection signal according to testing result;
One first logical circuit is connected between this delay circuit and this first controlled end, and it can provide one first control signal to this first controlled end according to the detection signal of this delay circuit; And
One second logical circuit, it can provide one second control signal to this second controlled end according to this detection signal.
8. ESD protection circuit as claimed in claim 7, wherein this second logical circuit is connected between this first logical circuit and this second controlled end, to provide this second control signal according to this first control signal to this second controlled end.
9. ESD protection circuit as claimed in claim 7, wherein this transmission gating circuit also includes one first bias terminal and one second bias terminal, and this ESD protection circuit also includes:
One first semiconductor unit is connected between this first bias terminal and the second source line, and this first semiconductor unit can be controlled between this first bias terminal and this second source line whether conducting according to this first control signal; And
One second semiconductor unit is connected between this second bias terminal and one first power line, and this second semiconductor unit can be controlled the whether conducting of this second bias terminal and this first power line according to this second control signal.
10. ESD protection circuit as claimed in claim 9, wherein this transmission gating circuit includes two metal oxide semiconductor transistors, and this first and second bias terminal is respectively the substrate of this two metal oxide semiconductor transistor.
11. an ESD protection circuit is used for protecting an internal circuit; This ESD protection circuit comprises:
One transmission gating circuit is connected between a connection welding and this internal circuit, whether conducting between this connection welding of its may command and this internal circuit; This transmission gating circuit has one first bias terminal and one second bias terminal;
One delay circuit, whether it can detect electrostatic discharge event and take place and provide a detection signal according to testing result;
One first logical circuit is connected to this delay circuit, and it can provide one first control signal according to the detection signal of this delay circuit;
One second logical circuit, it can provide one second control signal according to this detection signal;
One first semiconductor unit is connected between this first bias terminal and the second source line, and this first semiconductor unit can be controlled between this first bias terminal and this second source line whether conducting according to this first control signal; And
One second semiconductor unit is connected between this second bias terminal and one first power line, and this second semiconductor unit can be controlled the whether conducting of this second bias terminal and this first power line according to this second control signal.
12. as the ESD protection circuit of claim 11, wherein this second logical circuit is connected between this first logical circuit and this second controlled end, to provide this second control signal according to this first control signal.
13. as the ESD protection circuit of claim 11, wherein this transmission gating circuit includes two metal oxide semiconductor transistors, and this first and second bias terminal is respectively the substrate of this two metal oxide semiconductor transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101642951A CN100568659C (en) | 2006-12-08 | 2006-12-08 | ESD protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101642951A CN100568659C (en) | 2006-12-08 | 2006-12-08 | ESD protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101197500A true CN101197500A (en) | 2008-06-11 |
| CN100568659C CN100568659C (en) | 2009-12-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101642951A Expired - Fee Related CN100568659C (en) | 2006-12-08 | 2006-12-08 | ESD protection circuit |
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| Country | Link |
|---|---|
| CN (1) | CN100568659C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106533419A (en) * | 2016-10-12 | 2017-03-22 | 格科微电子（上海）有限公司 | ESD protection circuit and clock path of MIPI interface |
| CN106899011A (en) * | 2015-12-18 | 2017-06-27 | 中芯国际集成电路制造（天津）有限公司 | Electrostatic discharge protective circuit |
| CN113451293A (en) * | 2020-03-26 | 2021-09-28 | 长鑫存储技术有限公司 | Electrostatic discharge protection circuit |
-
2006
- 2006-12-08 CN CNB2006101642951A patent/CN100568659C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106899011A (en) * | 2015-12-18 | 2017-06-27 | 中芯国际集成电路制造（天津）有限公司 | Electrostatic discharge protective circuit |
| CN106899011B (en) * | 2015-12-18 | 2019-01-18 | 中芯国际集成电路制造（天津）有限公司 | Electrostatic discharge protective circuit |
| CN106533419A (en) * | 2016-10-12 | 2017-03-22 | 格科微电子（上海）有限公司 | ESD protection circuit and clock path of MIPI interface |
| CN106533419B (en) * | 2016-10-12 | 2022-11-01 | 格科微电子（上海）有限公司 | ESD protection circuit and clock path of MIPI interface |
| CN113451293A (en) * | 2020-03-26 | 2021-09-28 | 长鑫存储技术有限公司 | Electrostatic discharge protection circuit |
| WO2021190286A1 (en) * | 2020-03-26 | 2021-09-30 | 长鑫存储技术有限公司 | Electrostatic discharge protection circuit |
| CN113451293B (en) * | 2020-03-26 | 2022-05-27 | 长鑫存储技术有限公司 | Electrostatic discharge protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100568659C (en) | 2009-12-09 |
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