TWI604677B - Cross-domain esd protection circuit - Google Patents

Description

Electrostatic discharge protection circuit across the power domain

The invention relates to an electrostatic discharge protection circuit, in particular to an electrostatic discharge protection circuit across a power supply domain.

Electrostatic discharge protection circuits are often placed in parallel with other circuits in integrated circuits to provide a discharge path in parallel with other circuits. In order to reduce the circuit area, the capacitor used in the conventional ESD protection circuit is mostly realized by a MOS capacitor.

However, in many advanced semiconductor processes, MOS capacitors are prone to gate leakage due to the thinner and thinner gate oxide thickness. As a result, the ESD protection circuit may cause a malfunction during the normal operation of other circuits, causing the integrated circuit to malfunction or fail to operate normally.

In view of this, how to effectively avoid the accidental operation of the electrostatic discharge protection circuit due to the gate leakage current of the MOS capacitor is a problem to be solved in the industry.

The present specification provides an embodiment of an ESD protection circuit across a power domain, comprising: a first current path switch on a first current path between a first power terminal and a first fixed potential terminal, in parallel The first circuit is configured to be turned off when the first node voltage is at a logic high level; a first node is coupled to a control end of the first current path switch for providing the first node voltage a first resistance element coupled between the first power terminal and the first node; a first MOS capacitor, coupled Connected between the first node and the first fixed potential terminal, and configured to charge when the first node voltage is at a logic high level; a second current path switch located at a second power terminal and a second a second current path between the fixed potential terminals, parallel to a second circuit, and controlled by a second node voltage; a switch control circuit coupled to the second power terminal and the second fixed potential terminal Between the second node voltage, and a node voltage control circuit coupled to the first power terminal, the first node, and the switch control circuit, configured to supply power to the first power terminal When the first circuit and the second power terminal supply power to the second circuit, the magnitude of the first node voltage is controlled according to the second node voltage to ensure that the first current path switch is maintained in an off state.

One of the advantages of the above embodiment is that even if the first MOS capacitor has a gate leakage current, the node voltage control circuit can control the magnitude of the first node voltage according to the second node voltage provided by the switch control circuit to ensure The first current path switch does not malfunction.

Another advantage of the above embodiments is that a more advanced semiconductor process technology can be employed to fabricate the first MOS capacitor to minimize the circuit area of the first MOS capacitor.

Other advantages of the invention will be explained in more detail in conjunction with the following description and drawings.

100,200‧‧‧ ESD protection circuit

101‧‧‧first power terminal

102‧‧‧first fixed-voltage terminal

103‧‧‧second power terminal

104‧‧‧second fixed-voltage terminal

105‧‧‧first circuit

106‧‧‧second circuit

110‧‧‧First current path switch

121‧‧‧first node

123‧‧‧first resister element

125‧‧‧First MOS capacitor

130‧‧‧second current path switch

140‧‧‧switch control circuit

141‧‧‧second node

143‧‧‧second resister element

145‧‧‧Second MOS capacitor

150‧‧‧node voltage control circuit

151‧‧‧First bypass switch

153‧‧‧second bypass switch

1 is a simplified functional block diagram of an ESD protection circuit according to a first embodiment of the present invention.

2 is a simplified functional block diagram of an ESD protection circuit according to a second embodiment of the present invention.

Embodiments of the present invention will be described below in conjunction with the associated drawings. In the drawings, the same reference numerals indicate the same or similar elements or methods.

1 is a simplified functional block diagram of an electrostatic discharge protection circuit 100 according to a first embodiment of the present invention. The right side of Figure 1 shows a first power located in the first power domain The source terminal 101, a first fixed potential terminal 102, and a first circuit 105 coupled between the first power terminal 101 and the first fixed potential terminal 102. The left side of FIG. 1 shows a second power terminal 103, a second fixed potential terminal 104, and a second coupling between the second power terminal 103 and the second fixed potential terminal 104. Two circuits 106. The first circuit 105 represents an unspecified circuit that may face an electrostatic discharge shock in the first power domain, while the second circuit 106 represents an unspecified circuit that may face an electrostatic discharge shock in the second power domain.

The first power terminal 101 is configured to provide a first operating voltage VDD1 required for the operation of the first circuit 105, and the second power terminal 103 is configured to provide a second operating voltage VDD2 required for the operation of the second circuit 106, and the first operating voltage VDD1 It is not the same as the second operating voltage VDD2. The first fixed potential terminal 102 is coupled to a first fixed potential GND1, and the second fixed potential terminal 104 is coupled to a second fixed potential GND2. In practice, the first fixed potential GND1 and the second fixed potential GND2 may be the same potential (for example, 0V), or may be different.

The ESD protection circuit 100 can be used to protect the first circuit 105 and the second circuit 106. The first power supply terminal 101 and the first fixed potential terminal 102 are coupled to the second power terminal 103 and the second fixed potential terminal 104 in the second power domain. Therefore, the ESD protection circuit 100 is a circuit that is connected across two different power domains.

As shown in FIG. 1 , the ESD protection circuit 100 includes a first current path switch 110 , a first node 121 , a first resistance element 123 , a first MOS capacitor 125 , and a second current path switch 130 . A switch control circuit 140 and a node voltage control circuit 150.

The first current path switch 110 is located at a first power terminal 101 and a first fixed potential terminal. a first current path between 102, parallel to the first circuit 105, and arranged to turn off when the first node voltage V1 is at a logic high level, and at the first node The voltage V1 is turned on when it is at a logic low level. The first node 121 is coupled to a control end of the first current path switch 110 for providing the first node voltage V1. The first resistance element 123 is coupled between the first power terminal 101 and the first node 121. The first MOS capacitor 125 is coupled between the first node 121 and the first fixed potential terminal 102 and is configured to be charged when the first node voltage V1 is at a logic high level.

The second current path switch 130 is located on a second current path between a second power terminal 103 and a second fixed potential terminal 104, is connected in parallel to the second circuit 106, and is controlled by a second node voltage V2. The switch control circuit 140 is coupled between the second power terminal 103 and the second fixed potential terminal 104 for providing the second node voltage V2.

The node voltage control circuit 150 is coupled to the first power terminal 101, the first node 121, and the switch control circuit 140, and is configured to control the magnitude of the first node voltage V1 and/or the second node voltage V2 to ensure the first current path. The switch 110 and/or the second current path switch 130 does not malfunction and affects the normal operation of the first circuit 105 and the second circuit 106.

In one embodiment, the switch control circuit 140 includes a second node 141, a second resistive element 143, and a second MOS capacitor 145 in series. The node voltage control circuit 150 includes a first bypass switch 151 and a second bypass switch 153.

When the first circuit 105 and the second circuit 106 do not need to operate, the first power terminal 101 and the second power terminal 103 can stop supplying power. At this time, both the first current path switch 110 and the second current path switch 130 should be maintained in an on state, so that the first current path and the second current path with lower impedance form a short circuit for static electricity. When the discharge event occurs, it becomes a path of current venting, thereby avoiding the first circuit 105 and the second circuit 106 Damaged by electrostatic discharge shock.

On the other hand, when the first circuit 105 and the second circuit 106 are to be normally operated, the first power terminal 101 supplies power to the first circuit 105, and the second power terminal 103 supplies power to the second circuit 106. Ideally, both the first current path switch 110 and the second current path switch 130 should be maintained in an off state at this time, so that both the first current path and the second current path form an open circuit for the first power source. The current supplied from the terminal 101 can flow correctly to the first circuit 105, and the current supplied from the second power terminal 103 can flow correctly to the second circuit 106.

In the ESD protection circuit 100, the second current path switch 130 is set to turn off when the second node voltage V2 is at a logic low level and is turned on when the second node voltage V2 is at a logic high level. The second node 141 is coupled to a control end of the second current path switch 130 for providing the second node voltage V2. The second resistance element 143 is coupled between the second node 141 and the second fixed potential terminal 104. The second MOS capacitor 145 is coupled between the second power terminal 103 and the second node 141 and is configured to be charged when the second node voltage V2 is at a logic low level.

The first bypass switch 151 is located on a first bypass path in parallel with the first resistive element 123 and is arranged to be turned on when the second node voltage V2 is at a logic low level. The second bypass switch 153 is located on the second bypass path in parallel with the second resistive element 143 and is arranged to be turned on when the first node voltage V1 is at a logic high level. In the embodiment of FIG. 1 , the first end of the first bypass switch 151 is coupled to the first power terminal 101 , the second end of the first bypass switch 151 is coupled to the first node 121 , and the first bypass switch The control end of the 151 is coupled to the second node 141. The second end of the second bypass switch 153 is coupled to the second node 141, the second end of the second bypass switch 153 is coupled to the second fixed potential end 104, and the control end of the second bypass switch 153 is coupled At the first node 121.

When the first power terminal 101 and the second power terminal 103 respectively supply the first circuit 105 and the second circuit 106, the first node voltage V1 initially provided by the first node 121 will be at a logic high level, and the second node 141 initially The provided second node voltage V2 will be at a logic low level. At this time, the first bypass switch 151 is turned on by the second node voltage V2, and the second bypass switch 153 is turned on by the first node voltage V1, so that the first bypass path and the second bypass path are both Form a pathway. Therefore, the first node voltage V1 is locked at a logic high level, and the second node voltage V2 is locked at a logic low level.

Thereafter, even if the first MOS capacitor 125 has a gate leakage current, the first node voltage V1 is not pulled low to a logic low. On the other hand, even if the second MOS capacitor 145 has a gate leakage current, the second node voltage V2 is not raised to a logic high level.

In this way, when the first circuit 105 and the second circuit 106 are in normal operation, the node voltage control circuit 150 in FIG. 1 can effectively prevent the first current path switch 110 from leaking due to the gate current of the first MOS capacitor 125. The problem is erroneously turned on, and it is also effective to prevent the second current path switch 130 from being erroneously turned on due to the gate leakage current problem of the second MOS capacitor 145.

Please refer to FIG. 2, which is a simplified functional block diagram of the ESD protection circuit 200 according to the second embodiment of the present invention.

In the ESD protection circuit 200, the second current path switch 130 is set to turn off when the second node voltage V2 is at a logic high level, and to turn on when the second node voltage V2 is at a logic low level. The second node 141 is coupled to a control end of the second current path switch 130 for providing the second node voltage V2. The second resistance element 143 is coupled between the second power terminal 103 and the second node 141. The second MOS capacitor 145 is coupled between the second node 141 and the second fixed potential terminal 104, and is disposed at the second node voltage V2. Charging when the logic is high.

The first bypass switch 151 is located on the first bypass path in parallel with the first resistive element 123 and is arranged to be turned on when the second node voltage V2 is at a logic high level. The second bypass switch 153 is located on the second bypass path in parallel with the second resistive element 143 and is arranged to be turned on when the first node voltage V1 is at a logic high level. In the embodiment of FIG. 2, the first end of the first bypass switch 151 is coupled to the first power terminal 101, the second end of the first bypass switch 151 is coupled to the first node 121, and the first bypass is The control end of the switch 151 is coupled to the second node 141. The second end of the second bypass switch 153 is coupled to the second power terminal 103, the second end of the second bypass switch 153 is coupled to the second node 141, and the control end of the second bypass switch 153 is coupled to The first node 121.

When the first power terminal 101 and the second power terminal 103 respectively supply the first circuit 105 and the second circuit 106, the first node voltage V1 initially provided by the first node 121 will be at a logic high level, and the second node 141 initially The second node voltage V2 provided is also at a logic high. At this time, the first bypass switch 151 is turned on by the second node voltage V2, and the second bypass switch 153 is turned on by the first node voltage V1, so that the first bypass path and the second bypass path are both Form a pathway. Therefore, the first node voltage V1 is locked at a logic high level, and the second node voltage V2 is also locked at a logic high level.

Thereafter, even if the first MOS capacitor 125 has a gate leakage current, the first node voltage V1 is not pulled low to a logic low. On the other hand, even if the second MOS capacitor 145 has a gate leakage current, the second node voltage V2 is not pulled low to a logic low.

In this way, when the first circuit 105 and the second circuit 106 are in normal operation, the node voltage control circuit 150 in FIG. 2 can effectively prevent the first current path switch 110 from leaking due to the gate current of the first MOS capacitor 125. The problem is erroneously turned on and can also be effective The second current path switch 130 is prevented from being erroneously turned on due to the gate leakage current problem of the second MOS capacitor 145.

It can be seen from the foregoing description that even if the first MOS capacitor 125 and the second MOS capacitor 145 have a gate leakage current, the node voltage control circuit 150 can effectively lock the first node voltage V1 and the second node voltage V2. The correct logic potential is to ensure that the first current path switch 110 and the second current path switch 130 do not malfunction. Therefore, the first metal oxide semiconductor capacitor 125 and the second metal oxide semiconductor capacitor 145 can be fabricated by using a more advanced semiconductor process technology to minimize the circuit area of the first metal oxide semiconductor capacitor 125 and the second metal oxide semiconductor capacitor 145. . In this way, the circuit area of the ESD protection circuit 100 or 200 can be minimized.

In the foregoing embodiments, any one of the first current path switch 110, the second current path switch 130, the first bypass switch 151, and the second bypass switch 153 is set to correspond to When the node voltage is turned on at a logic high level (that is, turned off when the corresponding node voltage is at a logic low level), the single N-type MOS transistor can be used to implement the switching device, or The switching device is implemented by a combination of an N-type MOS transistor and an even number of inverters connected in series to the gate of the N-type MOS transistor. Alternatively, the switching device may be implemented by a combination of a P-type MOS transistor and an odd number of inverters connected in series to the gate of the P-type MOS transistor.

If a single switch is set to be turned on when the corresponding node voltage is at a logic low level (ie, turned off when the corresponding node voltage is at a logic high level), then a single P-type MOS semiconductor can be used. The switching device is implemented by a crystal to achieve the switching device, or a combination of a P-type MOS transistor and an even number of inverters connected in series to the gate of the P-type MOS transistor. Alternatively, an N-type gold oxide half can also be used. The switching device is realized by a combination of a conductor transistor and an odd number of inverters connected in series to the gate of the N-type MOS transistor.

In the foregoing embodiments, if any of the first MOS capacitor 125 and the second MOS capacitor 145 is configured to be charged when the corresponding node voltage is at a logic high level, one can be used. a single N-type MOS transistor to implement the body of the capacitor device, or a combination of an N-type MOS transistor and an even number of inverters connected in series with the gate of the N-type MOS transistor The body of the capacitive device is implemented. Alternatively, the body of the capacitive device may be implemented by a combination of a P-type MOS transistor and an odd number of inverters connected in series to the gate of the P-type MOS transistor.

If any of the foregoing capacitive devices are arranged to be charged when the corresponding node voltage is at a logic low level, the body of the capacitive device can be implemented with a single P-type MOS transistor, or a P-type gold can be used. The body of the capacitive device is implemented by a combination of an oxy-semiconductor transistor and an even number of inverters connected in series to the gate of the P-type MOS transistor. Alternatively, the body of the capacitive device may be implemented by a combination of an N-type MOS transistor and an odd number of inverters connected in series to the gate of the N-type MOS transistor.

Please note that the foregoing architectures of the ESD protection circuits 100 and 200 are merely a few exemplary embodiments and are not intended to limit the actual implementation of the invention. For example, in some embodiments, the second MOS capacitor 145 in the switch control circuit 140 can also be implemented by using other processes in which the gate oxide layer is thicker and does not cause gate leakage current problems. In addition, in some applications in which the second MOS capacitor 145 does not generate a gate leakage current, or the gate leakage current has other circuit architectures, the second of the node voltage control circuits 150 may be used. The bypass switch 153 is omitted to simplify the architecture of the circuit.

Certain terms are used throughout the description and claims to refer to particular elements, and those skilled in the art may refer to the same elements. This specification and the scope of the patent application do not use the difference in the name as the means for distinguishing the elements, but the difference in function of the elements as the basis for the distinction. The term "including" as used in the specification and the scope of the patent application is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect means of attachment. Therefore, if the first element is described as being coupled to the second element, the first element may be directly connected to the second element by electrical connection or by wireless transmission, optical transmission, or the like, or by other elements or connections. The means is indirectly electrically or signally connected to the second component.

The description of "and/or" used in the specification includes any one of the listed items or any combination of items. In addition, the terms of any singular are intended to include the meaning of the plural, unless otherwise specified in the specification.

The above are only the preferred embodiments of the present invention, and equivalent changes and modifications made to the claims of the present invention are intended to be within the scope of the present invention.

100‧‧‧Electrostatic discharge protection circuit

101‧‧‧First power terminal

102‧‧‧First fixed potential end

103‧‧‧second power terminal

104‧‧‧second fixed potential end

105‧‧‧First circuit

106‧‧‧Second circuit

110‧‧‧First current path switch

121‧‧‧first node

123‧‧‧First resistance element

125‧‧‧First MOS Capacitor

130‧‧‧Second current path switch

140‧‧‧Switch Control Circuit

141‧‧‧second node

143‧‧‧second resistance element

145‧‧‧Second MOS capacitor

150‧‧‧node voltage control circuit

151‧‧‧First bypass switch

153‧‧‧Second bypass switch

Claims (5)

An ESD protection circuit (100; 200) across a power domain includes: a first current path switch (110) located between a first power supply terminal (101) and a first fixed potential terminal (102) The first current path is parallel to a first circuit (105) and is set to be turned off when the first node voltage (V1) is at a logic high level; a first node (121) coupled to the first a control terminal of the current path switch (110) for providing the first node voltage (V1); a first resistance component (123) coupled to the first power terminal (101) and the first node (121) a first MOS capacitor (125) coupled between the first node (121) and the first fixed potential terminal (102) and disposed at the first node voltage (V1) Charging is performed at a logic high level; a second current path switch (130) is located on a second current path between a second power supply terminal (103) and a second fixed potential terminal (104), and is connected in parallel The second circuit (106) is controlled by a second node voltage (V2); a switch control circuit (140) coupled to the second power terminal (103) and the second fixed potential terminal ( Between 104) for providing the second node voltage (V2); and a node voltage control circuit (150) coupled to the first power terminal (101), the first node (121), and the switch a control circuit (140) configured to supply power to the first circuit (105) at the first power terminal (101) and to supply the second circuit (106) to the second circuit (106) The node voltage (V2) controls the magnitude of the first node voltage (V1) to ensure that the first current path switch (110) remains in the off state. The ESD protection circuit (100; 200) of claim 1, wherein the second current path switch (130) is set to be turned off when the second node voltage (V2) is at a logic low level, The switch control circuit (140) includes: a second node (141) coupled to a control end of the second current path switch (130) for providing the second node voltage (V2); The second resistive component (143) is coupled between the second node (141) and the second fixed potential terminal (104); and a second MOS capacitor (145) coupled to the second power terminal And (103) is disposed between the second node (141) and configured to perform charging when the second node voltage (V2) is at a logic low level; wherein the node voltage control circuit (150) includes: a first The bypass switch (151) is located on a first bypass path in parallel with the first resistive element (123) and is arranged to be turned on when the second node voltage (V2) is at a logic low level. The electrostatic discharge protection circuit (100; 200) of claim 2, wherein the node voltage control circuit (150) further comprises: a second bypass switch (153) located at the second resistive element (143) And a second bypass path connected in parallel and arranged to be turned on when the first node voltage (V1) is at a logic high level. The ESD protection circuit (100; 200) of claim 1, wherein the second current path switch (130) is set to be turned off when the second node voltage (V2) is at a logic high level, and the switch The control circuit (140) includes: a second node (141) coupled to a control end of the second current path switch (130) for providing the second node voltage (V2); a second resistance element (143) coupled between the second power terminal (103) and the second node (141); a second MOS capacitor (145) coupled between the second node (141) and the second fixed potential terminal (104), and configured to be at a logic high level at the second node voltage (V2) Charging at a time; wherein the node voltage control circuit (150) includes: a first bypass switch (151) located on a first bypass path in parallel with the first resistive element (123), and configured to Turns on when the second node voltage (V2) is at a logic high level. The ESD protection circuit (100; 200) of claim 4, wherein the node voltage control circuit (150) further comprises: a second bypass switch (153) located at the second resistive element (143) And a second bypass path connected in parallel and arranged to be turned on when the first node voltage (V1) is at a logic high level.