TWI464858B - Esd protection circuit with merged triggering mechanism - Google Patents

Description

Electrostatic discharge protection circuit with combined trigger mechanism

The present invention relates to an electrostatic discharge protection circuit, and more particularly to an electrostatic discharge protection circuit that can save area and prevent leakage current.

FIG. 1 illustrates a prior art electrostatic discharge protection (ESD protection) circuit 100. As shown in FIG. 1, the electrostatic discharge protection circuit 100 of the prior art may include electrostatic discharge protection elements 101, 103, trigger circuits 107, 109, and an electrostatic discharge detection circuit 111, the main purpose of which is to avoid the generation of an electrostatic discharge voltage. Direct input from the input/output pad 113 to the internal circuit 105 causes damage to the internal circuit 105. The operation principle of the ESD protection circuit 100 can be briefly described as follows: When the ESD detection circuit 111 detects the ESD voltage generation, a control signal is generated to control the trigger circuits 107 and 109, and the trigger circuits 107 and 109 trigger. The electrostatic discharge protection element 101 or 103 allows the electrostatic discharge protection element 101 or 103 to direct the electrostatic discharge current for the purpose of protecting the internal circuit 105.

However, the trigger circuit 107 typically occupies a relatively large area, and in this configuration, each ESD protection component must be coupled to a trigger circuit. Therefore, the trigger circuit will occupy a considerable area. In addition, in order to reduce the complexity and manufacturing cost of the wafer, the electrostatic discharge detecting circuit and the trigger circuit are usually implemented as an element having a thin oxide layer. As a result, there may be leakage current I _LEA flowing along the path shown in FIG. 1 to the voltage V _ss , resulting in insufficient voltage across the capacitor in the ESD circuit, which affects the role in the ESD protection circuit. When the internal circuit 105 is in normal operation, the leakage current causes additional power consumption.

It is an object of the present invention to provide an electrostatic discharge protection circuit that can save the area of the trigger circuit.

Another object of the present invention is to provide an electrostatic discharge protection circuit that can reduce leakage current.

An embodiment of the present invention discloses an electrostatic discharge protection circuit including an electrostatic discharge detection circuit, a first type of electrostatic discharge protection component, a second type of electrostatic discharge protection component, and a trigger circuit. The electrostatic discharge detecting circuit is configured to detect an electrostatic discharge voltage to generate a control signal. The first type of electrostatic discharge protection component is configured to output a first trigger current. The second type of electrostatic discharge protection component is configured to receive a second trigger current. The trigger circuit is configured to form a conduction path according to the control signal to receive the first trigger current from the first type electrostatic discharge protection component and output a second trigger current to the second type electrostatic discharge protection component.

In addition, the ESD protection circuit may further include a first switch and a second switch, and the first switch determines whether to turn on the first type electrostatic discharge protection component and the second type electrostatic discharge protection component according to the control signal, and the second switch is controlled according to the control. The signal determines whether the first voltage level, the second voltage level, and the electrostatic discharge detecting circuit form a conduction path.

According to the above embodiments, the ESD protection circuit according to the embodiment of the present invention can save the area of the flip-flop circuit, and can further provide a structure for reducing leakage current. Therefore, the problem of the electrostatic discharge protection circuit of the prior art can be improved.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

FIG. 2 illustrates an ESD protection circuit 200 that can save a trigger circuit area in accordance with an embodiment of the present invention. In this embodiment, the electrostatic discharge protection element is implemented with an N-type 矽-controlled rectifier and a P-type 矽-controlled rectifier, but is not intended to limit the invention. As shown in FIG. 2, the ESD protection circuit 200 includes an N-type 矽-controlled rectifier 201, a P-type 矽-controlled rectifier 203, a trigger circuit 205, and an ESD detection circuit 207. Please note that the internal circuit described in FIG. 1 is omitted and not shown for convenience of explanation. The ESD detecting circuit 207 is configured to detect an ESD voltage to generate a control signal CS. The N-type pilot rectifier 201 is configured to output a first trigger current I _tri1 ; the N-type pilot rectifier 201 can be triggered between the two ends via the first trigger current I _tri1 (that is, the supply potential V _DD and the input / The output pads 208 are electrically connected to a conduction path. The P-type pilot rectifier 203 is configured to receive a second trigger current I _tri2 ; and via the triggering of the second trigger current, the P-type _PWM rectifier 203 can be between the two ends thereof (ie, the input/output pad 208 and the ground potential V Between _SS ) conducts a conduction path. The trigger circuit 205 is configured to form a conduction path according to the control signal CS to receive the first trigger current I _tri1 from the N-type _PWM rectifier 201 and output the second trigger current I _tri2 to the P-type _PWM rectifier 203. In an embodiment, the first trigger current I _tri1 and the second trigger current I _tri2 have the same current value; in other words, in an embodiment of the invention, the trigger circuit 205 can trigger the step-controlled rectifier 201 The current is transferred to another pilot rectifier 203, which triggers two pilot rectifiers with a single trigger circuit 205. Under this architecture, only one trigger circuit is needed to trigger more than one ESD protection component. This mechanism is called a combined trigger mechanism, which saves the area occupied by the trigger circuit. The current values of the first trigger current I _tri1 and the second trigger current I _tri2 may be adjusted to other values according to the trigger current required by the step-controlled rectifier; basically, the step-controlled rectifiers 201 and 203 may have different thresholds. The current is turned on, and the trigger circuit 205 can be combined by the controlled rectifier 201 and transmitted to the other controlled rectifier 203 as long as a sufficiently large current (for example, a threshold current greater than the threshold rectifiers 201 and 203) can be extracted. Trigger both. Moreover, in the block diagram shown in FIG. 2, the trigger circuit 205 is not coupled to the supply potential V _DD and the ground potential V _SS , but the trigger circuit 205 can also be coupled to the supply potential V _DD and the ground potential V _SS . In addition, the trigger circuit 205 and the electrostatic discharge detecting circuit 207 can be integrated into a composite circuit 209.

Figs. 3 and 4 respectively show an example of the detailed structure of the electrostatic discharge protection circuit shown in Fig. 2. In the embodiment shown in FIG. 3, the electrostatic discharge detecting circuit 207 has a resistor 301 and a capacitor 303. The flip-flop circuit 205 in FIG. 3 includes a first NMOS 305 and an inverter 307. The first NMOS 305 has a drain coupled to the N-type controlled rectifier 201 and a source coupled to the P-type controlled rectifier 203. The inverter 307 has an output coupled to one of the gates of the first NMOS 305 and has an input coupled to the second end of the resistor 301.

The supply potential V _DD and the ground potential V _SS are used as the supply voltage of the inverter 307. Normally, the supply potential V _DD charges the capacitor 303. Therefore, the voltage level at point A is HIGH and the voltage level at point B is LOW, and the first NMOS 305 is in a non-conducting state. Conversely, when the electrostatic discharge voltage is generated, since the capacitor 303 cannot be charged quickly, the voltage level at point A is LOW and the voltage level at point B is HIGH, and the first NMOS 305 is in an on state. The N-type 矽-controlled rectifier 201 and the P-type 矽-controlled rectifier 203 are respectively triggered to be turned on by receiving a negative current and a positive current, respectively, and triggering the formed conduction path to derive the electrostatic discharge current, thereby preventing the electrostatic discharge current from damaging the internal circuit.

In Fig. 4, the electrostatic discharge detecting circuit 207 also has a resistor 401 and a capacitor 403, but its position is opposite to that of the resistor 301 and the capacitor 303 of Fig. 3. Further, the first NMOS 305 of FIG. 3 is replaced by the first PMOS 405. In the example shown in Figure 4, the supply potential V _DD will normally charge the capacitor 403. The voltage level at point A will be LOW, and the voltage level at point B will be HIGH. Therefore, the first PMOS 405 will Presents a non-conducting state. Conversely, when the electrostatic discharge voltage is generated, the voltage level at point A is HIGH and the voltage level at point B is LOW, so the first PMOS 405 is in an on state. The N-type 矽-controlled rectifier 201 and the P-type 矽-controlled rectifier 203 are respectively triggered by receiving a negative current and a positive current, and the electrostatic discharge current is derived after the triggering, thereby preventing the electrostatic discharge current from damaging the internal circuit.

5 to 7 illustrate the detailed structure of an electrostatic discharge protection circuit capable of preventing leakage current according to an embodiment of the present invention. Compared with the embodiment shown in FIGS. 2 to 4, the embodiment shown in FIGS. 5 to 7 includes, in addition to the structure for reducing the area of the trigger circuit shown in FIGS. 2 to 4, A structure that prevents leakage current. In the fifth to seventh embodiments, the electrostatic discharge detecting circuit and the trigger circuit can be further integrated into a composite circuit, which has the functions of an electrostatic discharge detecting circuit and a trigger circuit, and has a structure for preventing leakage current. In the electrostatic discharge protection circuit 500 shown in FIG. 5(a), the composite circuit 501 includes a second NMOS 503 in addition to the resistor 301, the capacitor 303, the first NMOS 305, and the inverter 307. . Therefore, when the first NMOS 305 is not turned on, the second NMOS 503 is also not turned on, so that leakage current can be prevented from being generated. For example, when normal operation is performed under normal conditions, the second NMOS 503 that is turned off will cut off the leakage path of the capacitor 303 to the ground potential V _SS to prevent the leakage current from being continuously turned on to consume power. Similarly, the electrostatic discharge protection circuit 500 shown in FIG. 5(b) further includes a second PMOS 505 compared to FIG. 4, so when the first PMOS 405 is not turned on, the second PMOS 505 It is also not conductive, so it can prevent leakage current.

The concepts of the embodiments shown in Figures 5(a) and 5(b) can be as follows: The ESD protection circuit includes a first switch (first NMOS 305 or first PMOS 405) and a second switch ( The second NMOS 503 or the second PMOS 505), the first switch determines whether to turn on the first type of electrostatic discharge protection component (N-type controlled rectifier 201) and the second type of electrostatic discharge protection component according to the control signal (P-type control) The rectifier 203) determines, according to the control signal, whether to make the first voltage level (such as the supply potential V _DD ), the second voltage level (such as the ground potential V _SS ), and the electrostatic discharge detecting circuit form a conduction path.

6 to 7 illustrate the detailed structure of an electrostatic discharge protection circuit capable of preventing leakage current according to an embodiment of the present invention. The common concept of the ESD protection circuits 600 and 700 is to reduce the cross-over voltage of the composite circuit capacitor, thereby improving the leakage current. In the ESD protection circuit 600 shown in FIG. 6, the composite circuit 601 includes a first PMOS 603, a first NMOS 605, a first resistor 607, a capacitor 609, a second resistor 611, and a second PMOS. 613, a second NMOS 615 and a third NMOS 617. The first PMOS 603 has a source coupled to the supply potential V _DD and a gate coupled to the N-type pilot rectifier 201. The first NMOS 605 has a gate coupled to the N-type pilot rectifier 201 and a drain coupled to one of the drains of the first PMOS 603. The first resistor 607 has a first end coupled to a source of the first NMOS 605 and a second end coupled to the ground potential V _SS . The second PMOS 613 has a gate coupled to one of the supply potential V _DD and coupled to one of the drains of the first PMOS 603 , and a drain coupled to one of the N-type controlled rectifiers 201 . The second NMOS 615 has a drain coupled to the drain of the second PMOS 613 and a gate coupled to the drain of the first PMOS 603. The capacitor 609 has a first end coupled to the gate of the second NMOS 615. The third NMOS 617 has a drain coupled to one of the sources of the second NMOS 615, a gate coupled to the second end of the capacitor, and a source coupled to the P-type controlled rectifier 203. The second resistor 611 has a first end coupled to the gate of the third NMOS 617 and a second end coupled to the ground potential V _SS .

The operation of the ESD protection circuit 600 shown in FIG. 6 can be briefly described as follows: in normal operation, the second PMOS 613 is turned on and the voltage level at point B is HIGH, and by the feedback mechanism, point A The voltage level is pulled down to LOW. As a result, the voltage across the capacitor 609 is reduced, and the second NMOS 615 and the third NMOS 617 are effectively turned off. Therefore, the leakage path is cut off to reduce leakage current. The situation.

The action concept of the ESD protection circuit 700 shown in FIG. 7 is similar to that of the ESD protection circuit 600, but the ESD protection circuit 700 replaces the two NMOS and one PMOS of the ESD protection circuit 600 with two PMOSs and one NMOS. Moreover, the positions of the resistors and capacitors in the composite circuit are different. The composite circuit 701 in the ESD detection circuit 700 includes a first PMOS 703, a first NMOS 705, a first resistor 707, a capacitor 709, a second resistor 711, a second PMOS 713, and a second A PMOS 715 and a second NMOS 717. The first PMOS 703 has a gate coupled to the P-type pilot rectifier 203. The first NMOS 705 has a gate coupled to the P-type controlled rectifier 203, a drain coupled to one of the first PMOS 703, and a source coupled to the ground potential VSS. The first resistor 707 has a second end coupled to one of the first end of the supply potential V _DD and one of the sources of the first PMOS 705.

The second resistor 711 has a first end coupled to the supply potential V _DD . The second PMOS 713 has a source coupled to one of the N-type pilot rectifiers 203 and a gate coupled to the second terminal of the second resistor 711. The capacitor 709 has a first end coupled to the gate of the second PMOS 713 and a second end coupled to the drain of the first NMOS 705. The third PMOS 715 has a source coupled to one of the drains of the second PMOS 713 , a gate coupled to the second end of the capacitor 709 , and a drain coupled to the P-type pilot rectifier 203 . The second NMOS 717 has a drain coupled to one of the P-type step-controlled rectifier 203, a gate coupled to the second end of the capacitor 709, and a source coupled to the ground potential V _SS .

The operation of the ESD protection circuit 700 shown in FIG. 7 can be briefly described as follows: during normal operation, the second NMOS 717 is turned on and the voltage level of the B point is LOW, and by the feedback mechanism, the capacitor 709 is coupled. The voltage level connected to the second terminal of the drain of the first NMOS 705 is pulled high to HIGH, so that the voltage across the capacitor 709 is reduced, and the third PMOS 715 and the second PMOS 713 are effectively turned off. Therefore, the leakage path is cut off to reduce the leakage current.

According to the above embodiments, the ESD protection circuit according to the embodiment of the present invention can save the area of the flip-flop circuit, and can further provide a structure for reducing leakage current. Therefore, the problem of the electrostatic discharge protection circuit of the prior art can be improved.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

200, 300, 400, 402, 500, 502, 600, 700. . . Electrostatic discharge protection circuit

201. . . N-type voltage controlled rectifier

203. . . P type voltage controlled rectifier

205. . . Trigger circuit

207. . . Electrostatic discharge detection circuit

208. . . Input/output pad

301, 401. . . resistance

303, 403, 609, 709. . . capacitance

307. . . inverter

305, 605, 705. . . First NMOS

405, 603, 703. . . First PMOS

209, 501, 504. . . Composite circuit

503. . . Second NMOS

505, 613, 713. . . Second PMOS

601, 701. . . Composite circuit

607, 707. . . First resistance

611, 711. . . Second resistance

617,717. . . Third NMOS

FIG. 1 illustrates an electrostatic discharge protection circuit of the prior art.

FIG. 2 illustrates an ESD protection circuit that saves the area of the trigger circuit in accordance with an embodiment of the present invention.

Fig. 3 and Fig. 4 respectively show an example of the detailed structure of the electrostatic discharge protection circuit shown in Fig. 2.

5 to 7 illustrate the detailed structure of an electrostatic discharge protection circuit capable of preventing leakage current according to an embodiment of the present invention.

200. . . Electrostatic discharge protection circuit

201. . . N-type voltage controlled rectifier

203. . . P type voltage controlled rectifier

205. . . Trigger circuit

207. . . Electrostatic discharge detection circuit

208. . . Input/output pad

209. . . Composite circuit

Claims (15)

An ESD protection circuit having a combined triggering mechanism includes: an ESD detecting circuit for detecting an ESD voltage to generate a control signal, wherein the ESD detecting circuit is coupled to a first wire and a a second wire, the first wire receives a first voltage level and the second wire receives a second voltage level, the first voltage level is higher than the second voltage level; a first type of electrostatic discharge protection The component is configured to output a first trigger current; a second type of electrostatic discharge protection component is configured to receive a second trigger current; a trigger circuit coupled to the first voltage level and the second voltage level Forming a conduction path according to the control signal to receive the first trigger current from the first type electrostatic discharge protection component, and outputting the second trigger current to the second type electrostatic discharge protection component; and an input And an output pad; wherein the ESD detecting circuit is not directly connected to the input/output pad, the trigger circuit includes a first switch and a second switch, the first switch root The control signal determines whether to turn on the first type of electrostatic discharge protection component and the second type of electrostatic discharge protection component, and the second switch determines whether to make the first voltage level and the second voltage level according to the control signal And the ESD detecting circuit forms a conduction path. The electrostatic discharge protection circuit of claim 1, wherein the first type of electrostatic discharge protection component is an N-type 矽-controlled rectifier, and the second type of static electricity The discharge protection component is a P-type pilot rectifier. The electrostatic discharge protection circuit of claim 1, wherein the first trigger current and the second trigger current have the same value. The ESD protection circuit of claim 1, wherein the ESD detection circuit comprises: a resistor having a first end coupled to the first voltage level; and a capacitor coupled a first end of the second end of the resistor and a second end coupled to the second voltage level; the trigger circuit further includes: an inverter having a gate coupled to the first switch An output terminal having an input coupled to the second end of the resistor of the ESD detection circuit; wherein the first switch is a first NMOS having a first type of electrostatic discharge protection a drain of the component and a source coupled to the second type of electrostatic discharge protection component; and the first voltage level and the second voltage level are used as a supply voltage of the inverter. The electrostatic discharge protection circuit of claim 4, wherein the second switch is a second N-type MOS, having a drain coupled to the second end of the capacitor, coupled to the first a source of two voltage levels, and a gate coupled to the gate of the first N-type MOS and a gate of the output of the inverter. The ESD protection circuit of claim 1, wherein the ESD detection circuit comprises: a capacitor having a first end coupled to the first voltage level; and a resistor coupled a first end of the second end of the capacitor and a second end coupled to the second voltage level; the trigger circuit further includes: an inverter having a gate coupled to the first switch An input end of the pole, and having an input end coupled to the second end of the capacitor of the ESD detecting circuit; wherein the first switch is a first PMOS having a first type of electrostatic discharge coupled a source of the protection component and a drain coupled to the second type of electrostatic discharge protection component; and the first voltage level and the second voltage level are used as a supply voltage of the inverter. The electrostatic discharge protection circuit of claim 6, wherein the second switch is a second P-type MOS, and has a first end coupled to the first end of the capacitor, coupled to the first a source of one of the voltage levels, and a gate coupled to the first P-type MOS and a gate of the output of the inverter. An electrostatic discharge protection circuit having a combined triggering mechanism includes: an electrostatic discharge detecting circuit for detecting an electrostatic discharge voltage to generate a control signal; and a first type of electrostatic discharge protection component for outputting a first trigger a second type of electrostatic discharge protection element for receiving a second trigger current; and a trigger circuit for forming a conduction path according to the control signal, from the first type The ESD protection component receives the first trigger current and outputs the second trigger current to the second type ESD protection component; wherein the ESD detection circuit and the trigger circuit are both coupled to a first voltage level And a second voltage level, wherein the first voltage level is higher than the second voltage level; wherein the trigger circuit comprises a first switch and a second switch, the first switch is based on the control signal Determining whether to turn on the first type of electrostatic discharge protection component and the second type of electrostatic discharge protection component, the second switch determining whether to make the first voltage level, the second voltage level, and the electrostatic discharge according to the control signal The detection circuit forms a conduction path. The electrostatic discharge protection circuit of claim 8, wherein the first trigger current and the second trigger current have the same value. An electrostatic discharge protection circuit having a combined triggering mechanism includes: an electrostatic discharge detecting circuit for detecting an electrostatic discharge voltage to generate a control signal; and a first type of electrostatic discharge protection component for outputting a first trigger a second type of electrostatic discharge protection element for receiving a second trigger current; and a trigger circuit for forming a conduction path according to the control signal to receive the first type from the first type of electrostatic discharge protection element Triggering current, and outputting the second trigger current to the second type of electrostatic discharge protection component; wherein the electrostatic discharge detection circuit and the trigger circuit are coupled between a first voltage level and a second voltage level And the first voltage level is higher than the second voltage level; wherein the electrostatic discharge detecting circuit comprises: a resistor having a first end coupled to the first voltage level; and a capacitor having a first end coupled to a second end of the resistor and coupled to the second voltage level The trigger circuit includes: a first NMOS having a drain coupled to the first type of electrostatic discharge protection component and a source coupled to the second type of electrostatic discharge protection component; and an inverting An output terminal coupled to one of the gates of the first NMOS and having an input coupled to the second end of the resistor of the ESD detection circuit; and the first voltage level sum The second voltage level is used as the supply voltage of the inverter. The electrostatic discharge protection circuit of claim 10, further comprising a second N-type MOS having a drain coupled to the second end of the capacitor and coupled to the second voltage level And a source coupled to the gate of the first N-type MOS and a gate of the output of the inverter. An electrostatic discharge protection circuit having a combined triggering mechanism includes: an electrostatic discharge detecting circuit for detecting an electrostatic discharge voltage to generate a control signal; and a first type of electrostatic discharge protection component for outputting a first trigger a second type of electrostatic discharge protection element for receiving a second trigger current; and a trigger circuit for forming a conduction path according to the control signal, from the first type The ESD protection component receives the first trigger current and outputs the second trigger current to the second type ESD protection component; wherein the ESD detection circuit and the trigger circuit are both coupled to a first voltage level And a second voltage level, wherein the first voltage level is higher than the second voltage level; wherein the electrostatic discharge detecting circuit comprises: a capacitor having a first one coupled to the first voltage level a first end; and a resistor having a first end coupled to the second end of the capacitor and a second end coupled to the second voltage level; the trigger circuit comprising: a first PMOS having a source coupled to the first type of electrostatic discharge protection device and a drain coupled to the second type of electrostatic discharge protection device; and an inverter having a gate coupled to the first PMOS An output end having an input coupled to the second end of the capacitor of the ESD detecting circuit; and the first voltage level and the second voltage level are used as a supply voltage of the inverter . The electrostatic discharge protection circuit of claim 12, further comprising a second P-type MOS having a drain coupled to the first end of the capacitor and coupled to the first voltage level And a source coupled to the gate of the first P-type MOS and a gate of the output of the inverter. An electrostatic discharge protection circuit having a combined triggering mechanism includes: an electrostatic discharge detecting circuit for detecting an electrostatic discharge voltage to generate a control signal; and a first type of electrostatic discharge protection component for outputting a first trigger a second type of electrostatic discharge protection element for receiving a second trigger current; and a trigger circuit for forming a conduction path according to the control signal to receive the first type from the first type of electrostatic discharge protection element Triggering current, and outputting the second trigger current to the second type of electrostatic discharge protection component; wherein the trigger circuit is integrated into the electrostatic discharge detection circuit to form a composite circuit, the composite circuit comprising: a first PMOS having a source coupled to the first voltage level, and a gate coupled to the first type of electrostatic discharge protection element; a first NMOS having a first coupling to the first type of electrostatic discharge protection element a gate, and a drain connected to one of the drains of the first PMOS; a first resistor having a first end coupled to one of the sources of the first NMOS And a second PMOS coupled to the second voltage level; a second PMOS having a source coupled to the first voltage level and a gate coupled to one of the first PMOS gates a second NMOS having a drain coupled to the drain of the second PMOS and coupled to the first PMOS a gate of the drain; a capacitor having a first end coupled to the gate of the second NMOS; a third NMOS having a drain coupled to a source of the second NMOS, a gate coupled to the second end of the capacitor, and coupled to the second type a source of one of the ESD protection elements; and a second resistor having a first end coupled to the gate of the third NMOS and a second end coupled to the second voltage level. An electrostatic discharge protection circuit having a combined triggering mechanism includes: an electrostatic discharge detecting circuit for detecting an electrostatic discharge voltage to generate a control signal; and a first type of electrostatic discharge protection component for outputting a first trigger a second type of electrostatic discharge protection element for receiving a second trigger current; and a trigger circuit for forming a conduction path according to the control signal to receive the first type from the first type of electrostatic discharge protection element Triggering current, and outputting the second trigger current to the second type of electrostatic discharge protection component; wherein the trigger circuit is integrated into the electrostatic discharge detection circuit to form a composite circuit, the composite circuit comprising: a first PMOS having a gate coupled to the second type of electrostatic discharge protection device; a first NMOS having a gate coupled to the second type of electrostatic discharge protection component and coupled to one of the first PMOS drain electrodes a first resistor having a first end coupled to the first voltage level and a second end of one of the first PMOS sources; a second resistor having a first terminal coupled to the first voltage level; a second PMOS having a source coupled to the first type of electrostatic discharge protection component and coupled to the second resistor a gate of a second terminal; a capacitor having a first end coupled to the gate of the second PMOS, and And a third PMOS having a source coupled to one of the drains of the second PMOS and coupled to the second end of the capacitor a gate, and a drain coupled to the second type of electrostatic discharge protection component; a second NMOS having a drain coupled to the second type of electrostatic discharge protection component and coupled to the capacitor One of the two terminals is coupled to the source of the second voltage level.