JP2001308200A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a decline of the surge absorption ability caused by the pinch-off phenomenon and an enhancement of a leak current caused by a trap of hot electrons, in a protective circuit using a MOS transistor which is normally in an off-state in the protective circuit of a semiconductor device. SOLUTION: An enhancement of a leak current of a MOS transistor, and the internal circuit is protected by connecting a drain terminal and a source terminal of the MOS transistor to a power source line through a resistance and supplying the power source of the internal circuit from the drain terminal and the source terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electrostatic discharge ("ESD") for a semiconductor integrated circuit.
Discharge)).

[0002]

2. Description of the Related Art MOS devices and CMOS devices having a thin gate oxide film are affected by ESD, such as destruction of the gate oxide film or the PN junction and changes in element characteristics. ESD occurs when the accumulated charge is discharged to a terminal of the semiconductor device as a high voltage pulse in a short period. M
OS semiconductor integrated circuits are conventionally provided with a protection circuit in order to avoid the influence of the ESD. However, since the transistor area is reduced year by year, the energy concentration per unit transistor tends to increase. In many cases, a sufficient effect cannot be obtained with the conventional protection circuit. Hereinafter, the operation principle of the conventional protection circuit will be described with reference to the drawings.

FIG. 3 is a circuit diagram showing a first example of a conventional protection circuit. In FIG. 3, a protection circuit 10 provided at an input terminal 105 includes a diode 115 connected in the opposite direction between a power supply line 109 connected to a power supply terminal 107 (VDD) and an input signal path, and a power supply terminal 106. A diode 116 and a resistor 11 are connected in a reverse direction between a power supply line 110 connected to (VSS) and the input signal path, and the resistor is connected to a gate of a transistor in the internal circuit 124. The internal circuit 125 connected to the output terminal 108
Protection circuit 20 includes a diode 118 connected in the reverse direction between the power supply line 109 and the output signal path, and a diode 119 connected in the reverse direction between the output signal path and the power supply line 110. Is done. However, the diode 118
And the diode 119 are often replaced by a PN junction parasitic to the drain of the transistor constituting the output circuit, and may not be provided as an independent protection circuit.

In addition to a protection circuit, in a normal CMOS integrated circuit, a diode 117 formed by a junction between an N-type substrate and a P-type substrate, a P-channel MOS and an N-channel MOS
There is a diode 30 due to the respective drain-substrate junctions.

For the sake of simplicity, the operation of the protection circuit will be described only when a positive high voltage pulse is applied to the input terminal 105 with the power supply terminal 106 (VSS) as a reference when the power supply terminal 107 (VDD) is open.

[0006] The positive high voltage pulse applied to the input terminal 105 is connected to VSS through the reverse junction of the diode 116.
Discharged toward the terminal, the potential of the input terminal 105 drops rapidly and is clamped to the reverse voltage of the diode 116. However, the potential of the input terminal 105 is within a dangerously high potential range for a very short time until the discharge by the diode 116 proceeds sufficiently.

The dangerous high potential is supplied to the gate of the transistor in the internal circuit 124 via the resistor 11, but the gate has a gate capacitance (not shown). Due to the time constant of the resistor 11 and the gate capacitance, the gate cannot be rapidly increased, and the gate is protected from destruction until the potential of the input terminal 105 reaches a safe level.

The above is the operation of the protection circuit 10.
Actually, the electric charge flowing into the input terminal 105 is transferred to the power supply line 109 through the forward junction of the diode 115.
And the potential of the power supply line 109 rises. This rise in potential is suppressed by discharging current through the reverse junction of the diode 117, the protection circuit 20, and the diode 30. However, the current distribution was not performed properly,
When the electric charge is concentrated on some of the junctions, the junction of the drain and the source is destroyed.

Therefore, as shown in FIG. 4, it has been proposed to add a new protection circuit 40 between the power supply line 109 and the power supply line 110 for further protecting the internal circuit in order to solve the above problem. ing. FIG. 5 shows a conventional example of the new protection circuit 40.

FIG. 5A shows a protection circuit shown as a conventional example in FIGS. 8 and 9 of Japanese Patent Application Laid-Open No. 10-229132 (hereinafter referred to as Reference 1), wherein the drain of an N-channel MOS transistor 41 is shown. Are connected to the power supply line 109, and the source and the gate are connected to the power supply line 110. This protection circuit is described in paragraph [000] of Document 1.
As described in detail from “4” to “0010”, the present invention utilizes the punch-through voltage Vp of the MOS transistor 41 in the off state. Since the punch-through voltage Vp can be made lower than the reverse breakdown voltage of the diode 117, the protection function of the internal circuit can be improved.

FIG. 5B shows the circuit of FIG. 5A in which the gate of the N-channel MOS transistor 41 is connected to a resistor 4.
2 to the power supply line 110. This resistor 42 has the same effect as the resistor 11 in FIG. That is, the N-channel MOS transistor 4
In conjunction with a gate capacitance of 1 (not shown), the instantaneous application of a high voltage to the gate is suppressed, and the gate is prevented from being broken.

The drawback of the circuit shown in FIG. 5A (or FIG. 5B) is described in the paragraph "0010" of Document 1, "However, punch-through is a phenomenon that occurs after the potential difference Vg becomes large. In addition to the timing at which the surge starts to be released, the punch-through voltage Vp1 or Vp2
Since the absolute value of itself is large, it may put a burden on other internal circuits in the semiconductor integrated circuit, promote the deterioration of the element, and eventually cause a destruction failure. "

FIG. 5C shows FIGS. 11 and 12 of Document 1.
FIG. 5 shows another protection circuit shown as a conventional example.
(A) An improvement of the protection circuit shown in (b), wherein the gate of the N-channel MOS transistor 41 is connected to the power supply line 110 via a resistor 42, and the power supply line is connected via a capacitor 43. 109 is connected.

In FIG. 5 (c), in a steady state, the gate potential of the N-channel MOS transistor 41 is maintained at the source potential by the resistor 42, so that the N-channel MOS transistor 41 is off. When the potential of the power supply line 109 rises sharply, the capacitance 43 and N
The voltage divided by the gate capacitance of the channel MOS transistor 41 is applied to the gate, and the N-channel MOS transistor 41 is turned on to rapidly discharge the electric charge from the power supply line 109.

Reference 1 discloses the protection circuit of FIG.
In the paragraphs “0017” to “0018”, “This protection circuit uses a rising component of a surge voltage, that is, a differential component, so that the operation timing is early,
In this respect, the disadvantage of the punch-through type is solved. However, since the applied surge voltage generally has a large potential difference, the potential difference between the gate and the drain becomes small in the vicinity of the drain, the induced charge decreases, and the channel disappears, which causes a pinch-off phenomenon. For this reason, the surge absorbing ability is lost, and a load is imposed on other internal circuits, and the deterioration of the element is accelerated, which eventually leads to a destruction failure. Further, the large current flowing at the time of pinch-off generates hot electrons, some electrons are captured in the gate oxide film below the gate 84, and a variation in the threshold voltage Vt causes a malfunction of the protection circuit itself. The effect is described.

Reference 1 proposes a circuit shown in FIG. 5D as a new protection circuit for solving these disadvantages. Since this circuit uses a parasitic bipolar transistor, it is considered that the capability of discharging a surge current is extremely high and the capability as a protection circuit is excellent. However, due to the structure in which the substrate of the N-channel MOS transistor 41 is connected to the source and the power supply 110 via a relatively high resistance, the protection circuit shown in FIGS. It is considered that the well-known latch-up phenomenon easily occurs.

[0017]

Accordingly, the present invention provides a safe use of the protection circuit shown in FIGS. 5A, 5B or 5C, which has the above-mentioned drawbacks but has a high latch-up withstand voltage. The task was to do it.

[0018]

In order to achieve the above-mentioned object, a first means used in the present invention is a CMOS semiconductor integrated circuit using a MOS transistor which is normally turned off when energized as a part of a protection circuit. In the MOS
A source end of the transistor is connected to a power supply line connected to one power supply terminal via a resistor, and a drain end is connected to a power supply line connected to the other power supply terminal via a resistor. The power supply for the circuit portion of the MOS transistor is supplied from the drain terminal and the source terminal of the MOS transistor.

A second means used in the present invention is the first means, wherein power is supplied to at least a part of the circuit portion from the drain terminal and the source terminal of the MOS transistor via respective resistors. It is to do.

The third means used in the present invention is the above-mentioned first or second means, wherein the gate of the MOS transistor is connected to the source of the MOS transistor via a resistor and the drain is connected via a capacitor. The end is to be connected to a power supply line connected via a resistor.

The fourth means used in the present invention is that the MOS
At least a part of the resistance connected to the drain or the source of the transistor is constituted by a substrate resistance.

A fifth means used in the present invention is that, in the third means, the capacitance uses an insulating film having a thickness different from a gate oxide film as a dielectric material.

A sixth means used in the present invention is that, in the third means, one electrode of the capacitor is a metal wiring member and the other electrode is a polysilicon wiring member.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. The parameters of the integrated circuit used for testing the effectiveness of the present invention are as follows. Breakdown voltage of diode 217
13.0 V Off-state breakdown voltage of N-channel MOS transistor 11.0 VP-state off-state voltage of MOS transistor 9.5 V

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, the new protection circuit 40 has a configuration similar to the configuration shown in FIG. 5B. That is, the drain of the N-channel MOS transistor 41 is connected to the power supply line 109 connected to one power supply terminal 107 (VDD) via the resistor 101, and the source is connected to the resistor 10
2 is connected to the power supply line 110 connected to the other power supply terminal 106 (VSS), and the gate is connected to the source via the resistor 42.

The power of the internal circuit 125 connected to a part of the circuit, for example, the output terminal 108, is supplied from the drain terminal 111 and the source terminal 112 of the MOS transistor 41, and the other at least part of the circuit, for example, the internal The power of the circuit 124 is supplied from the drain terminal 111 and the source terminal 112 via the resistors 103 and 104, respectively. In this case, the first means and the second means are used in combination.

In this embodiment, the resistance 4
The value of 2 may be 0. The diode 217 is particularly provided, and the way of wiring, the way of contacting, and the like are devised so that high voltage can be effectively clamped.

In the circuit shown in FIG.
When a positive charge is injected into the input terminal 105 based on (VSS), the potential of the power supply line 109 increases due to the forward characteristics of the diode 115.

This potential rise is clamped to 13 V as a result of the discharge by the diode 217, but there is a period in which the potential of the power supply line 109 is extremely high until the discharge sufficiently proceeds. However, this period is extremely short, and a large parasitic capacitance (not shown) exists at the drain end 111 of the MOS transistor 41. Therefore, a sharp increase in the potential of the drain end 111 during this period is suppressed. . Even if the drain-source voltage of the MOS transistor 41 rises to the punch-through voltage, the discharge current is limited by the resistors 101 and 102, so that the MOS transistor 41 and the large output transistor in the internal circuit 125 may be damaged. I will not receive it. The voltage between the drain terminal 111 and the source terminal 112 is 11 V
Is clamped to.

The same description as above can be applied to the relationship between the power supply of the internal circuit 124 and the potential of the drain terminal 111. In this way, the protection circuit 40 can operate the internal circuit 12 without damaging the MOS transistor 41.
4, 125 can be protected. There is no inconvenience that the carrier generated in the discharging process is trapped under the gate of the transistor and the leak current increases.

In the embodiment of FIG. 1, when the transistors constituting the internal circuit 125 are sufficiently large and it is necessary to reduce the output resistance, as shown by the thick dotted line in FIG. One or both of the power supplies of the internal circuit 125 may be directly supplied from the power supply lines 109 and 110.
Conversely, when the transistors that make up the internal circuit 125 are small or when it is not necessary to reduce the output resistance, the power supply of the internal circuit 125 may be shared with the power supply of the internal circuit 124. In these cases, only the second means is performed.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In FIG. 2, the new protection circuit 40 has a configuration similar to the configuration shown in FIG. 5C. That is, the drain of the N-channel MOS transistor 41 is connected to the power supply line 109 connected to the power supply terminal 107 (VDD) via the resistor 101, and the source is connected to the power supply terminal 106 (VSS) via the resistor 102. Power line 1
10, the gate is connected to the source via a resistor 42, and the power supply line 10 is connected via a capacitor 44.
9 is connected.

The power of at least a part of the circuit, for example, the internal circuit 124 is supplied from the drain terminal 111 and the source terminal 112 of the MOS transistor 41. The power supply of another part of the circuit, for example, the internal circuit 125 connected to the output terminal 108 may be shared with the power supply of the internal circuit 124 as described in the first embodiment, It may be connected directly to the lines 109 and 110. In any case, the second means is not used in the second embodiment.

In the circuit shown in FIG.
When a positive charge is injected into the input terminal 105 with reference to (VSS), the potential is maintained until the potential of the power supply line 109 is clamped by the diode 217 as described in the first embodiment. High potential instantaneously. This rise in potential is applied to the N-channel MOS via the capacitor 44.
The gate potential of the transistor 41 is transmitted to the capacitor 44 and the N-channel MOS transistor 41.
To the potential divided by the gate capacitance of the gate electrode. The rise of the gate potential causes the N-channel MOS transistor 4
Since 1 is turned on and a short circuit occurs between the drain and the source, a dangerous high voltage is not applied to a circuit portion connected between the drain and the source.

When the potential of the power supply line 109 is clamped, the gate potential of the N-channel MOS transistor 41 decreases, and the N-channel MOS transistor 41 shifts to the off state. Although the voltage between the drain and the source of the N-channel MOS transistor 41 increases, a large parasitic capacitance (not shown) exists between the drain and the source as described above.
Due to the effects of 1 and 102, the rise in the drain-source voltage becomes gentle.

Therefore, N-channel MOS transistor 41
Discharge due to punch-through is also performed gradually.
The channel MOS transistor 41 and the circuit connected between the drain and the source are not damaged.

In the description of the first and second embodiments, the case where a positive charge is injected into the input terminal 105 based on the power supply terminal 106 (VSS) is considered. The present invention is effective in other cases irrespective of the terminal to which is applied and whether the injected charge is positive or negative.

In the above embodiment, the N-channel MOS transistor 41 is used for the protection circuit 40, but it is easy to change this to a P-channel MOS transistor.
In this case, it is natural that the connection points of the drain, source, substrate, resistor 42, capacitor 44, and the like of the P-channel MOS transistor are changed.

Further, a protection circuit using a P-channel MOS transistor may be provided in parallel with a protection circuit using an N-channel MOS transistor. By doing so, it is possible to disperse the discharge paths, and the effect of protection is further increased.

In the capacitor 44 in the second embodiment shown in FIG. 2, it is desirable to use an insulating film having a thickness different from that of the gate oxide film as a dielectric material in consideration of withstand voltage. In this case, it is preferable that one electrode of the capacitor is a metal wiring member and the other electrode is a polysilicon wiring member.

In FIGS. 1 and 2, the substrate of each MOS transistor is shown as being connected to the source. For example, in the integrated circuit having the SOI structure, the substrate of all or a part of the MOS transistor is connected. Can be in a floating state.

In an integrated circuit having a normal structure using a diffusion wafer, a substrate of a P-channel MOS transistor is used when the wafer is an N-type wafer, and a substrate of an N-channel MOS transistor is used when the wafer is a P-type wafer. Are connected to the power supply lines 109 or 110 via resistors, respectively, but these resistors are not shown in order to avoid complication. Since these resistors are diffusion resistors having a low concentration and have relatively high sheet resistance, the resistors 101, 102, and 102 shown in FIG. 1 or FIG.
103 and 104 can be designed to work effectively.

The resistors 101, 102, 103 and 1
04 can use a polysilicon resistance or a diffusion resistance provided in a substrate, but can also use a substrate resistance.
FIG. 6 is a schematic sectional view of an integrated circuit in which the resistors 101 and 103 are formed using a substrate resistor, and the resistors 102 and 104 are formed using a diffusion resistor. In this example, P
In the case where a mold wafer is used, the resistance 10 shown in FIG.
1, 102, 103 and 104 and the internal circuit 124
1 shows the structural relationship of one inverter.

In FIG. 6, P-type diffusion layers 60 and 62, N-type diffusion layers 61, 63, 64 and N
A mold diffusion well 51 is provided. In the N-type diffusion well 51, P-type diffusion layers 65 and 66, N-type diffusion layers 67 and 6 are provided.
8, 69 are provided.

The N-type diffusion layer 64 and the P-type diffusion layer 65 are commonly connected to form an output terminal of the inverter. The N-type diffusion layer 63 serving as the source of the N-channel MOS transistor is connected to the P-type substrate 50 via the P-type diffusion layer 62 in the vicinity thereof and is connected to one end of the N-type diffusion layer 61 which is a diffusion resistor. Connected.

The other end of the N-type diffusion layer 61, which is a diffusion resistor, is connected to the power supply line 1 connected to the power supply terminal (VSS).
The power line 110 is connected to the P-type substrate 50 via the P-type diffusion layer 60. A line connected to a point in the middle of the N-type diffusion layer 61 is connected to the source end 112 of the N-channel MOS transistor 41 (not shown in FIG. 6).
Connected to. Thus, the resistors 102 and 10 in FIG.
4 is formed by the N-type diffusion layer 61.

Although there is a parasitic resistance 202 due to a P-type substrate between the P-type diffusion layers 60 and 62, the sheet resistance of this resistance is considerably large, and the distance between the P-type diffusion layers 60 and 62 must be appropriately set apart. Thus, the effect of the parasitic resistance 202 can be reduced.

On the other hand, the P-type diffusion layer 66 serving as the source of the P-channel MOS transistor is connected to the N-type substrate 51 via the N-type diffusion layer 67 in the vicinity thereof. The N-type diffusion layer 68 is connected to the N-channel MOS transistor 41 (FIG. 6).
The N-type diffusion layer 69 is connected to the power supply line 109.

The N-type diffusion layer 68 and the N-type diffusion layer 6
7 and the N-type diffusion layer 69, resistors 103 and 101 are formed by an N-type substrate, respectively. Although the parasitic resistance 201 exists between the N-type diffusion layer 69 and the N-type diffusion layer 67, the influence can be reduced by measures such as increasing the width of the N-type diffusion layer 68.

[0050]

As is clear from the above description, the ESD
Therefore, it is possible to provide a protection circuit for a semiconductor integrated circuit that does not cause destruction of an internal circuit or increase in leakage current and has a high latch-up withstand voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram of one embodiment of the present invention.

FIG. 3 is a circuit diagram for explaining a protection circuit.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a structural diagram of one embodiment of the present invention.

[Explanation of symbols]

 41 N-channel MOS transistor 105 Input terminal 106 Power supply terminal (VSS) 107 Power supply terminal (VDD) 108 Output terminal 111 Drain terminal 112 Source terminal 124 Internal circuit 125 Internal circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/003 F-term (Reference) 5F038 AC05 AC17 AR01 AR09 AR30 BH07 BH13 EZ20 5F048 AA02 AA03 AB04 AC03 AC04 AC10 BA01 BA16 BE04 CC01 CC04 CC05 CC06 CC09 CC15 CC16 5J032 AA02 AC18 5J056 AA01 BB47 BB48 BB49 DD13 DD29 DD55 EE11 FF08 JJ05 KK02

Claims (6)

[Claims] In a CMOS semiconductor integrated circuit using a MOS transistor which is normally turned off when energized as a part of a protection circuit, a source terminal of the MOS transistor is connected to a power supply line connected to one power supply terminal. Connected via a resistor, the drain end is connected via a resistor to a power supply line connected to the other one of the power supply terminals, and the power supply of at least a portion of the circuit is connected to the drain end of the MOS transistor and the drain end of the MOS transistor. A semiconductor integrated circuit supplied from a source end. 2. The semiconductor integrated circuit according to claim 1, wherein power of at least a part of the circuit is supplied from the drain terminal and the source terminal of the MOS transistor via respective resistors. circuit. 3. The MOS transistor according to claim 1, wherein a gate of the MOS transistor is connected to a source of the MOS transistor via a resistor, and the drain terminal is connected to a power supply line connected via a resistor via a capacitor. The semiconductor integrated circuit according to claim 1. 4. The semiconductor integrated circuit according to claim 1, wherein at least a part of the resistance connected to the drain or the source of the MOS transistor is constituted by a substrate resistance. 5. The capacitor according to claim 3, wherein an insulating film having a thickness different from a gate oxide film is used as a dielectric material.
3. The semiconductor integrated circuit according to claim 1. 6. The semiconductor integrated circuit according to claim 3, wherein one electrode of the capacitor is a metal wiring member, and the other electrode is a polysilicon wiring member.