JPH0553074B2 - - Google Patents
Info
- Publication number
- JPH0553074B2 JPH0553074B2 JP61059278A JP5927886A JPH0553074B2 JP H0553074 B2 JPH0553074 B2 JP H0553074B2 JP 61059278 A JP61059278 A JP 61059278A JP 5927886 A JP5927886 A JP 5927886A JP H0553074 B2 JPH0553074 B2 JP H0553074B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- epitaxial layer
- conductivity type
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 2
- 108091006146 Channels Proteins 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 6
- 230000001965 increasing effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は、電力用の横形のDMOSトランジ
スタ（以下LDMOSという）と、その周辺回路等
を構成する他の半導体素子とを１チツプ上に構成
した半導体装置に関し、特にLDMOSの耐圧特性
を向上させたものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is a method of configuring a power lateral DMOS transistor (hereinafter referred to as LDMOS) and other semiconductor elements constituting its peripheral circuitry on a single chip. Regarding semiconductor devices, this is a device that particularly improves the breakdown voltage characteristics of LDMOS.
［発明の技術的背景とその問題点］
近年、各種車載電力負荷等のスイツチング素子
として用いられる電力用のMOSトランジスタと、
その駆動回路等の周辺回路を構成する半導体素子
とを１チツプ上に構成した半導体装置が提案され
ている。[Technical background of the invention and its problems] In recent years, power MOS transistors used as switching elements for various on-vehicle power loads, etc.
A semiconductor device has been proposed in which semiconductor elements constituting peripheral circuits such as a drive circuit are formed on one chip.
第３図は、このような半導体装置の従来例を示
すものである（R.A.Blanchard，1982 SID
INTERNATIONAL SYMPOSIUM DIGEST
of TECHNICAL PAPERS，1982，P258〜）。 Figure 3 shows a conventional example of such a semiconductor device (RABlanchard, 1982 SID
INTERNATIONAL SYMPOSIUM DIGEST
of TECHNICAL PAPERS, 1982, P258~).
半導体基板は、ｐ形（ｐ形を第１導電形とすれ
ば、ｎ形が第２導電形となる）の基板１上に、
n-エピタキシヤル層２を形成したものが用いら
れている。n-エピタキシヤル層２の所要部には、
ｐ基板１に達するｐ分離領域３が拡散形成され
て、LDMOS４が形成されるMOSトランジスタ
領域と、nMOS５およびpMOS６等の他の半導体
素子が形成される素子領域とに分離されている。 The semiconductor substrate has a substrate 1 of p type (if p type is the first conductivity type, n type is the second conductivity type),
The one in which an n -epitaxial layer 2 is formed is used. In the necessary parts of the n -epitaxial layer 2,
A p isolation region 3 reaching the p substrate 1 is formed by diffusion and is separated into a MOS transistor region where an LDMOS 4 is formed and an element region where other semiconductor elements such as an nMOS 5 and a pMOS 6 are formed.
LDMOS４は、高比抵抗のn-エピタキシヤル層
２をドレイン領域として、p+高不純物濃度領域
を含むｐ形のチヤンネル領域７、チヤンネル領域
７内に形成されたn+ソース領域８、n+ソース領
域８およびドレイン領域２間におけるチヤンネル
領域７上にゲート酸化膜９を介して配設されたポ
リシリコンからなるゲート電極１１、n+ソース
領域８およびチヤンネル領域７に接続されたソー
ス電極１２、n+のドレインコンタクト領域１３
に接続されたドレイン電極１４等で構成されてい
る。 The LDMOS 4 has a high resistivity n - epitaxial layer 2 as a drain region, a p-type channel region 7 including a p + high impurity concentration region, an n + source region 8 formed within the channel region 7, and an n + source. A gate electrode 11, n made of polysilicon is disposed on the channel region 7 between the region 8 and the drain region 2 via the gate oxide film 9, and a source electrode 12, n connected to the + source region 8 and the channel region 7. + drain contact region 13
The drain electrode 14 is connected to the drain electrode 14 and the like.
LDMOS４は、チヤンネル領域７がｐ形なので
ｎチヤンネルとして構成され、また高比抵抗の
n-エピタキシヤル層２がドレイン領域とされて
高耐圧化が図られ、電力用のMOSトランジスタ
として動作する。 Since the channel region 7 is p-type, the LDMOS 4 is configured as an n-channel, and has a high specific resistance.
The n - epitaxial layer 2 is used as a drain region to achieve high breakdown voltage, and operates as a power MOS transistor.
一方、素子領域には、さらにｐウエル領域１５
が形成され、このｐウエル領域１５内に形成され
たnMOS５と、n-エピタキシヤル層２中に直接形
成されたpMOS６とでCMOSが構成されている。 On the other hand, the element region further includes a p-well region 15.
An nMOS 5 formed in this p well region 15 and a pMOS 6 formed directly in the n - epitaxial layer 2 constitute a CMOS.
nMOS５は、ｐウエル領域１５を基板領域とし
て、n+ソース領域１６、n+ドレイン領域１７、
ゲート酸化膜１８上に形成されたゲート電極１９
等で構成されている。 The nMOS 5 has a p-well region 15 as a substrate region, an n + source region 16, an n + drain region 17,
Gate electrode 19 formed on gate oxide film 18
It is composed of etc.
またpMOS６は、n-エピタキシヤル層２を基板
領域として、p+ソース領域２１、p+ドレイン領
域２２、ゲート酸化膜２３上に形成されたゲート
電極２４等で構成されている。 The pMOS 6 also includes a p + source region 21, a p + drain region 22, a gate electrode 24 formed on a gate oxide film 23, and the like, using the n - epitaxial layer 2 as a substrate region.
このように電力用のLDMOS４と、その駆動回
路等を構成する周辺回路を１チツプ上に集積する
ことは、特性、チツプコスト、および実装コスト
等で有利となる。 In this way, integrating the power LDMOS 4 and the peripheral circuits constituting its drive circuit and the like on one chip is advantageous in terms of characteristics, chip cost, and mounting cost.
第４図は、他の従来例を示すもので上記第３図
の従来例におけるLDMOS４と類似のLDMOS部
分のみが開示されたものである（A.Blicher著
“Field Effect and Bipolar Power Transister
Physics”，ACADEMIC PRESS，p277）。 Fig. 4 shows another conventional example, in which only the LDMOS portion similar to the LDMOS4 in the conventional example shown in Fig. 3 is disclosed (A. Blicher, “Field Effect and Bipolar Power Transistor
Physics”, ACADEMIC PRESS, p277).
第４図中、２５は中間絶縁膜、２６は最終保護
膜、２７はp+チヤンネルコンタクト領域で、チ
ヤンネル領域７はp+チヤンネルコンタクト領域
２７を介してソース電極１２に接続されている。 In FIG. 4, 25 is an intermediate insulating film, 26 is a final protective film, 27 is a p + channel contact region, and the channel region 7 is connected to the source electrode 12 via the p + channel contact region 27.
ところで電力負荷がモータやソレノイド等の誘
導性の負荷である場合は、負荷電流を遮断した際
に高電圧のサージが発生し、この高電圧のサージ
は、LDMOSのドレイン・ソース間に加わる。即
ち第４図のLDMOSで云えば、この高電圧のサー
ジは、ドレイン２とチヤンネル領域７間のpn接
合部に逆電圧として加わり、特にそのコーナーａ
の部分に集中して加わり易い。 By the way, when the power load is an inductive load such as a motor or a solenoid, a high voltage surge occurs when the load current is cut off, and this high voltage surge is applied between the drain and source of the LDMOS. In other words, in the LDMOS shown in FIG. 4, this high voltage surge is applied as a reverse voltage to the pn junction between the drain 2 and the channel region 7, especially at the corner a.
It is easy to concentrate and participate in the part.
そしてドレイン耐圧を越えた高電圧のサージが
加わるとアバランシエ降伏を起し、コーナー部ａ
への電流集中による発熱でLDMOSは破壊され
る。 When a high voltage surge exceeding the drain breakdown voltage is applied, avalanche breakdown occurs and the corner a
The LDMOS is destroyed due to heat generated by current concentration in the LDMOS.
このためLDMOSは、予想されるサージ電圧よ
りも十分高い耐圧特性を有するように設計してお
く必要があり、従来のLDMOSは、この耐圧特性
の向上をn-エピタキシヤル層２の比抵抗、云い
換えればドレイン領域の比抵抗を大にすることに
より行なつていた。 For this reason, LDMOS must be designed to have voltage resistance characteristics that are sufficiently higher than the expected surge voltage, and in conventional LDMOS, this improvement in voltage resistance characteristics is achieved by increasing the resistivity of the n -epitaxial layer 2. In other words, this was done by increasing the specific resistance of the drain region.
しかしながらn-エピタキシヤル層２の比抵抗
を大にすると、LDMOSの動作時のオン抵抗が高
くなり過ぎ、これを解決するためには素子面積を
大にせざるを得ないという問題点があつた。また
n-エピタキシヤル層２には、nMOS５および
pMOS６等の他の半導体素子も形成されているの
で、n-エピタキシヤル層２の比抵抗を大にする
と、これらの他の半導体素子の設計にも影響が及
び、同一特性の素子とするためには、素子面積が
大になつてチツプ面積が増大し、コスト的に不利
を招くという問題点があつた。 However, when the resistivity of the n - epitaxial layer 2 is increased, the on-resistance during LDMOS operation becomes too high, and in order to solve this problem, the device area must be increased. Also
The n - epitaxial layer 2 includes nMOS5 and
Since other semiconductor elements such as pMOS6 are also formed, increasing the resistivity of the n - epitaxial layer 2 will affect the design of these other semiconductor elements, and in order to make elements with the same characteristics. However, there was a problem in that the element area became large and the chip area increased, resulting in a cost disadvantage.
［発明の目的］
この発明は、上記事情に基づいてなされたもの
で、LDMOSのオン抵抗が低く動作特性が優れ、
且つチツプ面積を小さくすることができてコスト
低減を図ることのできる半導体装置を提供するこ
とを目的とする。[Object of the Invention] This invention was made based on the above circumstances, and provides an LDMOS with low on-resistance and excellent operating characteristics.
Another object of the present invention is to provide a semiconductor device that can reduce the chip area and reduce costs.
［発明の概要］
この発明は、上記目的を達成するために、第１
導電形の基板およびドレイン領域となる第２導電
形のエピタキシヤル層の間に第２導電形で且つ高
不純物濃度の埋込層を設け、第１導電形のチヤン
ネル領域は当該埋込層に達するように形成すると
ともに、チヤンネル領域内にはソース電極および
前記埋込層に接続されるように第１導電形で且つ
高不純物濃度のツエナ電圧制御領域を形成し、こ
のツエナ電圧制御領域および前記の埋込層により
ドレイン・ソース間に所要のツエナ電圧特性を有
するツエナダイオードを形成して、高電圧のサー
ジはこのツエナダイオードを介してソースにバイ
パスされるようにしたものである。[Summary of the invention] In order to achieve the above object, the present invention
A buried layer of a second conductivity type and having a high impurity concentration is provided between the substrate of the conductivity type and the epitaxial layer of the second conductivity type serving as a drain region, and the channel region of the first conductivity type reaches the buried layer. A Zener voltage control region of a first conductivity type and a high impurity concentration is formed in the channel region so as to be connected to the source electrode and the buried layer, and this Zener voltage control region and the A Zener diode having the required Zener voltage characteristics is formed between the drain and the source using the buried layer, and a high voltage surge is bypassed to the source via this Zener diode.
［発明の実施例］
以下この発明の実施例を図面に基づいて説明す
る。[Embodiments of the Invention] Examples of the present invention will be described below based on the drawings.
第１図はこの発明の一実施例を示す図である。
なお第１図において前記第３図および第４図にお
ける部材または部位と同一ないし均等のものは、
前記と同一符号を以つて示し重複した説明を省略
する。 FIG. 1 is a diagram showing an embodiment of the present invention.
In addition, parts or parts in FIG. 1 that are the same as or equivalent to those in FIGS. 3 and 4 are as follows:
The same reference numerals as above are used to omit redundant explanation.
まず構成を説明すると、ｎエピタキシヤル層２
の比抵抗は、電源電圧に対して十分なドレイン耐
圧特性が得られるような値に選ばれている。 First, to explain the structure, the n epitaxial layer 2
The specific resistance of is selected to a value that provides sufficient drain breakdown voltage characteristics with respect to the power supply voltage.
そしてMOSトランジスタ領域におけるｎエピ
タキシヤル層２とｐ基板１との間に、高不純物濃
度のn+埋込層（埋込ドレイン領域）２９が埋設
されている。チヤンネル領域７の下部は、この
n+埋込層２９に広い面積に亘つて接している。
チヤンネル領域７のほぼ中央部位には、高不純物
濃度のp+ツエナ電圧制御領域２８が形成されて
いる。 An n + buried layer (buried drain region) 29 with a high impurity concentration is buried between the n epitaxial layer 2 and the p substrate 1 in the MOS transistor region. The lower part of channel area 7 is
It is in contact with the n + buried layer 29 over a wide area.
A p + Zener voltage control region 28 with a high impurity concentration is formed approximately at the center of the channel region 7 .
p+ツエナ電圧制御領域２８の上部は、チヤン
ネルコンタクト領域２７を介してソース電極１２
に接続され、下部は広い面積でn+埋込層２９に
接している。p+ツエナ電圧制御領域２８とn+埋
込層２９との間のp+・n+接合により、LDMOS内
のドレイン・ソース間に所要のツエナ電圧と電流
容量特性を有するツエナダイオードが形成され
る。 The upper part of the p + Zener voltage control region 28 is connected to the source electrode 12 via the channel contact region 27.
The lower part is in contact with the n + buried layer 29 over a wide area. The p + /n + junction between the p + zener voltage control region 28 and the n + buried layer 29 forms a Zener diode having the required Zener voltage and current capacity characteristics between the drain and source in the LDMOS. .
ツエナダイオードのツエナ電圧は、p+制御領
域２８の不純物濃度を制御することにより、
LDMOSのドレイン・ソース間耐圧より所要値だ
け低い値に規定されている。 The Zener voltage of the Zener diode can be determined by controlling the impurity concentration of the p + control region 28.
It is specified to be a value lower than the drain-source breakdown voltage of LDMOS by the required value.
なお第１図には、素子領域が図示省略されてい
るが、素子領域におけるｎエピタキシヤル層２内
には、前記第３図におけるものとはほぼ同様の
nMOS５、およびpMS６等の他の半導体素子が
形成されている。 Although the element region is not shown in FIG. 1, there is a layer in the n epitaxial layer 2 in the element region that is almost the same as that in FIG. 3.
Other semiconductor elements such as nMOS5 and pMS6 are formed.
次に作用を説明する。 Next, the effect will be explained.
電力負荷のスイツチング素子等として用いられ
ているLDMOSは、ドレイン領域として用いられ
ているｎエピタキシヤル層２の比抵抗が、電源電
圧に対して十分なドレイン耐圧が得られるような
通常の値を有するものが用いられているので、そ
の動作時のオン抵抗は低く抑えられ、良好な動作
特性が得られる。 In LDMOS, which is used as a power load switching element, etc., the specific resistance of the n-epitaxial layer 2 used as the drain region has a normal value such that sufficient drain withstand voltage can be obtained with respect to the power supply voltage. Since a metal is used, the on-resistance during operation can be kept low, and good operating characteristics can be obtained.
負荷電流を遮断したとき発生する高電圧のサー
ジがドレイン電極１４に加わるが、そのサージ電
圧値がドレイン耐圧を越えても、高電圧のサージ
は所要の電流容量を有するツエナダイオードを介
してソースにバイパスされ、LDMOSの破壊が防
止される。 A high voltage surge that occurs when the load current is cut off is applied to the drain electrode 14, but even if the surge voltage value exceeds the drain withstand voltage, the high voltage surge is transferred to the source through a Zener diode with the required current capacity. Bypassed to prevent LDMOS destruction.
次いで第２図にはこの発明の他の実施例を示
す。 Next, FIG. 2 shows another embodiment of the present invention.
この実施例は、ｐ基板１上にｐ形のエピタキシ
ヤル層３２が形成されている。ｐエピタキシヤル
層３２におけるMOSトランジスタ領域に相当す
る部位には、n+埋込層２９に達するｎウエル領
域３１が形成され、このｎウエル領域３１が
LDMOS４のドレイン領域とされている。 In this embodiment, a p-type epitaxial layer 32 is formed on a p-substrate 1. An n-well region 31 that reaches the n + buried layer 29 is formed in a portion of the p-epitaxial layer 32 that corresponds to the MOS transistor region.
It is considered as the drain region of LDMOS4.
ｎウエル領域３１に対しpn接合分離されたｐ
エピタキシヤル層３２の部分が素子領域とされて
いる。 p-n junction isolated from n-well region 31
A portion of the epitaxial layer 32 is used as an element region.
素子領域におけるｐエピタキシヤル層３２に
は、ｎウエル領域３３が形成され、pMOS６がこ
のｎウエル領域３３内に形成され、nMOS５はｐ
エピタキシヤル層３２内に直接形成されている。 An n-well region 33 is formed in the p-epitaxial layer 32 in the element region, a pMOS6 is formed in this n-well region 33, and an nMOS5 is formed in the p-type epitaxial layer 32.
Formed directly within epitaxial layer 32.
この実施例によれば、ｐエピタキシヤル層３２
の比抵抗は、nMOS５およびpMOS６からなる
CMOSの設計に合つた値に選ぶことができる。 According to this embodiment, the p epitaxial layer 32
The resistivity of is composed of nMOS5 and pMOS6
You can choose a value that suits your CMOS design.
また素子領域の縦方向構造は、ｐエピタキシヤ
ル層３２／ｐ基板１となつているので、ｐエピタ
キシヤル層３２内にｎウエル領域３３を形成して
も、寄生バイポーラトランジスタが構成されるこ
とがない。したがつてツエナダイオード内蔵の
LDMOS４側に高電圧のサージが入力した場合で
あつても、寄生バイポーラトランジスタに起因す
るCMOSの誤動作は生じることがなく動作特性
が向上する。 Furthermore, since the vertical structure of the element region is p epitaxial layer 32/p substrate 1, even if the n well region 33 is formed within the p epitaxial layer 32, a parasitic bipolar transistor cannot be constructed. do not have. Therefore, the built-in Zener diode
Even if a high voltage surge is input to the LDMOS 4 side, the CMOS will not malfunction due to the parasitic bipolar transistor, and its operating characteristics will be improved.
［発明の効果］
以上説明したように、この発明によればドレイ
ン領域となるエピタキシヤル層と基板との間に、
エピタキシヤル層と同一導電形で高不純物濃度の
埋込層を設け、この埋込層およびソース電極に接
続されるように埋込層とは反対導電形で且つ高不
純物濃度のツエナ電圧制御領域を形成したので、
横形MOSトランジスタ内のドレイン・ソース間
には所要のツエナ電圧特性を有するツエナダイオ
ードが形成され、高電圧のサージはこのツエナダ
イオードを介してソースにバイパスされる。した
がつてドレイン領域は、ドレイン耐圧を増大させ
るためにその比抵抗を格別大にする必要がなくな
り、横形MOSトランジスタの動作時のオン抵抗
が低くなるとともに、同一特性の素子であれば横
形MOSトランジスタおよび他の半導体素子を含
めて素子面積を小さくすることができ、チツプ面
積も小さくすることができてコスト低減を図るこ
とができるという利点がある。[Effects of the Invention] As explained above, according to the present invention, between the epitaxial layer serving as the drain region and the substrate,
A buried layer having the same conductivity type as the epitaxial layer and having a high impurity concentration is provided, and a Zener voltage control region having a conductivity type opposite to that of the buried layer and having a high impurity concentration is provided to be connected to the buried layer and the source electrode. Since it was formed,
A Zener diode having required Zener voltage characteristics is formed between the drain and source of the lateral MOS transistor, and high voltage surges are bypassed to the source via this Zener diode. Therefore, the drain region does not need to have a particularly high specific resistance in order to increase the drain withstand voltage, and the on-resistance during operation of the lateral MOS transistor becomes lower, and if the elements have the same characteristics, the lateral MOS transistor There are advantages in that the element area including the semiconductor elements and other semiconductor elements can be reduced, and the chip area can also be reduced, leading to cost reduction.
また基板と同一導電形のエピタキシヤル層を形
成し、このエピタキシヤル層に反対導電形のウエ
ル領域を形成して、これをMOSトランジスタ領
域とし、上記ウエル領域に対してpn接合分離さ
れたエピタキシヤル層の領域を素子領域とした実
施例によれば、上記共通の効果に加えて、素子領
域に特性的により一層優れたCMOS等の半導体
素子を形成することができるという利点がある。 In addition, an epitaxial layer of the same conductivity type as the substrate is formed, a well region of the opposite conductivity type is formed in this epitaxial layer, this is used as a MOS transistor region, and an epitaxial layer separated by a p-n junction from the well region is formed. According to the embodiment in which the region of the layer is used as the element region, in addition to the above-mentioned common effects, there is an advantage that a semiconductor element such as CMOS, which has even better characteristics, can be formed in the element region.
第１図はこの発明に係る半導体装置の一実施例
を一部省略して示す縦断面図、第２図はこの発明
の他の実施例を示す縦断面図、第３図は従来の半
導体装置を示す縦断面図、第４図は他の従来例を
示す縦断面図である。
１……基板、２，３２……エピタキシヤル層、
３……分離領域、４……LDMOS（横形MOSトラ
ンジスタ）、５……nMOS（他の半導体素子）、６
……pMOS（他の半導体素子）、７……チヤンネル
領域、８……ソース領域、９……ゲート酸化膜
（ゲート絶縁膜）、１１……ゲート電極、１２……
ソース電極、１４……ドレイン電極、２７……チ
ヤンネルコンタクト領域、２８……ツエナ電圧制
御領域、２９……埋込層、３１……ウエル領域。
FIG. 1 is a vertical cross-sectional view showing one embodiment of a semiconductor device according to the present invention with some parts omitted, FIG. 2 is a vertical cross-sectional view showing another embodiment of the present invention, and FIG. 3 is a conventional semiconductor device. FIG. 4 is a longitudinal sectional view showing another conventional example. 1... Substrate, 2, 32... Epitaxial layer,
3... Separation region, 4... LDMOS (lateral MOS transistor), 5... nMOS (other semiconductor element), 6
... pMOS (other semiconductor element), 7 ... channel region, 8 ... source region, 9 ... gate oxide film (gate insulating film), 11 ... gate electrode, 12 ...
Source electrode, 14...Drain electrode, 27...Channel contact region, 28...Zena voltage control region, 29...Buried layer, 31...Well region.
Claims (1)
シヤル層を形成し、該エピタキシヤル層の所要部
に前記基板に達する第１導電形の分離領域を形成
して当該エピタキシヤル層をMOSトランジスタ
領域と素子領域とに分離し、 前記MOSトランジスタ領域には、前記基板お
よびドレイン領域となる前記エピタキシヤル層の
間に埋設された第２導電形で且つ高不純物濃度の
埋込層と、該埋込層に達するように前記エピタキ
シヤル層中に形成された第１導電形のチヤンネル
領域と、該チヤンネル領域内に形成された第２導
電形のソース領域と、該ソース領域および前記エ
ピタキシヤル層間における前記チヤンネル領域上
にゲート絶縁膜を介して配設されたゲート電極
と、前記ソース領域に接続されたソース電極と、
該ソース電極および前記埋込層に接続されるよう
に前記チヤンネル領域内に形成された第１導電形
で且つ高不純物濃度のツエナ電圧制御領域とを有
する横形MOSトランジスタを形成し、 前記素子領域には他の半導体素子を形成したこ
とを特徴とする半導体装置。[Scope of Claims] 1. An epitaxial layer of a second conductivity type is formed on a substrate of a first conductivity type, and an isolation region of a first conductivity type reaching the substrate is formed in a required portion of the epitaxial layer. The epitaxial layer is separated into a MOS transistor region and an element region, and the MOS transistor region has a second conductivity type and high impurity concentration buried between the substrate and the epitaxial layer serving as a drain region. a buried layer, a channel region of a first conductivity type formed in the epitaxial layer to reach the buried layer, a source region of a second conductivity type formed in the channel region, and a source region of a second conductivity type formed in the channel region; a gate electrode disposed on the channel region between the region and the epitaxial layer via a gate insulating film, and a source electrode connected to the source region;
forming a lateral MOS transistor having a first conductivity type and high impurity concentration Zener voltage control region formed in the channel region so as to be connected to the source electrode and the buried layer; is a semiconductor device characterized by forming another semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61059278A JPS62217664A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61059278A JPS62217664A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62217664A JPS62217664A (en) | 1987-09-25 |
| JPH0553074B2 true JPH0553074B2 (en) | 1993-08-09 |
Family
ID=13108755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61059278A Granted JPS62217664A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62217664A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5192989A (en) * | 1989-11-28 | 1993-03-09 | Nissan Motor Co., Ltd. | Lateral dmos fet device with reduced on resistance |
| US5701023A (en) * | 1994-08-03 | 1997-12-23 | National Semiconductor Corporation | Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness |
| JP5183835B2 (en) * | 2000-11-02 | 2013-04-17 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
| JP4387865B2 (en) | 2004-05-14 | 2009-12-24 | パナソニック株式会社 | Semiconductor device |
| JP4150704B2 (en) * | 2004-07-16 | 2008-09-17 | 新電元工業株式会社 | Horizontal short channel DMOS |
| DE102007012380A1 (en) | 2007-03-14 | 2008-09-18 | Austriamicrosystems Ag | Channel-connected MOSFET and method of making a channel-connected MOSFET |
-
1986
- 1986-03-19 JP JP61059278A patent/JPS62217664A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62217664A (en) | 1987-09-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4862233A (en) | Integrated circuit device having vertical MOS provided with Zener diode | |
| US6552597B1 (en) | Integrated circuit with closely coupled high voltage output and offline transistor pair | |
| US5323044A (en) | Bi-directional MOSFET switch | |
| US4893157A (en) | Semiconductor device | |
| US20060118860A1 (en) | Semiconductor device | |
| US7087973B2 (en) | Ballast resistors for transistor devices | |
| JPH11284175A (en) | Mos type semiconductor device | |
| US6876041B2 (en) | ESD protection component | |
| US20160043067A1 (en) | Semiconductor device | |
| JPS61182264A (en) | Vertical type mos transistor | |
| JPH04768A (en) | Mos semiconductor device | |
| US6878996B2 (en) | MOS power transistor | |
| US5903034A (en) | Semiconductor circuit device having an insulated gate type transistor | |
| US5072267A (en) | Complementary field effect transistor | |
| JP2954854B2 (en) | Integrated circuit chip | |
| US4969020A (en) | Semiconductor device | |
| JP3444263B2 (en) | Insulated gate semiconductor device with built-in control circuit | |
| JPH11163336A (en) | Semiconductor device | |
| JPH03180074A (en) | Semiconductor device | |
| JPH0553074B2 (en) | ||
| JPH0758331A (en) | Semiconductor device | |
| US6809393B1 (en) | Level shifter | |
| JP3389782B2 (en) | Semiconductor device | |
| JPH0817234B2 (en) | Semiconductor integrated circuit | |
| JPS62235785A (en) | Veritical field-effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |