JPH0196959A - Semiconductor device - Google Patents

Abstract

PURPOSE:To protect the gate insulating film of a MOSFET against high voltage static electricity and to obtain a protecting device in which the gate oxide film of a protecting element does not break down by employing an inter layer film as the gate insulating film, forming a resistor of the same N-type high concentration impurity layer as that of the drain electrode of a first protecting device, and further forming a surface breakdown type MOSFET of the impurity layer. CONSTITUTION:An N-type high concentration impurity layer 107 is connected to a conductive layer 101 of an input terminal, and the adjacent region of the layers 107 and 108 is covered with the layer 101, thereby forming a parasitic MOSFET of a thick gate oxide film. Further, an N-type high concentration impurity layer 108 is connected to a conductive layer 103 secured to a ground potential. The gate electrode of a MOSFET for surface breaking down a thin gate oxide film 100 is provided on the other region of the layer 107, and fixed to the ground potential. A gate electrode 110 is connected to a conductive layer 102. A P-well 109 is connected through a P-type high concentration impurity layer 106 to the layer 103, and fixed to the ground potential. Further, an N-type substrate is connected to a conductive layer 104 fixed to a power source potential.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices, particularly MTS (hereinafter referred to as MOS transistors) such as insulated gate field transistors (hereinafter referred to as MOS transistors).
Metal In5u1. ator Sem1. con
The present invention relates to a protection device for a ductor-type cord.

[Conventional technology]

Conventionally known protection devices include the patent application 1986-10
As described in No. 7678, a method was used in which the source of a MOSFET whose gate was fixed at a contact potential was grounded, and its drain was connected to an output terminal via a protective resistor.

[Problem that the invention seeks to solve]

The problems with the conventional technology are shown in Figures 2 and 3 below.

This will be explained using FIG. FIG. 2 is a circuit diagram of the prior art. In the conventional technology, a protective resistor 21 and a MOSFET 22 prevent the gate oxide film of the MOSFET 23 from being destroyed due to static electricity applied to the terminal 24.
The aim is to prevent this by a combination of the following. Here 22
MOSFETs do not work during normal circuit operation, but when a high voltage is applied, so-called surface breakdown occurs, causing a large current to flow between the drain and source. Therefore, static electricity applied to terminal 24 passes through 21.

Since it is bypassed by MOSFET 22, 23
This can prevent high voltage from being applied to the gate insulating film of the MOSFET. Here, the protective resistance of 21 is 2
It works to reduce the current flowing to the second MOSFET.

FIG. 3 shows a cross-sectional structural diagram of MOS FET 22. A p-well 35 is provided on the surface of an n-type substrate 36, and an n-type high concentration impurity region 31.degree. 32 is located on the surface thereof. Also, J, (there is an electrode 37 and an insulating film 38 on the upper part of the body, 31.37.
32 as drain and gate, respectively.

A MOSFET used as a source is formed. On the other hand, 33
is an n-type high concentration impurity layer, which is provided to fix the potential of the p-well 35 to the ground potential, and the n-type high concentration impurity layer 34 is provided to fix the potential of the n-type substrate 36. ing.

FIG. 4 shows the voltage-current characteristics of the drain terminal 39 of the device shown in FIG. 3 relative to the ground potential.

When a voltage is applied to the terminal 39, the junction consisting of 31 and 35 breaks down at a point indicated by A. The surface of the junction 31 and 35 is covered with the gate electrode structure 37 and 38, so that breakdown of the junction occurs at a lower voltage than in a normal junction, so-called surface breakdown.

After surface breakdown occurs, the 31.35.32 npn structure exhibits bipolar operation as shown by B, and the drain voltage decreases.

Further increasing the current causes the source as shown by the 0 point.

The voltage increases due to drain parasitic resistance and other effects.

Further, the impurity layers 31, 35, 36 in FIG. 3 also have a vertical npn structure, and when a voltage is applied to the terminal 39 with the terminal 41 at the ground potential, a parasitic bipolar operation occurs between the terminal 39 and the power supply terminal 41. 6 Normally, the power supply terminal and the ground terminal are connected with a large capacitance of about 1000 pF or more, and the transient This vertical bipolar operating current plays an important role in bypassing static electricity.

As mentioned above, the conventional method can be said to be superior due to the use of surface breakdown, but in recent years MOSFET
The following problems have arisen with regard to thinning of the gate oxide film of ET.

First, in Fig. 1, the MOSFET terminal 22 shown in Fig. 2 is connected.
When a large current flows due to static electricity applied to the terminal, the voltage at the terminal 25 increases due to the internal resistance shown at point 0,
The problem is that the gate insulating film of MOSFET No. 23 may be destroyed. In order to prevent this, there is a method of increasing the resistance by 21, but this requires increasing the size of the resistor, which increases the occupied area and also reduces the signal propagation speed from terminal 24 to terminal 25 in the original circuit operation. The problem arises of increasing

The second problem is that because the MOSFET of the protection element 22 itself uses a thin gate insulating film 38 in FIG. 3, the gate insulating film of the protection element is destroyed by static electricity.

The purpose of the present invention is to solve the above problems, protect the gate insulating film of MOSFET from high voltage static electricity, and
It is an object of the present invention to provide a protection device that does not destroy the gate oxide film of the protection element itself.

[Means for solving problems]

The above objective is achieved by taking the following measures.

First, the first-stage gate electrode of the protection device uses an electrode for wiring, and the gate insulating film uses its interlayer film.

Second, a resistor is made using the same n-type high concentration impurity layer as the drain electrode of the first protection device.

Third, a surface breakdown type MOSFET using the above n-type high concentration impurity layer is fabricated.

Fourth, a resistor made of a conductive layer is inserted between the first protection device and the input terminal.

Fifth, the resistance of the high concentration impurity layer provided outside the well is reduced by a conductive layer.

[Effect]

The above means has the following effects.

In the MOSFET using the first R'I interlayer, the gate insulating film of the protection element is thick, so that breakdown of the gate insulating film of the protection element itself can be prevented. However, since the first element is not of the surface breakdown type, the voltage at the drain terminal cannot be lowered sufficiently. Therefore, by creating a resistor using the second impurity layer resistor and further creating a third surface breakdown type MOSFET, M
The voltage at the drain of the OSFET can be lowered sufficiently. At this time, the second impurity layer resistance has the effect of reducing the current flowing through the third surface breakdown type MOSFET and reducing the voltage applied to the gate oxide film of the third MOSFET.

Further, by making this resistor common to the drains of the first and third MO3FIETs, a sufficiently large resistor can be obtained with a small area.

The resistance provided by the fourth conductive layer has the effect of preventing the drain junction from being thermally destroyed due to a large current flowing through the first MOSFF, T.

Further, by lowering the resistance of the heavily doped impurity layer provided outside the fifth well, it is possible to prevent the potential of the drain terminal from rising due to the current flowing toward the power supply terminal and the resistance of the heavily doped impurity layer.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a layout diagram of a first embodiment of the present invention.

In this embodiment, in order to simplify the explanation, a case will be described in which a p-well is formed on an n-type substrate. In the figure, 109 is a p-well region.

107 and 108 are n-type high concentration impurity layers, and 107
108 are adjacent to each other. , the n-type high concentration impurity layer 107 is connected to the conductive layer 101 of the input terminal through the contact hole 114.
The adjacent regions of 07 and 108 are covered to form a parasitic MO3FET with a thick gate oxide film. Further, the n-type high concentration impurity region 108 is connected to the conductive layer 103 fixed at a ground potential through a contact hole 113.

On the other hand, in other regions of the conductive fllt layer 107, M is 110.
MOS that performs surface breakdown operation of thin gate oxide film
A gate electrode of the FET is provided and fixed to the ground potential through a contact hole 117. A contact hole 123 is provided near the gated tf 411 and connected to the conductive layer 102 . The p-well 109 includes a p-type high concentration impurity layer 106 and a contact hole 12.
It is connected to the conductive layer 103 through 1, 118, 116, and 112, and is fixed to the ground potential. Further, the n-type substrate is connected to a conductive layer 104 fixed at a power supply potential through contact holes 122, 110, 115, and 111.

In the case of this embodiment 1, in normal operation, an input signal is transmitted from the input terminal through the conductive tti layer 101, through the high concentration impurity layer 107, and to the conductive layer 102.

FIG. 5 shows a sectional view of the first embodiment. Each symbol corresponds to the symbol in FIG. Conductive layer 1
When static electricity is applied to 01.

107. n p n structure consisting of 109, 108 and 1
The npn structure consisting of 07.109 and 124 causes bipolar operation, and currents j^ and jB flow.

It shows the time change of the current level, the bipolar operating current i^, and the time change of the bipolar operating current i^. When static electricity with a certain charge is applied to node A, 1.07,109,1
Since the npn structure consisting of 08 performs bipolar operation, a very large current i^ flows. At this time, a parasitic resistance exists in the bipolar element and a potential difference is generated between it and i^, so that the node A has a considerably high potential. Since the gate insulating film in this part is an interlayer insulating film between conductive layers, sufficient dielectric strength is ensured, and this part will not be damaged (A). However, as shown in No. 6, the voltage at point A exceeds the withstand voltage of the gate oxide film, so it is insufficient as a protection device for the gate oxide film. Therefore, a MO5FIET with a gate electrode of 110 is provided. At this time, the current flowing through the MOSFET is limited by the resistance caused by the impurity layer 107.

The potential at node B is kept low, and the potential at point B is also kept low. In this embodiment, the resistance due to the impurity layer 107 plays an important role as described above. This resistor may be a resistor made of a conductive layer, but this requires a large area. However, as shown in FIG. 5, by making the n-type high-density impurity layer that serves as a resistor common to the drains of the two M(l SFETs), there is an effect of reducing the required area.On the other hand, - In boat fishing, there is a large parasitic capacitance between the power supply potential terminal and the ground potential terminal, and the potential of the base body is transiently grounded in an alternating current manner.Therefore, 107°1
09, a current ic flows into the conductive layer 105 due to the npn sliding structure made of the base. Since this jc has the function of reducing i^ and iB, the structure that makes it easier to flow through IC has the function of strengthening the protection element. In this embodiment, the resistance of the impurity layer 105 is reduced by the 4 ri layer 104, and the jc
This has the effect of making the protective element stronger by making it easier to flow.

A layout diagram of a second embodiment of the present invention is shown in FIG.

In this embodiment, the input terminal 125 is connected to the conductive layer 101 through the resistor 124 made of a conductive layer. This has the effect of reducing the node terminal voltage even more than the embodiment.

A layout diagram of the third embodiment of the present invention is shown in FIG. 8, and an equivalent circuit is shown in FIG. 9. In this example, the impurity layer is 1.07
A parasitic MO5 FIET is provided at the boundary between the impurity layer 108 and the impurity layer 107, and the boundary between the impurity layer 107 and the impurity layer 127, the gate of the former is the input conductive layer 101, and the gate of the latter is the conductive N, layer that provides the fri source potential. It is 104.

Further, the impurity layer 108 is a conductive layer 103 that provides a ground potential.
The impurity layer 127 is connected to the conductive layer 104 that provides a power supply potential. On the other hand, in the other part of the impurity layer 107, there is an N08FI layer with the conductive layer 110 as a gate electrode.
An ET is formed, the source of which is fixed at ground potential. The conductive layer 110 itself serves as a resistor, and is fixed to the ground potential through this resistor. A constriction is formed between the MOSFET region and the parasitic MO3FET region, forming a resistor. Also MO
The potential of the drain of the SFET is taken out to the outside by a conductor ff1W 124.

In the equivalent circuit of FIG. 9, when static electricity is applied from the input terminal 200, current flows through the parasitic MOs 5201 and 202 to the ground terminal and the power supply terminal. The static electricity will further flow to the MO8FET 205 through the impurity layer resistor 204.

In this embodiment, since the parasitic MO3FET is connected not only to the ground terminal but also to the power supply terminal, the current flowing through the parasitic MO5FHT connected to the ground terminal is reduced, suppressing the rise in potential of the node 208. Can be done. Furthermore, since the resistor 204 is formed by utilizing the constriction of the impurity layer 107, the required resistance value can be achieved with a small area.

Also, the resistance value 209 is set to prevent the gate insulating film of the MOSFET 205 from being destroyed.
The gate electrode can be fixed at ground potential without affecting normal circuit operation. FIG. 10 shows a sectional view of a portion 10 of the parasitic MO 8 of this embodiment. When static electricity is applied to the node 200, the n of the impurity layers 107, 109°130
Due to the p n structure, an impurity layer 107.1 is added to the ground terminal.
They are bypassed to the power supply terminals by the npn structures of 09 and 108, respectively.

FIG. 11 shows a fourth embodiment of the present invention. In this embodiment, resistors 211 and 210 are connected in series to the source side of the parasitic MnS2 and the drain side of the parasitic NO5, respectively. These resistances can be provided by adjusting the resistance of each impurity layer.

In the case of this embodiment, since there are resistors 210 and 21.1,
The current flowing through the parasitic MO8FETs 201 and 202 is reduced, which has the effect of preventing the parasitic MO5FETs 201 and 202 from being thermally destroyed.

FIG. 12 shows a fifth embodiment of the present invention. "In this embodiment, the td level of the gate electrode of the parasitic MO5FF T 202 is fixed to the input terminal 200 or the ground potential. However, the drain electrode of the parasitic MO5FIET 202 is connected to the power supply terminal, and static electricity is transferred to the power supply terminal side. Since it can be bypassed, it has the same effect as the third embodiment, resulting in a structure that is resistant to electrostatic damage.

FIG. 13 shows a circuit diagram of a sixth embodiment of the invention, and FIG. 14 shows a circuit diagram of a seventh embodiment of the invention.

In both methods, the potentials of the gate electrodes of the parasitic MO520] and 2o2 are different, but the source of the parasitic MO8201 is connected to the ground terminal, and the drain of the parasitic MQS202 is connected to the ijy source terminal terminal, so they are similar to the third embodiment. This makes the structure resistant to electrostatic damage.

〔Effect of the invention〕

As a method for preventing electrostatic damage of a protection element, a method is widely used in which a charge charged to a capacitance of 1000 pF is applied to the protection element through a resistor of 1.5 Ω.

According to the present invention, it is possible to provide a protection element that has approximately the same area as the conventional method and is resistant to about twice as much charge.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of the first embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional method, and FIG. 3 is a sectional view of a conventional method.
FIG. 4 is a diagram showing the operation of the conventional method. FIG. 5 is a sectional view of the first embodiment of the present invention, FIG. 6 is a diagram showing the operation of the present invention, FIG. 7 is a layout diagram of the second embodiment of the present invention, and FIG. 8 is a diagram of the present invention. FIG. 9 is a layout diagram of the third embodiment of the present invention, FIG. 9 is a circuit diagram of the third embodiment of the present invention, and FIG.
The figure is a cross-sectional view of the parasitic MO8 part of the third embodiment of the present invention,
11 is a circuit diagram of a fourth embodiment of the present invention, FIG. 12 is a circuit diagram of a fifth embodiment of the present invention, FIG. 13 is a circuit diagram of a sixth embodiment of the present invention, and FIG. The figure is a circuit diagram of a seventh embodiment of the present invention. 101... Electrocardiographic layer, 102... Conductive layer, 104...
・Conductive layer, 107, 108-n type highly concentrated impurity layer, 109
Figure 1 Figure 2 Figure 3 Figure 4 D Figure 5 Figure 4 7121 Figure 8/29 Jun 9 Figure Kaya ) 1 Figure cc Bud 12 I\1 V131\1 rA) (Snake) Figure 14 CB)

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a first well region of a second conductivity type provided in a surface region of the semiconductor substrate, and a first well region provided in the first well region. a first insulating film having one insulating film;
a first insulated gate transistor of a conductivity type; a second insulated gate transistor having a first insulating film of a second conductivity type formed on a surface region of the semiconductor substrate; and a second insulated gate transistor provided through a second insulating film. In a semiconductor device comprising a second conductive layer for interconnection, a first impurity region of a first conductivity type provided on a further surface of the first well region is fixed at a ground potential or a power supply potential. A second impurity region of the first conductivity type adjacent to the first impurity region is connected to an external terminal, and a second conductivity type is connected to the boundary between the first impurity region and a part of the second impurity region. A parasitic MOSFET is formed by forming a parasitic MOSFET, the second conductive layer is fixed to the external terminal potential, the ground potential, or the power supply potential, and the other part of the second impurity region is a third conductive layer of the second conductivity type. The third impurity region of the first conductivity type becomes the drain of the third MOSFET.
A semiconductor device characterized in that a source electrode of an SFET is fixed to a ground potential, and a gate electrode of a third MOSFET is fixed to a ground potential. 2. Between the impurity region described in item 1 above and the external terminal,
A semiconductor device characterized by comprising a resistance formed by a conductive layer. 3. A third impurity region of the first conductivity type is provided on the surface of the semiconductor substrate around the well region described in item 1 above, and a low resistance conductive layer fixed to a power supply potential is provided on the third impurity region. A semiconductor device characterized in that the low resistance conductive layer and a third impurity region are in contact with each other. 4. A semiconductor device characterized in that the gate electrode of the MOSFET according to item 3 above is fixed to a ground potential through a resistor made of the same conductive layer as the gate electrode.