JPS6384964U - - Google Patents
Info
- Publication number
- JPS6384964U JPS6384964U JP1986178954U JP17895486U JPS6384964U JP S6384964 U JPS6384964 U JP S6384964U JP 1986178954 U JP1986178954 U JP 1986178954U JP 17895486 U JP17895486 U JP 17895486U JP S6384964 U JPS6384964 U JP S6384964U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- gate electrode
- read
- boundary
- mos transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Description
第１図は本考案の一実施例の半導体装置の要部
構成図、第２図は本考案の一実施例の半導体装置
の製造工程図、第３図、第４図は従来例の説明図
である。
１……半導体基板、２……酸化膜、３……ゲー
ト電極（アドレスライン）、４……拡散領域、５
……層間絶縁膜、６……アルミニウム配線層（読
み出しライン）、７……レジスト。
FIG. 1 is a block diagram of the main parts of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention, and FIGS. 3 and 4 are explanatory diagrams of a conventional example. It is. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Oxide film, 3... Gate electrode (address line), 4... Diffusion region, 5
...Interlayer insulating film, 6...Aluminum wiring layer (readout line), 7...Resist.
Claims (1)
リセル内の少なくとも１つのＭＯＳトランジスタ
のゲート電極に欠切部を設けて、該ＭＯＳトラン
ジスタの少なくとも一方の拡散領域の境界とゲー
ト電極の側壁境界をずらしてゲート電圧閾値が異
なるＭＯＳトランジスタを有することを特徴とす
る読み出し専用メモリ半導体装置。 In a read-only memory semiconductor device, a notch is provided in the gate electrode of at least one MOS transistor in a memory cell, and the boundary of the diffusion region of at least one of the MOS transistors is shifted from the sidewall boundary of the gate electrode to adjust the gate voltage threshold. 1. A read-only memory semiconductor device comprising MOS transistors with different values.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986178954U JPS6384964U (en) | 1986-11-20 | 1986-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986178954U JPS6384964U (en) | 1986-11-20 | 1986-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6384964U true JPS6384964U (en) | 1988-06-03 |
Family
ID=31121572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986178954U Pending JPS6384964U (en) | 1986-11-20 | 1986-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6384964U (en) |
-
1986
- 1986-11-20 JP JP1986178954U patent/JPS6384964U/ja active Pending
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