JPH0275751U - - Google Patents

Description

[Brief explanation of drawings]

The drawing is a side sectional view of a memory cell to which the present invention can be applied. In addition, in the symbols used in the drawings, 12...nM
OS transistor, 13...n ⁺ diffusion layer, 14...
...n ⁺ diffusion layer, 16...n ⁺ polycrystalline Si layer, 18
... Insulating film, 21 ... Polycrystalline Si thin film, 22 ...
p ⁺ diffusion layer, 23...p ⁺ diffusion layer, 24...pM
It is an OS transistor.

Claims (1)

[Claims for Utility Model Registration] 1. In a semiconductor memory in which a memory cell is configured using a flip-flop consisting of a pair of CMOS transistors, first and second conductivity type MOS transistors of the CMOS transistors share a gate electrode. the first conductivity type MO in a layer below the gate electrode;
A source/drain region of an S transistor is formed, a source/drain region of the second conductivity type MOS transistor is formed in a semiconductor layer above the gate electrode, and a source/drain region of the second conductivity type MOS transistor is formed. A semiconductor memory in which at least a semiconductor nitride film is formed as a gate insulating film between the gate electrode and the semiconductor layer. 2. The semiconductor memory according to claim 1, wherein the gate insulating film is a three-layer film of a semiconductor oxide film, a semiconductor nitride film, and a semiconductor oxide film.